309results about "Coding details" patented technology

Methods and apparatus for leveraging transfer learning of one Wireless Transmit / Receive Unit (WTRU) to benefit another WTRU are provided. One method may include the WTRU receiving AI / ML model configuration information indicating one or more AI / ML models available from the network node, a profile associated with the AI / ML models, and a training convergence threshold. Based at least on the profile(s), the WTRU determining that the one or more AI / ML models are not suitable for use by the WTRU, and sending first information indicating that the one or more AI / ML models are not suitable for the WTRU and / or that the WTRU will be training a local AI / ML model. The method may then include training the local AI / ML model according to the convergence threshold, receiving a request to transfer AI / ML model parameters, and sending an indication of the AI / ML model parameters associated with the trained local AI / ML model to the network node.

The invention provides a decoder, a decoding method, a memory system, an operation method of the memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in a current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check matrix, the check formula and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to: determine a flipping threshold in a current iteration based on a change state of the checkout weight; and the bit flipping circuit is configured to output the to-be-decoded code word in the next round of iteration based on a comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value in the current iteration determined by the processor.

This disclosure provides methods, components, devices, and systems for ultra-high reliability (UHR) signaling design. Some aspects more specifically relate to an access point (AP) transmitting a frame including a user info field to a wireless station (STA), where the user info field supports UHR parameters. The user info field may include a subfield indicating a coding scheme for communications, where the subfield includes at least two bits to support at least three coding scheme options. Additionally, or alternatively, the AP may transmit a trigger frame indicating for one or more STAs to communicate via distributed resource units (RUs). The AP may arrange the user info fields in the trigger frame to implicitly indicate respective global cyclic shift delay (CSD) indexes to the STAs. A STA receiving the trigger frame may determine a global CSD index corresponding to the STA according to the order of the user info fields.

A method of encoding data includes determining, by an encoder, a first data instance by corrupting the data with Gaussian noise. The method also includes determining, by the encoder, information representative of one or more conditional distributions. The method additionally includes determining, by the encoder, an index of a corrupted data instance of the sequence of progressively less corrupted data instances. The index corresponds with a conditional distribution of the one or more conditional distributions which causes the corrupted data instance to have a desired bit-rate. The method further includes transmitting, from the encoder to a decoder, the first data instance and the information representative of the one or more conditional distributions to enable the decoder to recover the corrupted data instance having the desired bit-rate and use the corrupted data instance to generate output data representative of the data.

In some implementations, a memory system may obtain, from a host system, a command to read data. The memory system may retrieve a codeword associated with the data. The memory system may generate, based on the codeword, a syndrome. The memory system may generate one or more decoding values based on the syndrome and using one or more combinational circuits. The memory system may correct one or more errors in the codeword using the one or more decoding values. The memory system may provide the data to the host system.

According to disclosed embodiments, methods and systems of data transmission are provided. An aspect of the present disclosure is a method comprising receiving an audio stream, parsing the audio stream into packets, encoding each packet using Alphabet Linear Network Coding (ALNC), and transmitting the encoded packets.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.

Various aspects of the present disclosure generally relate to wireless communication. Some aspects more specifically provide procedures and configurations used to perform, at a transmitter, probabilistic amplitude shaping (PAS) of quadrature amplitude modulation (QAM) communications using non-binary polar coding (NBPC). NBPC differs from binary polar coding (BPC) in that BPC uses a binary-input channel whereas NBPC uses a non-binary input channel. For example, while BPC uses a log likelihood ratio (LLR) with a single value corresponding to a given bit to be shaped, NBPC may use a probability mass function (PMF) to define or represent amplitude shaping target values. As another example, aspects use non-binary transformations, which reduce the number of passes to shape q bits from q passes (for BPC) to 1 pass (for NBPC).

The invention provides a decoder, a decoding method, a memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, wherein the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check formula, the check matrix and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to select a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the checkout weight in the initial iteration; distributing one flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit is configured to output the to-be-decoded code word in the next iteration based on the comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value allocated by the processor.

Methods, systems, and devices for wireless communications are described. An encoding device (e.g., a network entity or user equipment (UE)) can communicate an indication of an encoding symbol identifier (ESI), a source block number (SBN), or both, to a decoding device in downlink control information (DCI). By way of example, the indication of the SBN and / or ESI can be transmitted using either an unused field or a repurposed field in the downlink control information (DCI) that schedules a transmission including the encoding symbols, or in a new DCI piggybacked on a downlink shared channel transmission including the encoding symbols. Additionally or alternatively, in a first option, the ESI can be explicitly indicated by the DCI. In another option, the network entity can indicate (e.g., via radio resource control messaging) a configuration for implicitly determining the ESI based on information conveyed in the DCI.

The embodiments of the present application relates to the technical field of wireless communications. Provided are an encoding method, a decoding method, and an apparatus, which are used for reducing the complexity of decoding. The encoding method comprises: a first communication device acquiring a first sequence, wherein the first sequence is a bit sequence to be encoded, and the first sequence comprises K information bits; and the first communication device encoding the first sequence. If K is less than (or equal to) K1, the first sequence is encoded on the basis of a basic sequence. Alternatively, if K is greater than (or equal to) K1, polar encoding is performed on the first sequence. K1 is a positive integer less than 11. On the basis of the solution, when the number K of information bits is larger (for example, greater than K1), if a basic sequence is used for performing encoding, the complexity of decoding is also larger due to the larger number of mask sequences, and if polarization encoding is used, the complexity of decoding can be reduced.

Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device (WCD) may send an indication of supporting a plurality of parity mapping schemes for communication. The WCD may receive a communication having a first parity mapping scheme and a second parity mapping scheme, the first parity mapping scheme being different from the second parity mapping scheme. Numerous other aspects are described.

The present disclosure provides coding and decoding methods, a communication device, and a storage medium. The coding method, applied to a first transmission node, includes: determining a base matrix for low density parity check (LDPC) coding from a preset base matrix set; performing LDPC coding on original data according to the base matrix, so as to obtain coded data; transmitting the coded data to a second transmission node; wherein the base matrix includes two kinds of elements: an element indicating an all-zero square matrix, and an element indicating a cyclic shift of an identity matrix; the base matrix set includes at least two non-empty subsets of base matrices, and all base matrices in each subset of the at least two non-empty subsets of base matrices have a same coding rate.

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.

A matrix computing method and apparatus are provided. In the method, block division is performed by row on input data of a to-be-multiplied first matrix at a granularity of a subblock whose scale is M×N, to obtain at least one first subblock; and block division is performed by column on input data of a to-be-multiplied second matrix at a granularity of a subblock whose scale is N×R, to obtain at least one second subblock, where all M, N, and R are positive integers. One or more target subblock combinations are determined, where each target subblock combination includes one first subblock and one second subblock, and at least one element in the first subblock and at least one element in the second subblock in each target subblock combination are to-be-multiplied elements. Each of the one or more target subblock combinations is used as input data of a matrix computing apparatus, to obtain a product result of the first matrix and the second matrix that is output by the matrix computing apparatus.

One approach may include at least partially initializing the mesh of the SE engine based at least in part on predetermined state information about the communication channel associated with the incoming data stream; and processing the incoming data stream via the MLSE engine to further initialize the mesh and decode the incoming data stream.

In some aspects, the techniques described herein relate to a method including: receiving a standard error code correction (ECC) matrix, the standard ECC matrix including a portion for checking a payload and a portion for checking a parity of the payload; and extending the ECC matrix to form an extended matrix by adding a plurality of rows and a plurality of columns to form an upper matrix and a lower matrix, wherein the plurality of rows and columns include at least one all zero portion, at least one portion for checking a quantized Knuth (QK) index, and a portion for checking a parity of the QK index.

Methods, systems, and devices for wireless communication are described herein. An encoding device (e.g., a network entity or user equipment (UE)) may transmit an indication of a coded symbol identifier (ESI), a source block number (SBN), or both, with a decoding device in downlink control information (DCI). For example, the indication of SBN and / or ESI may be transmitted using an unused or re-used field in downlink control information (DCI) that schedules transmissions including encoded symbols or in a new DCI that carries on downlink shared channel transmissions including encoded symbols. Additionally or alternatively, in the first option, the ESI may be explicitly indicated by the DCI. In another option, the network entity may indicate (e.g., via radio resource control messaging) a configuration for implicitly determining the ESI based on information communicated in the DCI.

An apparatus has processing circuitry 2 to perform data processing in response to instructions; at least one control storage element 74 to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry 70 to generate a checksum based on at least one item of internal state stored in the at least one control storage element 74. The checksum is stored in a diagnostic storage location 72 from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and / or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

The present invention provides a device, method, and non-temporary computer-readable medium for rate matching and transmitting transport blocks (TBoMS) spanning multiple slots. [Solution] Method 800 includes determining the starting position of at least one redundant version of a transport block in a circular buffer based at least partially on the position of another redundant version of the transport block in a circular buffer, and transmitting another redundant version and / or one or more of the at least one redundant version using the determined starting position of the at least one redundant version of the transport block, 820 where only one of the at least one redundant version is transmitted, multiple redundant versions of the at least one redundant version are transmitted, or several of the other redundant versions and the at least one redundant version are transmitted.

Memory controllers and memory systems including the same are disclosed. The memory controller is configured to control a memory module, the memory controller comprising: processing circuitry configured to: perform ECC decoding of a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicative of the type of error.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may transmit, via a first transmission of a hybrid automatic repeat request (HARQ) procedure, a first set of information bits, wherein the first set of information bits are encoded into a first polar codeword of a first size. The wireless communication device may transmit, via a second transmission of the HARQ procedure, the first set of information bits and a second set of information bits, wherein the first set of information bits and the second set of information bits are jointly encoded into a second polar codeword of a second size. Numerous other aspects are described.

Incoming sensor data from a data collection device may be received at the data processing platform that includes the plurality of data processing microservices. A data processing microservice of the data processing platform may detect that the incoming sensor data from the data collection device caused an error. As a result, the incoming sensor data may be queued in a faulty data cache of the data processing platform. Subsequently, at least one of the data processing microservice or the incoming sensor data stored in the faulty data cache may be modified such that the incoming sensor data is processed by the data processing microservice without the error. Following the processing, the incoming sensor data may be deleted from the faulty data queue of the data processing platform.

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.

An error correction circuit includes an error processing circuit, a poison processing circuit, and a data pattern conversion circuit. The error processing circuit receives data, generates delayed data, a parity signal, and syndrome information, and outputs error correction data generated by correcting errors in the data according to the syndrome information. The poison processing circuit outputs one of a write poison flag and a read poison flag as a poison pattern control signal in accordance with a write command. The data pattern conversion circuit converts the delayed data and the parity signal into a poison pattern according to the poison pattern control signal and outputs the poison pattern.

An apparatus may include a transmitter. The apparatus may identify a target code rate and a low density parity check (LDPC) code that has a base code rate for a base size of information bits, select, based at least on the target data rate and the base code rate, a first size that is less than the base size of information bits, generate a second set of information bits to include a first set of information bits corresponding to the first size and one or more bits to increase a size of the second set of information to correspond to the base size of information bits, encode, using the base code rate, the second set of information bits to generate parity data, and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate. The transmitter may transmit the codeword.

The present disclosure disclose decoders, decoding methods, memory systems, memory controllers and computer readable storage medium. The decoder comprises a first data processing circuit and a second data processing circuit coupled to the first data processing circuit; the first data processing circuit is configured to: perform a current check calculation using a current column of a check matrix and a current sub-matrix of a current flag matrix, and perform a current incremental check calculation on a result of the current check calculation and a previous syndrome to generate a current syndrome; the second data processing circuit is configured to: determine an error symbol in a next data block of the codeword, using one of the current syndrome or a previous syndrome and a next column of the check matrix, based on the current syndrome not satisfying a check condition; wherein the previous syndrome is generated prior to the current syndrome.

This application provides a rate matching method and a communication apparatus. A transmit end punctures an LDPC codeword based on a priority order of check bits of a mother code of an LDPC code. The priority order of the check bits of the mother code indicates a priority order of puncturing the check bits in a rate matching process, and the priority order is related to confidences of the check bits. The confidences of the check bits indicate degrees to which the check bits are affected by noise in a channel transmission process. In addition, puncturing the check bits can ensure restorability of a system variable node, and a check bit with a higher confidence is more likely to be correctly restored, so that more valid information can be provided for another system variable node during decoding iteration. Therefore, in this application, it is considered that a check bit with a high confidence is preferentially punctured, to provide more valid information for another system variable node in an iterative decoding process, thereby improving decoding performance of a receive end.

The invention relates to a device and a method for error correction in resistive memories or flash memories, protected by an error correcting code which allows the correction of at least two erroneous bits per code word stored in memory. The device combines a correction module capable of correcting up to r-1 erroneous bits per code word, and a detection module for checking the number of erroneous bits per code word. The detection module is arranged to detect whether the read code word comprises at most r-1 erroneous bits, and if not, to initiate a sequence of decoding operations on a succession of words each of which comprises a single bit inverted with respect to the read code word. A check is then made to verify whether the number of erroneous bits in the version of the code word with inversion of one bit has become correctable. As soon as this condition is satisfied, the code word can be corrected. Figure for abstract: Fig. 1