601results about "Coding details" patented technology

Methods and apparatus for leveraging transfer learning of one Wireless Transmit / Receive Unit (WTRU) to benefit another WTRU are provided. One method may include the WTRU receiving AI / ML model configuration information indicating one or more AI / ML models available from the network node, a profile associated with the AI / ML models, and a training convergence threshold. Based at least on the profile(s), the WTRU determining that the one or more AI / ML models are not suitable for use by the WTRU, and sending first information indicating that the one or more AI / ML models are not suitable for the WTRU and / or that the WTRU will be training a local AI / ML model. The method may then include training the local AI / ML model according to the convergence threshold, receiving a request to transfer AI / ML model parameters, and sending an indication of the AI / ML model parameters associated with the trained local AI / ML model to the network node.

Techniques are disclosed for reducing overhead during hybrid automatic repeat request (HARQ) operations performed by a user equipment (UE) during wireless communication. The UE receives a message over the wireless network and obtains a parity check matrix (PCM) associated with a received message. Rows of the PCM are assigned to respective groups of a plurality of groups, where the respective groups have corresponding one or more parity checks as determined by the PCM. The UE generates a feedback message including a plurality of bits, wherein an individual bit of the plurality of bits indicates whether a corresponding respective group of the plurality of groups include one or more unsatisfied parity checks. The UE then transmits the feedback message to a base station of the wireless network.

The embodiment of the invention discloses a data processing method and a related device, which are used for realizing inner code coding with higher gain, improving the performance of cascade coding and being beneficial to being applied to a 1.6 T ZR scene. Specifically, a coded data frame subjected to outer code coding is obtained, the coded data frame comprises v bits, and v is an integer greater than 1. Afterwards, a first bit set is obtained according to the coded data frame and the added dpad filling bits, the number of bits in the first bit set is v + dpad, and dpad is an integer greater than or equal to 1; next, performing convolutional interleaving on the first bit set to obtain a second bit set; and further, performing inner code coding on the second bit set to obtain a third bit set. The third bit set comprises R code words coded by the second FEC, each code word comprises N bits including K information bits and N-K check bits, R, N and K are all integers greater than 1, v + dpad = R * K, and dpad cannot be exactly divided by K.

The invention provides a decoder, a decoding method, a memory system, an operation method of the memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in a current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check matrix, the check formula and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to: determine a flipping threshold in a current iteration based on a change state of the checkout weight; and the bit flipping circuit is configured to output the to-be-decoded code word in the next round of iteration based on a comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value in the current iteration determined by the processor.

A method for decoding a memory system, the method may include establishing a plurality of check nodes and a plurality of variable nodes corresponding to the plurality of check nodes of a codeword; setting a preliminary operation speed based on a progress rate of a preliminary operation for generating predictive error information of each of the plurality of the variable nodes; performing the preliminary operation according to the preliminary operation speed; and performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.

This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a variable node that corresponds to a first data bit in a block of data, and obtains check node data from each check node. A hard decision likelihood is determined based on a check node data set including the check node data of each of the set of check nodes. The electronic device dynamically determines an adjustment factor based on the hard decision likelihood. Variable node data is determined for each of the set of check nodes based on the adjustment factor. In some embodiments, each check node is configured to verify validity of a set of data bits including the first data bit, and the check node data of each of the set of check nodes indicates a likelihood of the set of data bits being erroneous.

A device and a method for reading a code word in a resistive memory protected by an ECC where each memory cell includes resistive devices for storing a bit of a code word. The method allows the selection, as a function of the value of a syndrome, of a corrected word following a first decoding process without inversion of weak-bits or of a corrected word following a second decoding process with inversion of weak-bits. If the computed syndrome determines that the first decoding process has indicated an uncorrectable error or determines that the second decoding process has indicated neither an uncorrectable error nor an n-error (i.e., a maximum of n erroneous bits per code word), the selected word is the corrected word with inversion of the weak-bits. Otherwise, the selected word is the corrected word without inversion of the weak-bits.

This disclosure provides methods, components, devices and systems for managing long low-density parity check (LDPC) codewords in ultra high reliability (UHR) systems. One method for wireless communication may be performable at a transmitter device or node. The method may include transmitting signaling to a receiver device or node indicating that the transmitter device supports use of a first LDPC codeword length that is greater than or equal to a threshold LDPC codeword length. The method may further include transmitting an LDPC codeword of the first LDPC codeword length (e.g., a long LDPC codeword) to the receiver device when one or more conditions are satisfied.

The embodiment of the invention discloses a communication method and a communication device, relates to the technical field of communication, and is used for meeting the transmission requirement of a high throughput scene. The method comprises the following steps: determining a physical channel of a first scene, wherein the throughput of the first scene is greater than a preset threshold; and under the condition that the transmission layer number of the physical channel is greater than the preset layer number, transmitting data in a single code word form.

A memory may include: a memory core; an error correction code (ECC) engine configured to generate an error correction code to be stored in the memory core together with write data by using the write data during an encoding operation, and to correct an error of read data read from the memory core using the error correction code read from the memory core during a decoding operation; and an error determination circuit configured to determine that during the encoding operation, a 1-bit error exists when upper index portions of syndromes generated by the ECC engine have odd weights, and to determine that a correctable 2-bit error exists when the upper index portions of the syndromes are one of predetermined even weight patterns.

In the matrix computing method, block division is performed by row on input data of a to-be-multiplied first matrix at a granularity of a subblock whose scale is M×N, to obtain at least one first subblock; and block division is performed by column on input data of a to-be-multiplied second matrix at a granularity of a subblock whose scale is N×R, to obtain at least one second subblock. One or more target subblock combinations are determined, where each target subblock combination includes one first subblock and one second subblock, and at least one element in the first subblock and at least one element in the second subblock in each target subblock combination are to-be-multiplied elements. Each of the one or more target subblock combinations is used as input data of a matrix computing apparatus, to obtain a product result of the first matrix and the second matrix.

The embodiment of the invention provides a communication method and device, relates to the field of communication, and can realize channel coding of low-complexity terminal equipment. The communication method comprises: a terminal device receiving first information, the first information indicating the terminal device to send an uplink signal, an input bit sequence of the uplink signal being a first bit sequence; and a pre-stored second bit sequence is output, and the second bit sequence is obtained by arranging bit sequences obtained after channel coding is carried out on the first bit sequence according to a predefined sequence.

This disclosure provides methods, components, devices, and systems for ultra-high reliability (UHR) signaling design. Some aspects more specifically relate to an access point (AP) transmitting a frame including a user info field to a wireless station (STA), where the user info field supports UHR parameters. The user info field may include a subfield indicating a coding scheme for communications, where the subfield includes at least two bits to support at least three coding scheme options. Additionally, or alternatively, the AP may transmit a trigger frame indicating for one or more STAs to communicate via distributed resource units (RUs). The AP may arrange the user info fields in the trigger frame to implicitly indicate respective global cyclic shift delay (CSD) indexes to the STAs. A STA receiving the trigger frame may determine a global CSD index corresponding to the STA according to the order of the user info fields.

A method of encoding data includes determining, by an encoder, a first data instance by corrupting the data with Gaussian noise. The method also includes determining, by the encoder, information representative of one or more conditional distributions. The method additionally includes determining, by the encoder, an index of a corrupted data instance of the sequence of progressively less corrupted data instances. The index corresponds with a conditional distribution of the one or more conditional distributions which causes the corrupted data instance to have a desired bit-rate. The method further includes transmitting, from the encoder to a decoder, the first data instance and the information representative of the one or more conditional distributions to enable the decoder to recover the corrupted data instance having the desired bit-rate and use the corrupted data instance to generate output data representative of the data.

The present invention relates to communication system and method for error-proportional energy-saving in encoding and decoding in Body Area Networks (BAN) using Human Body Communication (HBC). The method includes receiving message signal from data sources. Further, the method includes encoding data symbols using encoding algorithms. Furthermore, the method includes calculating syndrome values for the encoded data symbols. Furthermore, the method includes generating an error signal when the calculated syndrome values corresponds to a non-zero value. Furthermore, the method includes receiving the error signal from the syndrome module. Furthermore, the method includes activating an Error Location Polynomial (ELP) module when the syndrome values corresponds to a non-zero value. Subsequently, the method includes generating an error indication signal. Consequently, the method includes activating an Error Magnitude Polynomial (EMP) solver module and a chien search module. Finally, the method includes decoding the encoded data symbols.

A soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. A match array is maintained. Each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. A bit flip threshold from a threshold data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. The respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold.

According to one aspect of an embodiment, a decision feedback equalizer (DFE) may be configured for noise suppression slices. The DFE may be configured to receive an output signal having a receive (Rx) symbol from the feed-forward equalizer. The DFE may be configured to initialize noise suppression slicer (NSS) parameters including one or more initial NSS coefficients and one or more initial slicer delay decision (SDD) threshold offsets. The DFE may be configured to determine one or more updated NSS coefficients. The DFE may be configured to determine one or more updated SDD threshold offsets. The DFE may be configured to update an NSS parameter of the processing register based on the one or more updated NSS coefficients and the one or more updated SDD threshold offsets.

A memory device includes a memory cell array that includes a plurality of memory cells disposed in a plurality of rows, an eraser detector that stores vulnerable row data including a location of an estimation error corresponding to a vulnerable row among the plurality of rows, an error correction code (ECC) engine that decodes first data read from the memory cell array based on the vulnerable row data to generate information on a first error included in the first data in response to a read command and corrects the first error to generate second data, and a flag generator that generates a decoding flag indicating a decoding state of the ECC engine based on the vulnerable row data, the information on the first error, and the second data.

The present invention is related to a quantum computing arrangement comprising a plurality of qubits, to a quantum computing system comprising a plurality of said quantum computing arrangements, to a method of implementing, on a quantum computing system, a quantum error correction code, said quantum computing system comprising the quantum computing arrangement, and to the use of a quantum computing system or a quantum computing arrangement for implementing a quantum error correction code.

In some implementations, a memory system may obtain, from a host system, a command to read data. The memory system may retrieve a codeword associated with the data. The memory system may generate, based on the codeword, a syndrome. The memory system may generate one or more decoding values based on the syndrome and using one or more combinational circuits. The memory system may correct one or more errors in the codeword using the one or more decoding values. The memory system may provide the data to the host system.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engines is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address, The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

The present application relates to the field of communications. Provided in the embodiments are communication methods and an apparatus, which can implement low-complexity channel coding of terminal devices. A communication method comprises: a terminal device receives first information, the first information instructing the terminal device to send an uplink signal, and an input bit sequence of the uplink signal being a first bit sequence; and outputting a pre-stored second bit sequence, wherein the second bit sequence is obtained by arranging in a predefined order a bit sequence acquired by subjecting the first bit sequence to channel coding.

According to disclosed embodiments, methods and systems of data transmission are provided. An aspect of the present disclosure is a method comprising receiving an audio stream, parsing the audio stream into packets, encoding each packet using Alphabet Linear Network Coding (ALNC), and transmitting the encoded packets.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.