192results about "Coding details" patented technology

The invention provides a decoder, a decoding method, a memory system, an operation method of the memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in a current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check matrix, the check formula and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to: determine a flipping threshold in a current iteration based on a change state of the checkout weight; and the bit flipping circuit is configured to output the to-be-decoded code word in the next round of iteration based on a comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value in the current iteration determined by the processor.

This disclosure provides methods, components, devices, and systems for ultra-high reliability (UHR) signaling design. Some aspects more specifically relate to an access point (AP) transmitting a frame including a user info field to a wireless station (STA), where the user info field supports UHR parameters. The user info field may include a subfield indicating a coding scheme for communications, where the subfield includes at least two bits to support at least three coding scheme options. Additionally, or alternatively, the AP may transmit a trigger frame indicating for one or more STAs to communicate via distributed resource units (RUs). The AP may arrange the user info fields in the trigger frame to implicitly indicate respective global cyclic shift delay (CSD) indexes to the STAs. A STA receiving the trigger frame may determine a global CSD index corresponding to the STA according to the order of the user info fields.

In some implementations, a memory system may obtain, from a host system, a command to read data. The memory system may retrieve a codeword associated with the data. The memory system may generate, based on the codeword, a syndrome. The memory system may generate one or more decoding values based on the syndrome and using one or more combinational circuits. The memory system may correct one or more errors in the codeword using the one or more decoding values. The memory system may provide the data to the host system.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.

The invention provides a decoder, a decoding method, a memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, wherein the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check formula, the check matrix and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to select a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the checkout weight in the initial iteration; distributing one flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit is configured to output the to-be-decoded code word in the next iteration based on the comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value allocated by the processor.

Methods, systems, and devices for wireless communications are described. An encoding device (e.g., a network entity or user equipment (UE)) can communicate an indication of an encoding symbol identifier (ESI), a source block number (SBN), or both, to a decoding device in downlink control information (DCI). By way of example, the indication of the SBN and / or ESI can be transmitted using either an unused field or a repurposed field in the downlink control information (DCI) that schedules a transmission including the encoding symbols, or in a new DCI piggybacked on a downlink shared channel transmission including the encoding symbols. Additionally or alternatively, in a first option, the ESI can be explicitly indicated by the DCI. In another option, the network entity can indicate (e.g., via radio resource control messaging) a configuration for implicitly determining the ESI based on information conveyed in the DCI.

Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device (WCD) may send an indication of supporting a plurality of parity mapping schemes for communication. The WCD may receive a communication having a first parity mapping scheme and a second parity mapping scheme, the first parity mapping scheme being different from the second parity mapping scheme. Numerous other aspects are described.

A modem chip receives a codeword including a transport block composed of a plurality of code blocks, and includes a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation with respect to the codeword, and an internal memory configured to store data generated by the HARQ processing circuit. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks in units of code blocks and perform a first cyclic redundancy check on each of the decoded plurality of code blocks, and a codeword processing circuit configured to perform a second cyclic redundancy check on a decoded transport block.

One approach may include at least partially initializing the mesh of the SE engine based at least in part on predetermined state information about the communication channel associated with the incoming data stream; and processing the incoming data stream via the MLSE engine to further initialize the mesh and decode the incoming data stream.

In some aspects, the techniques described herein relate to a method including: receiving a standard error code correction (ECC) matrix, the standard ECC matrix including a portion for checking a payload and a portion for checking a parity of the payload; and extending the ECC matrix to form an extended matrix by adding a plurality of rows and a plurality of columns to form an upper matrix and a lower matrix, wherein the plurality of rows and columns include at least one all zero portion, at least one portion for checking a quantized Knuth (QK) index, and a portion for checking a parity of the QK index.

An apparatus has processing circuitry 2 to perform data processing in response to instructions; at least one control storage element 74 to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry 70 to generate a checksum based on at least one item of internal state stored in the at least one control storage element 74. The checksum is stored in a diagnostic storage location 72 from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and / or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

The present invention provides a device, method, and non-temporary computer-readable medium for rate matching and transmitting transport blocks (TBoMS) spanning multiple slots. [Solution] Method 800 includes determining the starting position of at least one redundant version of a transport block in a circular buffer based at least partially on the position of another redundant version of the transport block in a circular buffer, and transmitting another redundant version and / or one or more of the at least one redundant version using the determined starting position of the at least one redundant version of the transport block, 820 where only one of the at least one redundant version is transmitted, multiple redundant versions of the at least one redundant version are transmitted, or several of the other redundant versions and the at least one redundant version are transmitted.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may transmit, via a first transmission of a hybrid automatic repeat request (HARQ) procedure, a first set of information bits, wherein the first set of information bits are encoded into a first polar codeword of a first size. The wireless communication device may transmit, via a second transmission of the HARQ procedure, the first set of information bits and a second set of information bits, wherein the first set of information bits and the second set of information bits are jointly encoded into a second polar codeword of a second size. Numerous other aspects are described.

Incoming sensor data from a data collection device may be received at the data processing platform that includes the plurality of data processing microservices. A data processing microservice of the data processing platform may detect that the incoming sensor data from the data collection device caused an error. As a result, the incoming sensor data may be queued in a faulty data cache of the data processing platform. Subsequently, at least one of the data processing microservice or the incoming sensor data stored in the faulty data cache may be modified such that the incoming sensor data is processed by the data processing microservice without the error. Following the processing, the incoming sensor data may be deleted from the faulty data queue of the data processing platform.

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.

An error correction circuit includes an error processing circuit, a poison processing circuit, and a data pattern conversion circuit. The error processing circuit receives data, generates delayed data, a parity signal, and syndrome information, and outputs error correction data generated by correcting errors in the data according to the syndrome information. The poison processing circuit outputs one of a write poison flag and a read poison flag as a poison pattern control signal in accordance with a write command. The data pattern conversion circuit converts the delayed data and the parity signal into a poison pattern according to the poison pattern control signal and outputs the poison pattern.

The present disclosure disclose decoders, decoding methods, memory systems, memory controllers and computer readable storage medium. The decoder comprises a first data processing circuit and a second data processing circuit coupled to the first data processing circuit; the first data processing circuit is configured to: perform a current check calculation using a current column of a check matrix and a current sub-matrix of a current flag matrix, and perform a current incremental check calculation on a result of the current check calculation and a previous syndrome to generate a current syndrome; the second data processing circuit is configured to: determine an error symbol in a next data block of the codeword, using one of the current syndrome or a previous syndrome and a next column of the check matrix, based on the current syndrome not satisfying a check condition; wherein the previous syndrome is generated prior to the current syndrome.

Aspects of the disclosure are directed to an error detection approach performed in a processing cycle with improved accuracy and reduced latency. The approach involves determining whether the size of a received input value is greater than, equal to, or less than the size of an accumulator value and performing error detection accordingly using parallel lookup tables corresponding to portions of the input value. To avoid bit reversals in the error detection approach, results stored in the lookup tables may be stored in a bit reversed order. For input values that are less than the size of an accumulator value, the accumulator value is split into two portions to increase accuracy of the error detection result.

The present invention provides a magnetic disk device that can efficiently record parity and has excellent error correction capabilities for user data on the disk. [Solution] The magnetic disk device comprises a disk DK, a write head WHD, a volatile buffer memory 80, a parity generation unit, a write processing unit 62, an error correction unit 64, a storage processing unit 65, and a normal correction limit prediction unit 66. The parity generation unit generates a first normal parity and a first strong parity based on first user data, and generates a second normal parity and a second strong parity based on second user data. The storage processing unit 65 overwrites the first recording area of ​​the buffer memory with the second strong parity if the first prediction information is normal information, and if the first prediction information changes to abnormal information, it leaves the first strong parity in the first recording area and stores the second strong parity in the second recording area of ​​the buffer memory.

A processing-in-memory (PIM) device implements block quantization techniques for matrix-vector operations. The PIM device performs matrix-vector operations between portions of a weight matrix and an input vector, and copies results to a register. A read operation retrieves the copied results while additional matrix-vector operations are performed in parallel. The device may apply scaling factors to the results using multipliers within the PIM device. In some implementations, the weight matrix includes data columns and scaling factor columns interspersed at regular intervals. The scaling factors may be applied to accumulated results using parallel multiplication operations. Disclosed techniques enable efficient implementation of block quantization for applications such as Large Language Models while managing computational resources within the PIM architecture.

According to one aspect of the present disclosure, a decoder is provided. The decoder may include a first processing circuit to: obtain a check formula and check formula weight based on a codeword to be decoded in a current iteration and a check matrix; a second processing circuit to: obtain energy of the codeword to be decoded based on the check formula, the check matrix and a flipping state of the codeword to be decoded; a processor to: in a first iteration, select a preset threshold sequence as an initial threshold sequence based on the check formula weight; and assign a flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit to: output a codeword to be decoded in a following iteration based on a result of a comparison between energy of the codeword to be decoded and the flipping threshold.

The invention relates to error control using a combinatorial circuit in a memory system. In some embodiments, a memory system may obtain a command to read data from a host system. The memory system may retrieve a codeword associated with the data. The memory system may generate a syndrome based on the codeword. The memory system may generate one or more decoded values based on the syndrome and using one or more combining circuits. The memory system may use the one or more decoded values to correct one or more errors in the codeword. The memory system may provide the data to the host system.

A method for execution by one or more computing devices of a storage network includes determining a threshold number of favorably performing storage units of a set of storage units will be available during a time period for testing a storage unit of the set of storage units that is not apart of the threshold number of favorably performing storage units. The method further includes initiating the testing of the storage unit. The method further includes generating a testing report regarding the testing of the storage unit.

Aspects presented herein may improve latency and power consumption of communications by enabling a wireless device to apply external coding (OC) (using forward error correction (FEC)) to a transmission. In one aspect, a wireless device segments each packet data convergence protocol (PDCP) packet of a plurality of PDCP packets into a set of OC symbols, where the plurality of PDCP packets correspond to a packet data unit (PDU) set. The wireless device assembles a plurality of sets of OC symbols into an OC block. The wireless device applies FEC coding to the OC block. The wireless device outputs the OC block based on the FEC encoding. In some examples, the wireless device also adds an OC header to the OC block, where the OC header includes a symbol size, a set of source symbols, and / or a symbol index associated with FEC coding.

A storage network is operable to generate a plurality of encoded data slices for storage via a plurality of storage units based on performing an encoding function upon at least one data object. The plurality of encoded data slices are stored via a set of storage units located in a plurality of different locations. Testing of a storage unit of the set of storage units is performed. Availability of a subset of the set of storage units that includes a predetermined threshold number of storage units of the set of storage units is maintained during the testing of the storage unit. A testing report regarding the testing of the storage unit is generated. The data object is accessed based on reading multiple ones of the plurality of encoded data slices from multiple ones of the set of storage units, where the multiple ones of the set of storage units includes the storage unit.

A codeword synchronization method includes: entering a synchronization position determining state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determining state, where the synchronization position indicates a start position of a codeword in the data sequence; entering a loss-of-lock detection state in response to determining the synchronization position; verifying, in the loss-of-lock detection state, a plurality of codewords selected based on the synchronization position; and re-entering the synchronization position determining state in response to a verification failure.

Apparatuses, systems, and techniques to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals. In at least one embodiment, one or more EDC algorithms are to be performed on said one or more RAN signals based, at least in part, on one or more quality indicators of said one or more RAN signals.