6 results about "Single parity check" patented technology

The application provides a polar code soft input soft output decoding method, a decoding device and a communication device; the decoding method comprises the following steps: (S1) performing fast serial cancellation list decoding under dynamic frozen bit constraint for all special nodes constituting a polar code; the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) calculating the approximation of the sum of the posterior probabilities of the legal code words not accessed under each special node after decoding; (S3) using the approximation of the code book probability obtained in the step (S2) to calculate the bit level soft information of the output polar code. The low-latency polar code soft input soft output decoding method provided by the application improves the parallelism by realizing fast soft output decoding based on the Rate0, Rate1, REP and SPC nodes, and significantly reduces the decoding latency without losing the soft output precision compared with the SO-SCL decoding algorithm.

The invention provides a polarization code soft input soft output decoding method, a decoding device and communication equipment. The decoding method comprises the following steps: (S1) aiming at all special nodes forming a polarization code, fast serial cancellation list decoding under dynamic frozen bit constraint is executed, and the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) after each special node is decoded, calculating the approximation of the posterior probability sum of legal code words which are not accessed under the node; and (S3) utilizing the approximate estimation codebook probability obtained in the step (S2) and calculating bit-level soft information of the output polarization code. Compared with an SO-SCL decoding algorithm, the low-delay soft input and soft output decoding method for the polarization codes, provided by the invention, has the advantages that the degree of parallelism is improved and the decoding delay is remarkably reduced on the premise that the soft output precision is not lost by realizing rapid soft output decoding based on the Rate0, the Rate1, the REP and the SPC nodes.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

Decoding low-density parity check (LDPC) codes in a communication system includes identifying a first set of indices of variable nodes (VNs) having log-likelihood ratios (LLRs) greater than a threshold. A second set of indices that includes the first set of indices, indices of shortening VNs, and indices of single parity check (SPC) VNs is created. LDPC decoding proceeds by iteratively updating check-to-variable (C2V) messages and variable-to-check (V2C) messages, with updates for a VN being skipped when an index of the respective VN belongs to the second set of indices.

The invention discloses a decoding method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a plurality of root node likelihood values in response to a decoding instruction; based on the plurality of root node likelihood values, determining a plurality of initial bit values, a target flip position of each column and a plurality of parallel check values; under the condition that a parallel check value in the plurality of parallel check values meets a parallel check condition, obtaining a target flipping column; flipping the current bit value at the target flipping position of the target flipping column to obtain a flipping bit value; replacing the current bit value at the target flipping position in the target flipping column with a flipping bit value to obtain a first bit path; determining a bit path set based on the first bit path and a path flipping rule; performing single parity check on the bit path set to obtain a target bit path; according to the technical scheme of the invention, the memory consumption is reduced, the decoding efficiency is improved, and the decoding delay is reduced.

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.