2 results about "Single parity check" patented technology

The invention discloses a decoding method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a plurality of root node likelihood values in response to a decoding instruction; based on the plurality of root node likelihood values, determining a plurality of initial bit values, a target flip position of each column and a plurality of parallel check values; under the condition that a parallel check value in the plurality of parallel check values meets a parallel check condition, obtaining a target flipping column; flipping the current bit value at the target flipping position of the target flipping column to obtain a flipping bit value; replacing the current bit value at the target flipping position in the target flipping column with a flipping bit value to obtain a first bit path; determining a bit path set based on the first bit path and a path flipping rule; performing single parity check on the bit path set to obtain a target bit path; according to the technical scheme of the invention, the memory consumption is reduced, the decoding efficiency is improved, and the decoding delay is reduced.

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.