490results about "Error detection only" patented technology

The invention provides a multi-feature information hidden document integrity verification and tampering positioning method, and relates to the field of network security and digital document protection. The multi-feature information hidden document integrity verification and tampering positioning method comprises the following steps: S1, document multi-dimensional feature extraction and encryption: based on an original Word document, adopting an SHA-3 algorithm to calculate a full-text hash value as a content feature, and extracting document object model features such as paragraph hierarchy, table structure and the like through a DOM tree analyzer; after the two types of features are combined into a feature matrix, a dynamic secret key is generated through Logistic chaotic mapping for XOR encryption, and an encrypted document feature matrix is generated. A dynamic key is generated by combining Logistic chaotic mapping encryption through a multi-dimensional extraction technology fusing document content hash values and structural features, so that the anti-cracking capability of a feature matrix is remarkably improved, the confidentiality of document features in open network transmission is ensured, the block information retention rate is simulated and predicted by adopting Monte Carlo, and the watermark embedding weight is dynamically allocated.

Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit / receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and / or the second bit level control information group.

Circuits defined by n-state switching tables with n>2 are transformed by at least one n-state inverter which may be a Finite Lab-transform (FLT) into a Finite Lab-transformed (FLTed) n-state switching devices. Computer operations defined by transformed or modified n-state switching tables are applied in cryptographic operations, including one or more message digests or hashing methods or computer one-way functions. A keyword is generated from a public keyword by at least one modified known hashing method. A known hashing method may be selected from the group consisting of SHA-1, SHA-2, SHA-3, MD5, MD6, Blake2, Blake3 and CubeHash. Internal states of known hashing methods are modified to generate unpredictable hash values.

A method, computer program product, and computing system for processing a plurality of packets transmitted from a first computing device to a second computing device. A packet sequence number associated with each packet is identified. An error-detecting code representation is generated using the packet sequence number of each packet. A packet that is missing from the plurality of packets is identified. A packet loss pattern associated with the plurality of packets is identified by comparing the error-detecting code representation with a plurality of entries of a high probability loss pattern memory table.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The disclosure discloses a method for supporting segmented cyclic redundancy check, comprising: in response to correctness of a first cyclic redundancy check performed on an encoding block by using a generator polynomial corresponding to the encoding block belonging to a transport block, performing a second cyclic redundancy check operation on the encoding block by using a generator polynomial corresponding to the transport block, obtaining a first result; performing third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transmission block and the length of the coding block by using a generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, and performing a fourth cyclic redundancy check operation on the result of the first operation by using a generator polynomial corresponding to the transmission block to obtain a partial result of the coding block in the cyclic redundancy check code of the whole transmission block; and performing second operation on each part result to obtain a cyclic redundancy check code of the whole transmission block.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

The invention discloses a PSI5 decoding method, and relates to the technical field of PSI5 decoding, a main chip sends a PWM signal to enable a PSI5 conversion module to generate a synchronization pulse, a sensor detects the synchronization pulse and then fills fluctuating current data, a current comparison module converts the fluctuating current data into a digital voltage signal, a voltage output module amplifies the digital voltage signal and then sends the digital voltage signal to a main chip universal port, and the PSI5 conversion module outputs the digital voltage signal to the main chip universal port. The main chip detects the level of a port through a timed task, and Manchester soft decoding is carried out to obtain data. The method has obvious advantages, the dependence on a special decoding chip is eliminated, the cost is reduced, data can be analyzed by using a general interface of a main chip, the requirement on the main chip is reduced, the system performance is improved by software decoding, and the control real-time performance and the control effect are improved in applications such as an electric control suspension and the like.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

A system and a method are disclosed relating to a transport block processing chain for a transmitter. A code block determination circuit may be configured to determine a size of a code block that maps across multiple slots of a wireless physical shared channel according to a Transport Block over Multiple Slots (TBoMS) configuration, and a rate matching circuit may be configured to rate match bits of the code block to a number of bits available in a transport block that spans the predetermined number of slots of the wireless physical shared channel. Additionally, an interleaver may be configured to interleave a continuous output of the rate matching circuit on a slot basis so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved within the first slot and the second slot.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

In some implementations, an apparatus may receive a first copy of payload data and a corresponding first cyclic redundancy check (CRC) code, and a second copy of the payload data and a corresponding second CRC code. Each of the first copy and the second copy may be encrypted with an identical keystream. The apparatus may decrypt, using the keystream, the first copy to obtain first decrypted data and the second copy to obtain second decrypted data, append the first CRC code to the first decrypted data to form first data, append the second CRC code to the second decrypted data to form second data, determine one or more bit positions, at each of which the first data and the second data have bit values different from each other, and correct, based on the one or more bit positions, an error contained in the first data.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

An example semiconductor device includes a first semiconductor die including a morph-link circuit and a first interface circuit. The morph-link circuit is configured to receive streaming data formatted in a first format according to a first protocol, the streaming data comprising a plurality of data bits in the first format and a plurality of control bits in the first format; and convert the streaming data to a second format according to a second protocol, including separating the plurality of control bits from the plurality of data bits. The morph-link circuit is further configured to transmit the streaming data in the second format to the first interface circuit, including transmitting the plurality of data bits in the second format via a first communication channel to the first interface circuit and transmitting control information corresponding to the plurality of control bits via a second communication channel to the first interface circuit.

The present invention relates to a multiple application QR code capable of storing information of a plurality of applications in such a way that a respective information can be retrieved for each application in a reliable and time-efficient manner. The information is encoded into encoded data including at least a header and a respective data container per application. The header can comprise at least a single identifier indicating a presence of the plurality of applications and a respective application identifier per application. The encoded data are distributedly stored in a plurality of data pixels distributed over an encoding region of the QR code, according to an allocation rule. A QR code reader can retrieve the information stored in the QR code by only accessing and processing the data pixels associated with the respective application of interest and by using an error correction which is specific to this respective application.

Redundant data storage includes performing a first data transfer to a first storage device as part of a redundant write operation. A first error detection code is generated for the first data transfer. A second data transfer is performed to a second storage device as part of the redundant write operation. A second error detection code is generated for the second data transfer. The first error detection code is compared with the second error detection code for a match indicating that data of the first data transfer matches data of the second data transfer.

A device in a communication or broadcast system may comprise a memory, at least one transceiver, and at least one processor, comprising processing circuitry, connected to the memory and the at least one transceiver. The device may be configured to: acquire a signal; identify information about at least one dummy parity check (PC) bit among one or more PC bits of the signal on the basis of at least one information bit of the signal and a rate matching size for a polar code; identify a decoder setting for error detection and error correction on the basis of information about the at least one dummy PC bit; and decode the signal based on the decoder setting. The at least one dummy PC bit may include a bit having a fixed value regardless of one or more preceding bits of the decoding among the one or more PC bits.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

The invention relates to an adaptive low density parity check (LDPC) decoder architecture. An LDPC decoder architecture is provided for adaptively adjusting an LDPC control input for successfully decoding a corresponding received code block. The architecture supports a machine learning based process that facilitates learning the optimal LDPC control input required for a given channel condition and deployment scenario, such as log-likelihood (LLR) term scaling. This is accomplished by an unused LDPC decoder accelerator collecting posterior decoding metrics as a background process, the function of the accelerator being to process a tagged LLR dataset of different LDPC control input values. This optimal LDPC control input estimate may then be applied to real-time LDPC decoding based on previous learning under UE / channel conditions.

Implementations for simplified and efficient error correction code schemes with multiple codewords are provided. One aspect includes a computing system comprising: processing circuitry and memory storing instructions that, during execution, causes the processing circuitry to: encode data comprising user data and metadata in a memory module comprising a plurality of dies by: logically partitioning the memory module into a plurality of partitions; on a first partition: storing a first portion of the user data on one or more memory segments of the first partition; and storing a first cyclic redundancy check (CRC) codeword and the metadata on a memory segment of the first partition different from the one or more memory segments of the first partition, wherein the first CRC codeword is generated based on the first portion of the user data and the metadata; and storing parity data on one of the plurality of dies.

The present application relates to the technical field of communications. Provided are a channel encoding method and apparatus, and a channel decoding method and apparatus. The reliability of encoding based on cyclic redundancy check can be improved. The channel encoding method comprises: a first communication device determining the length of a check bit sequence on the basis of the size of a payload and an information identifier of the payload; encoding the payload on the basis of the length of the check bit sequence, so as to obtain an encoded bit sequence; and sending the encoded bit sequence.

In 5G / New Radio (NR), sidelink communication refers to a channel for communications directly between devices, e.g., user equipment (UEs), without use of traditional uplink or downlink communication channels. Sidelink Control Information (SCI) is separated into two stages (i.e., SCI stage 1 and SCI stage 2) before being transmitted to configure a user device. A method for configuring sidelink communications for a wireless device includes: obtaining SCI Stage 2 payload information; attaching and distributing cyclic redundancy check (CRC) information to the payload information; performing encoding and rate matching (RM) on the payload information; scrambling the encoded and rate matched payload information; performing modulation on the scrambled payload information; determining a resource mapping for the modulated payload information, wherein the modulated payload information is aggregated across two or more slots (e.g., using different processing operations for at least two slots); and transmitting the modulated payload information according to the determined resource mapping.

Provided in the present application are a polar code decoding method and a communication apparatus. The method comprises: obtaining a symbol sequence to be decoded; determining a first decoding result, the first decoding result being obtained by decoding the symbol sequence to be decoded; and, if the first decoding result does not pass verification, determining a second decoding result, wherein the second decoding result is obtained by decoding a first sequence, the first sequence is generated from the symbol sequence to be decoded and a perturbation sequence, and the perturbation sequence is related to the first decoding result. When the first decoding result of the symbol sequence to be decoded does not pass the verification, specific perturbation is applied to the symbol sequence to be decoded and re-decoding is performed, thus improving the polar code decoding performance.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A method for wireless communication at a UE and related apparatus are provided. In the method, the UE generates one or more CRCs for a transmission including a control payload and a data payload. The number of the one or more CRCs is based on a total size of the control payload and the data payload. The UE further provides the transmission, including the one or more CRCs, to a receiving device.

This application provides coding / decoding methods and communications apparatuses thereof. In an implementation, a coding method includes: obtaining a first information bit sequence; determining a first frozen bit sequence based on a probability distribution value P1 of the first information bit sequence, determining a check bit sequence based on a second information bit sequence, where the second information bit sequence is the first information bit sequence or a sequence obtained after a pre-transformation operation is performed on the first information bit sequence, obtaining a first bit sequence based on the second information bit sequence, the check bit sequence, and the first frozen bit sequence, where the first bit sequence includes bits in the second information bit sequence.

Coded stream processing is provided. A system and method for encoding streaming data to facilitate recovery from faulty or slow processor (s) is described herein. A batch of processing stream data may be partitioned into a plurality of data blocks. The parity block (s) are used for a plurality of data blocks. The plurality of data blocks and parity block (s) may be provided to a processor for processing. Processed data of at least some (e.g., one or more) data blocks of the plurality of data blocks and processed data of parity block (s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, the parity block (s) is received based at least in part on the received processed parity block (s) and the received processed data block (s). The processed data is determined for the particular data block (s) of the particular processor (s) from which the processed data is not received.