301results about "Error detection only" patented technology

Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit / receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and / or the second bit level control information group.

A method, computer program product, and computing system for processing a plurality of packets transmitted from a first computing device to a second computing device. A packet sequence number associated with each packet is identified. An error-detecting code representation is generated using the packet sequence number of each packet. A packet that is missing from the plurality of packets is identified. A packet loss pattern associated with the plurality of packets is identified by comparing the error-detecting code representation with a plurality of entries of a high probability loss pattern memory table.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

A system and a method are disclosed relating to a transport block processing chain for a transmitter. A code block determination circuit may be configured to determine a size of a code block that maps across multiple slots of a wireless physical shared channel according to a Transport Block over Multiple Slots (TBoMS) configuration, and a rate matching circuit may be configured to rate match bits of the code block to a number of bits available in a transport block that spans the predetermined number of slots of the wireless physical shared channel. Additionally, an interleaver may be configured to interleave a continuous output of the rate matching circuit on a slot basis so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved within the first slot and the second slot.

In some implementations, an apparatus may receive a first copy of payload data and a corresponding first cyclic redundancy check (CRC) code, and a second copy of the payload data and a corresponding second CRC code. Each of the first copy and the second copy may be encrypted with an identical keystream. The apparatus may decrypt, using the keystream, the first copy to obtain first decrypted data and the second copy to obtain second decrypted data, append the first CRC code to the first decrypted data to form first data, append the second CRC code to the second decrypted data to form second data, determine one or more bit positions, at each of which the first data and the second data have bit values different from each other, and correct, based on the one or more bit positions, an error contained in the first data.

Redundant data storage includes performing a first data transfer to a first storage device as part of a redundant write operation. A first error detection code is generated for the first data transfer. A second data transfer is performed to a second storage device as part of the redundant write operation. A second error detection code is generated for the second data transfer. The first error detection code is compared with the second error detection code for a match indicating that data of the first data transfer matches data of the second data transfer.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

Implementations for simplified and efficient error correction code schemes with multiple codewords are provided. One aspect includes a computing system comprising: processing circuitry and memory storing instructions that, during execution, causes the processing circuitry to: encode data comprising user data and metadata in a memory module comprising a plurality of dies by: logically partitioning the memory module into a plurality of partitions; on a first partition: storing a first portion of the user data on one or more memory segments of the first partition; and storing a first cyclic redundancy check (CRC) codeword and the metadata on a memory segment of the first partition different from the one or more memory segments of the first partition, wherein the first CRC codeword is generated based on the first portion of the user data and the metadata; and storing parity data on one of the plurality of dies.

The present application relates to the technical field of communications. Provided are a channel encoding method and apparatus, and a channel decoding method and apparatus. The reliability of encoding based on cyclic redundancy check can be improved. The channel encoding method comprises: a first communication device determining the length of a check bit sequence on the basis of the size of a payload and an information identifier of the payload; encoding the payload on the basis of the length of the check bit sequence, so as to obtain an encoded bit sequence; and sending the encoded bit sequence.

In 5G / New Radio (NR), sidelink communication refers to a channel for communications directly between devices, e.g., user equipment (UEs), without use of traditional uplink or downlink communication channels. Sidelink Control Information (SCI) is separated into two stages (i.e., SCI stage 1 and SCI stage 2) before being transmitted to configure a user device. A method for configuring sidelink communications for a wireless device includes: obtaining SCI Stage 2 payload information; attaching and distributing cyclic redundancy check (CRC) information to the payload information; performing encoding and rate matching (RM) on the payload information; scrambling the encoded and rate matched payload information; performing modulation on the scrambled payload information; determining a resource mapping for the modulated payload information, wherein the modulated payload information is aggregated across two or more slots (e.g., using different processing operations for at least two slots); and transmitting the modulated payload information according to the determined resource mapping.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

Coded stream processing is provided. A system and method for encoding streaming data to facilitate recovery from faulty or slow processor (s) is described herein. A batch of processing stream data may be partitioned into a plurality of data blocks. The parity block (s) are used for a plurality of data blocks. The plurality of data blocks and parity block (s) may be provided to a processor for processing. Processed data of at least some (e.g., one or more) data blocks of the plurality of data blocks and processed data of parity block (s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, the parity block (s) is received based at least in part on the received processed parity block (s) and the received processed data block (s). The processed data is determined for the particular data block (s) of the particular processor (s) from which the processed data is not received.

The invention relates to a method for frame synchronization for a digital receive signal, which is received at an output of a transmission channel as a consequence of a binary digital transmit signal supplied to an input of the transmission channel, wherein the binary digital transmit signal contains information to be transmitted in a data packet which has a predetermined number D of data symbols in a data section and a predetermined number S of synchronization symbols in an optional synchronization section, and wherein the binary digital transmit signal has a predetermined symbol rate, wherein the digital receive signal is represented by a sequence of digital samples and wherein a sampling frequency is used which is greater than or equal to the symbol rate.According to the invention, a sliding window is defined which has a temporal length corresponding to the temporal length of a data packet or a data segment of a data packet. At each position µ of the sliding window, a sample value is assigned to each symbol segment of the data segment and optionally to each symbol segment of the synchronization segment of the sliding window. For each position µ of the sliding window, a position value Λ is determined using a predefined metric. met[µ] is determined, using at least the sampled values ​​assigned to the symbol segments of the data segment. The metric is based on the use of a model for the transmission channel, which assumes a memory-free transmission channel and in which the digital received signal is described by a conditional probability density function for each of the possible binary values ​​of the transmitted signal. From the initial time of the sliding window in a position for which the position values ​​Λ met assume a maximum or for which the position value Λ met If a predetermined threshold is exceeded, a start time of a data packet in the digital received signal is determined. The invention further relates to a device and a computer program for implementing the method.

In an aspect, a method of coding a data stream is provided. In an aspect, the method includes mapping, by a data stream encoder, bits into one or more delimiters for the data stream while limiting a maximum run-length of a same polarity of bits in the data stream to be no more than 5. Each of the one or more delimiters include a zero bit and a one bit appended to an 8b / 10b codeword of one or more 8b / 10b codewords in the data stream. In an aspect, the method further includes transmitting, by a transmitter, the one or more delimiters in the data stream.

Systems and techniques are provided for wireless communications. For example, a network device can receive configuration information for redundancy bits associated with scheduled non-coherent transmissions. The network device can receive a plurality of non-coherent transmissions corresponding to a message, the message including a plurality of data bits and a plurality of redundancy bits, wherein each non-coherent transmission of the plurality of non-coherent transmissions is associated with a duty cycle corresponding to the scheduled non-coherent transmissions. The network device can determine error control information for one or more data bits of the plurality of data bits using corresponding redundancy bits of the plurality of redundancy bits, wherein the corresponding redundancy bits are determined based on the configuration information.

The application discloses a CRC hardware computing system and a chip, the CRC hardware computing system comprises i selected processing arrays; each selected processing array comprises m selected control modules, each bit of information value of the information field has a corresponding selected processing array in the CRC hardware computing system; in the generating polynomial, except the coefficient of the highest power of the generating polynomial, each power term has a corresponding selected control module in each selected processing array; each selected control module is used for selecting the exclusive or result of the information value of the corresponding bit in the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generating polynomial under the triggering of a clock signal, and transmitting the result to the associated selected control module except the selected processing array where the selected control module is located, so as to output the CRC code in parallel after several clock periods.

Disclosed herein are embodiments of a hearing aid configured to receive a wireless signal including a succession of frames including a first frame including first encoded audio samples, and determine a first codec, perform an error check based on the first frame, and in accordance with a determination that the first frame fails to pass the error check, perform a test.

Disclosed in the present invention is a real-time recursive CRC method. The method comprises: sequentially extracting from a real-time bit stream a1a2a3… binary sequences S1S2…Si… at non-fixed lengths; bisecting into left and right parts each binary sequence segment Si, so as to obtain sub-sequences, and repeatedly bisecting into left and right parts the sub-sequences until the lengths of finally obtained sub-sequences are less than a preset value; and calculating a CRC check value and check matrix of each final sub-sequence, and performing level-by-level upward merging calculation on left and right sub-sequences, so as to obtain a final check value of the entire real-time bit stream. Further disclosed in the present invention are a corresponding CRC apparatus and a computer storage medium and a program for implementing the CRC method. In the present invention, a method combining iteration with recursion is used to calculate, in real time, a check value of a variable-length binary sequence stream, thereby achieving logarithmic calculation time complexity and meeting CRC operation requirements of a real-time ultra-high-speed data stream.

Methods, systems, and devices for wireless communications are described. Cyclic redundancy check (CRC) bits may be appended to a set of information bits on a per-group basis prior to encoding using an error correcting code. The amount of CRC bits appended to each group of information bits may be based on the priority of the group of information bits. For example, the priority may be based on the type of information conveyed by the group of information bits. For example, for a video stream, information bits conveying low frequency information may have a higher priority than information bits conveying high frequency information, as the low frequency bits may be more important to user perception / experience of the video. The transmitting device and the receiving device may negotiate the CRC configuration (e.g., the CRC bits pergroupand the locations of the groups) so that the receiving device can verify the information bits.

Method (500) implemented using a network interface control circuit (110), wherein the network interface control circuit (110) is intended for use with a physical medium, the physical medium being intended for use in an Ethernet protocol frame transmission between the network interface control circuit (110) and a remote device, the method comprising: Receiving (502) Ethernet protocol frame data via the physical medium, wherein the Ethernet protocol frame data includes at least an alignment marker and data associated with triggering a timestamp; Acquiring (504) the data associated with triggering the timestamp; triggering (522) the timestamp based on the data associated with triggering the timestamp; and Remove (524) at least one alignment marker from the Ethernet protocol frame data after triggering (522) the timestamp.

Acceleration of S-polarized ECC throughput by a scheduler is disclosed. A method of simplified successive cancellation list (SSCL) error decoding of an S-polar code includes representing an S-polar code as a perfect binary tree; providing a node v with a soft information vector from a parent node of v to compute a soft information vector for a left child node of v; providing v with a hard decision vector from the left child node and using it with to create a soft information vector and pass it to a right child node of v; providing v with a hard decision vector from its right child node and using it with to create a hard decision vector β v and pass it to its parent node; when v is an i-th leaf node of the perfect tree, updating two path metrics and selecting a path obtained by extending a current path by the lowest path metric.

A high-speed parallel GRAND-CRC decoding method for functional safety communication is presented. M A round-robin noise error mode allocation scheme for each memory cell, without affecting error correction performance, provides... N The system adds an all-zero error mode to the set E of noise error modes and allocates noise error modes to each memory unit in turn. A high-speed parallel decoder architecture design scheme for GRAND-CRC is proposed, including a distributed memory design strategy and the advantage of unrestricted parallelism. The parallelism can be easily set according to hardware resources, and the decoder throughput increases linearly with the parallelism. The system uses a corrector as the basis for logical judgment, and the corrector signal processing unit triggers the correct decoding output. Its features include different processing methods in three cases, especially when contention occurs, selecting the guessed sequence corresponding to the corrector with the smallest sequence number as the decoding output.

The present application relates to multi-candidate successive cancellation list (SCL) decoding of polar codes. In an example, an apparatus processes multiple candidate codewords using a same SCL decoder. The SCL decoder may be cyclic redundancy code (CRC)-aided. The multiple candidate codewords may have different code configurations and / or different inputs. In an example, the multiple candidate codewords are packaged so that at most one of the candidate codewords in the package is valid.

An apparatus and method are described. The apparatus includes a transceiver and a processor that attaches transport block (TB) level (CRC) bits to a TB, selects an LDPC base graph (BG) based on a code rate (CR) and a TB size of the TB containing the TB level CRC bits, determines a number of code blocks (CBs) for segmenting the TB containing the TB level CRC bits according to the selected LDPC BG, determines a single CB size for each CB based on the number of CBs, segments the TB containing the TB level CRC bits into CBs based on the number of CBs and the CB size, pads a last CB of the CBs in the segmented TB with zero values, attaches CB level CRC bits to each of the CBs in the segmented TB, encodes each of the CBs in the segmented TB using the selected LDPC base graph, and transmits the encoded CBs.

The invention provides a coding and decoding method, which comprises the following steps that: coding equipment acquires A information bits and the number nPC of PC bits, and generates a first sequence; the first sequence comprises N bits, and the N bits comprise A information bits and nPC (Personal Computer) bits. The A information bits and the nPC bits are located at (A + nPC) positions with the highest reliability in the first sequence, the PC bits are located at the positions of the bits with the lowest reliability in the first position set S1, and the PC bits are located at the positions of the bits with the lowest row weight and the lowest reliability in the second position set S2. The S1 set is a position set of (A + nPC) bit positions in the first sequence, and the S2 set is a position set of A bit positions with the highest reliability in the first sequence; and the coding device performs polarization coding on the first sequence and sends the obtained Polar codeword sequence. According to the method, the performance of the PC bit improvement code spectrum is reserved, and the influence of the position of the PC bit on the reliability of the message set is avoided.

A communication device generates N encoded bits by encoding an information block on the basis of a polar sequence QN-10={Q0, Q1, . . . , QN-1} wherein N>1024, and 0<=QNi<=N−1 denotes a bit index for i=0, 1, . . . , N−1, the polar sequence QN-10 is defined in ascending order of reliability W(QN0)<W(QN1< . . . <W(QNN-1), W(QNi is the reliability of the bit index QNi, a reliability order of bit indices 0 to 1023 in the polar sequence QN-10 is the same as the reliability order of bit indices 0 to 1023 of a pre-defined polar sequence Q0Nmax-1 in which Nmax=1024, and bit indices having a partial order that can be evaluated from among bit indices greater than or equal to 1024 in the polar sequence QN-10 satisfy W(QNx)<W(QNy) for at least QNx<QNy.