601results about "Error detection only" patented technology

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

The invention provides a multi-feature information hidden document integrity verification and tampering positioning method, and relates to the field of network security and digital document protection. The multi-feature information hidden document integrity verification and tampering positioning method comprises the following steps: S1, document multi-dimensional feature extraction and encryption: based on an original Word document, adopting an SHA-3 algorithm to calculate a full-text hash value as a content feature, and extracting document object model features such as paragraph hierarchy, table structure and the like through a DOM tree analyzer; after the two types of features are combined into a feature matrix, a dynamic secret key is generated through Logistic chaotic mapping for XOR encryption, and an encrypted document feature matrix is generated. A dynamic key is generated by combining Logistic chaotic mapping encryption through a multi-dimensional extraction technology fusing document content hash values and structural features, so that the anti-cracking capability of a feature matrix is remarkably improved, the confidentiality of document features in open network transmission is ensured, the block information retention rate is simulated and predicted by adopting Monte Carlo, and the watermark embedding weight is dynamically allocated.

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

The invention provides a polarization code optimization method for a TLC flash memory, which belongs to the technical field of polarization code optimization of an NAND flash memory, and comprises the following steps of: firstly, constructing a polarization code based on a Monte Carlo method: randomly generating code words in each simulation, coding after setting frozen bits, transmitting and reading data through a flash memory channel, counting and accumulating sub-channel error times by using SC decoding, and calculating an error probability; the information bit determination process is optimized according to P / E cycle times for flash memory characteristics; data to be stored in a flash memory are coded based on PC-CASCL, an original binary bit sequence is averagely segmented, PC codes of all sub-segments are added with check bits, after the sub-segments are combined, CRC coding is carried out through a preset polynomial, polar code coding is carried out on a result, and the result is stored in the flash memory. After the coded data is read from the flash memory, decoding is carried out through PC-CASCL, a decoder is initialized, the maximum path number is set, a path list is created, whether the bits are odd-even check bits or not is judged and checked bit by bit, and after all the bits are decoded, an optimal path is selected as output through CRC code check.

The present invention relates to a multiple application QR code capable of storing information of a plurality of applications in such a way that a respective information can be retrieved for each application in a reliable and time-efficient manner. The information is encoded into encoded data including at least a header and a respective data container per application. The header can comprise at least a single identifier indicating a presence of the plurality of applications and a respective application identifier per application. The encoded data are distributedly stored in a plurality of data pixels distributed over an encoding region of the QR code, according to an allocation rule. A QR code reader can retrieve the information stored in the QR code by only accessing and processing the data pixels associated with the respective application of interest and by using an error correction which is specific to this respective application.

Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit / receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and / or the second bit level control information group.

Circuits defined by n-state switching tables with n>2 are transformed by at least one n-state inverter which may be a Finite Lab-transform (FLT) into a Finite Lab-transformed (FLTed) n-state switching devices. Computer operations defined by transformed or modified n-state switching tables are applied in cryptographic operations, including one or more message digests or hashing methods or computer one-way functions. A keyword is generated from a public keyword by at least one modified known hashing method. A known hashing method may be selected from the group consisting of SHA-1, SHA-2, SHA-3, MD5, MD6, Blake2, Blake3 and CubeHash. Internal states of known hashing methods are modified to generate unpredictable hash values.

The invention discloses a cascading error correction coding method and device and a storage medium, relates to the technical field of error correction coding, and solves the technical problem that the transmission rate of information is reduced due to the fact that redundant information is added to a traditional cascading code in a communication scene with a small data size. The method comprises the following steps: carrying out Viterbi decoding on a soft decision result of received information to obtain a decoding bit sequence; performing cyclic redundancy check on the decoding bit sequence; if not, performing convolutional code coding on the decoding bit sequence to obtain a coding bit sequence; obtaining a high-frequency error pattern, and correcting the decoding bit sequence according to the high-frequency error pattern; performing cyclic redundancy check on the decoded bit sequence after error correction; and if the error-corrected decoding bit sequence and / or the decoding bit sequence passes the cyclic redundancy check, ending the cascade error correction coding. According to the invention, efficient and reliable transmission of information can be ensured in a communication scene with a small data volume.

A method, computer program product, and computing system for processing a plurality of packets transmitted from a first computing device to a second computing device. A packet sequence number associated with each packet is identified. An error-detecting code representation is generated using the packet sequence number of each packet. A packet that is missing from the plurality of packets is identified. A packet loss pattern associated with the plurality of packets is identified by comparing the error-detecting code representation with a plurality of entries of a high probability loss pattern memory table.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

The disclosure discloses a method for supporting segmented cyclic redundancy check, comprising: in response to correctness of a first cyclic redundancy check performed on an encoding block by using a generator polynomial corresponding to the encoding block belonging to a transport block, performing a second cyclic redundancy check operation on the encoding block by using a generator polynomial corresponding to the transport block, obtaining a first result; performing third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transmission block and the length of the coding block by using a generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, and performing a fourth cyclic redundancy check operation on the result of the first operation by using a generator polynomial corresponding to the transmission block to obtain a partial result of the coding block in the cyclic redundancy check code of the whole transmission block; and performing second operation on each part result to obtain a cyclic redundancy check code of the whole transmission block.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

The invention discloses an ultrahigh frequency RFID reader-writer digital processing circuit based on RISC-V. The ultrahigh frequency RFID reader-writer digital processing circuit can be applied to the technical field of radio frequency. According to the application, the processing module, the memory module and the ultrahigh frequency read-write data module are arranged, the controller core constructed based on the RISC-V architecture is arranged in the processing module, and then the processing module, the memory module and the ultrahigh frequency read-write data module are tightly coupled, so that the integration level of the reader-writer can be effectively improved; the area of the reader-writer is reduced, then the interaction process of the ultrahigh-frequency read-write data module and the controller core is managed in a coordinated mode through the bus matrix, and after the controller core receives an external control instruction sent by an upper computer, the label data reading process of the ultrahigh-frequency read-write data module is controlled according to the external control instruction. Therefore, the characteristics of the RISC-V architecture can be utilized, the manufacturing cost is reduced, and the area of the reader-writer is further reduced.

The method includes: A transmitter obtains a first bit sequence, and then performs LDPC encoding on the first bit sequence based on a check matrix, to obtain a second bit sequence. Correspondingly, a receiver receives the second bit sequence, and then performs LDPC decoding on the second bit sequence based on the check matrix, to obtain K information bits. The first bit sequence includes the K information bits, the second bit sequence includes M check bits, and both K and M are positive integers. The check matrix is obtained based on a first base matrix, the first base matrix corresponds to a second base matrix, the second base matrix includes the following elements: 0, 1, and 2.

An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

The present method relates to a method by which a device transmits a signal in a communication system and to a device therefor, the method comprising the steps of: generating a first encoded bit sequence from an information bit sequence on the basis of a polar code; generating a second encoded bit sequence by puncturing the first encoded bit sequence, on the basis of a code rate; and transmitting the second encoded bit sequence, wherein the first encoded bit sequence is processed on the basis of a proposed puncturing pattern, and the puncturing pattern satisfies a nested property.

The invention discloses a PSI5 decoding method, and relates to the technical field of PSI5 decoding, a main chip sends a PWM signal to enable a PSI5 conversion module to generate a synchronization pulse, a sensor detects the synchronization pulse and then fills fluctuating current data, a current comparison module converts the fluctuating current data into a digital voltage signal, a voltage output module amplifies the digital voltage signal and then sends the digital voltage signal to a main chip universal port, and the PSI5 conversion module outputs the digital voltage signal to the main chip universal port. The main chip detects the level of a port through a timed task, and Manchester soft decoding is carried out to obtain data. The method has obvious advantages, the dependence on a special decoding chip is eliminated, the cost is reduced, data can be analyzed by using a general interface of a main chip, the requirement on the main chip is reduced, the system performance is improved by software decoding, and the control real-time performance and the control effect are improved in applications such as an electric control suspension and the like.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

Certain aspects of the present disclosure provide techniques for a probabilistic constellation shaping (PCS) scheme for multiple layer transmissions. An example method includes obtaining a configuration for performing a PCS modulation scheme, identifying a set of bits corresponding to a transport block for communication via the multi-layer transmission, performing distribution matching on the set of bits using a set of parameters indicated in the configuration to obtain a set of distributed symbols, converting the set of distributed symbols into a set of distributed bits, encoding the set of distributed bits to obtain an encoded set of distributed bits, performing a modulation procedure on the encoded set of distributed bits in accordance with the PCS modulation scheme to obtain a set of modulation symbols corresponding to a codeword associated with the transport block, and transmitting, to a receiving device, the codeword, including the set of modulation symbols, via the multi-layer transmission.

The invention relates to a coding method, a decoding method and a device, in the coding method, first equipment can determine a second bit sequence and a third bit sequence based on a first bit sequence, and the third bit sequence comprises a bit sequence of which the weight is higher than a first threshold in a base graph corresponding to the first bit sequence. That is, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the first device can perform polar code coding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with lower weight in a polar code coding mode, so as to improve the error correction performance. And for the third bit sequence with relatively high weight, LDPC coding can be performed on the third bit sequence and a polarization code coding result (namely, a fourth bit sequence obtained by performing polarization code coding on the second bit sequence). The error floor of LDPC decoding is reduced, and the error correction performance of LDPC codes is improved.

A system and a method are disclosed relating to a transport block processing chain for a transmitter. A code block determination circuit may be configured to determine a size of a code block that maps across multiple slots of a wireless physical shared channel according to a Transport Block over Multiple Slots (TBoMS) configuration, and a rate matching circuit may be configured to rate match bits of the code block to a number of bits available in a transport block that spans the predetermined number of slots of the wireless physical shared channel. Additionally, an interleaver may be configured to interleave a continuous output of the rate matching circuit on a slot basis so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved within the first slot and the second slot.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection / correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

In some implementations, an apparatus may receive a first copy of payload data and a corresponding first cyclic redundancy check (CRC) code, and a second copy of the payload data and a corresponding second CRC code. Each of the first copy and the second copy may be encrypted with an identical keystream. The apparatus may decrypt, using the keystream, the first copy to obtain first decrypted data and the second copy to obtain second decrypted data, append the first CRC code to the first decrypted data to form first data, append the second CRC code to the second decrypted data to form second data, determine one or more bit positions, at each of which the first data and the second data have bit values different from each other, and correct, based on the one or more bit positions, an error contained in the first data.

The invention relates to a bit error rate reduction method for reconfigured GPS CNAV-2 navigation message, by using the ORC-POLAR channel coding method instead of BCH and LDPC as the channel coding method to capture and correct errors caused by ambient noise.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

An example semiconductor device includes a first semiconductor die including a morph-link circuit and a first interface circuit. The morph-link circuit is configured to receive streaming data formatted in a first format according to a first protocol, the streaming data comprising a plurality of data bits in the first format and a plurality of control bits in the first format; and convert the streaming data to a second format according to a second protocol, including separating the plurality of control bits from the plurality of data bits. The morph-link circuit is further configured to transmit the streaming data in the second format to the first interface circuit, including transmitting the plurality of data bits in the second format via a first communication channel to the first interface circuit and transmitting control information corresponding to the plurality of control bits via a second communication channel to the first interface circuit.