20 results about "Decoding throughput" patented technology

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

The invention relates to the field of communication technology, and discloses a high-speed LDPC decoder suitable for near-earth satellite communication and an interleaved decoding method, comprising: a variable node operation module, which is used for performing variable node update operation according to a data frame transmitted by an input buffer module and confidence information transmitted from a check node to a variable node in a mutual information storage module, obtaining confidence information and decision information transmitted from the variable node to the check node, transmitting the confidence information transmitted from the variable node to the check node to the mutual information storage module, and transmitting the decision information to an output buffer module at the same time; the invention designs the conversion between the original code and the complement code of the variable node and the check node in the LDPC decoder and the operation of multiplying a correction factor originally belonging to the check node operation module into the variable node operation module, balances the complexity of the variable node and the check node, makes it more suitable for the interleaved decoding method, improves the decoding throughput and the throughput rate, and saves the cost.

A method and device for constructing a multi-rate low-density parity-check code, the embodiments of the present disclosure comprehensively consider the number of non-zero elements in the multi-rate check matrix and the decoding iteration number of each rate, introduce a global normalized throughput index, set the decoding iteration number to be less than a preset iteration number threshold, and set the column weight of the check matrix to be greater than a preset minimum column weight value, determine a base pattern matrix that has the maximum global normalized throughput index value and satisfies the first and second constraint conditions through a global search method, and construct a multi-rate low-density parity-check (LDPC) code based on the matrix, thereby reducing the hardware resource occupation and further improving the decoding throughput, ensuring that the generated multi-rate LDPC code has low hardware resource occupation, meeting the application requirements of resource-constrained scenarios, and improving the applicability of the LDPC code.

The present invention discloses a scheduling method based on a greedy algorithm for multiple parallel decoders. Before decoding, by obtaining the parameter configuration of the user, different transmission priorities are evaluated. At the same time, the user sorting unit sorts according to the priority and decoding efficiency to generate a user queue. After each data is allocated to the corresponding decoder, the decoder redundancy is compared one by one, and a pointer pointing to the decoder ID with the highest redundancy is maintained in the decoder ID queue in real time. The data allocation unit, according to the mechanism of the greedy algorithm, allocates the first user in the user queue to the decoder (with the highest redundancy) pointed to by the pointer in the current ID queue. The user deletion unit evaluates the decoder redundancy and the estimated decoding time of the user. If it cannot be decoded, the user is deleted from the queue and the data is reallocated to the decoder. The scheduling method proposed by the present invention realizes the parallel decoding of multiple Turbo decoders, improves the decoding throughput rate, has low complexity and is easy to implement.

The present invention relates to an FPGA implementation method of a normalized hierarchical minimum sum LDPC decoder, the method comprising: S1, obtaining i variable node values ​​NV and j check node values ​​CV according to the size of the expansion factor, and then recombining them into a valid to-be-decoded information Q LLR ; S2, according to the normalized hierarchical algorithm, the effective information to be decoded Q LLR The positions are divided into n layers; S3, using pipeline mode to update the APP value of the (j+1)th layer according to the valid #imgabs0# to be decoded at the jth layer position until the decoding is completed. Therefore, the pipeline decoding of the present invention greatly shortens the decoding delay and improves the decoding throughput by solving the problem of information loss between layers.

To provide a coefficient coding / decoding method, an encoder, a decoder, and a computer storage medium.SOLUTION: A coefficient decoding method includes: when the last non-zero coefficient position-reverse flag information, obtained when video flag information acquired from a bitstream indicates that a preset condition is satisfied, indicates that position reversing of the last non-zero coefficient is used, calculating coordinate information of the last non-zero coefficient, to identify the position of the last non-zero coefficient; according to a preset scanning order, decoding all coefficients before the position of the last no-zero coefficient to identify coefficients of the current block. In video coding / decoding scenarios with high bit depth, high bit rate, high quality, or lossless compression, the throughput and coding / decoding speed of coefficient coding / decoding can be improved, and compression efficiency can also be improved.SELECTED DRAWING: Figure 9

The invention discloses a QC-LDPC decoding FPGA pipeline implementation method and device. The method comprises the steps that a first lookup table, a second lookup table, a first storage array and a second storage array are constructed on an FPGA; receiving demodulated code word soft information, calculating the log-likelihood ratio of each bit, and writing the log-likelihood ratio into a first storage array; decoding iteration is executed according to a row traversal mode after parameter initialization, and an intermediate message and a log-likelihood ratio are updated; dividing the operation of each row of verification equations into a plurality of serial assembly lines; after all check nodes finish one-time pipeline processing, if the current iteration number is smaller than the maximum iteration number and a check equation which does not meet the parity check constraint exists, iteration is returned, and otherwise, decoding is ended; and performing hard decision on the symbol of the final log-likelihood ratio to obtain a decoding bit sequence, and outputting the decoding bit sequence. According to the invention, the occupation of FPGA storage resources is reduced, the compromise between performance and complexity is realized, the decoding throughput rate is improved, and the time delay is reduced.

The invention provides a flash memory controller and a flash memory access method. The flash memory controller includes a decoder. The decoder is configured to perform a decoding operation of a base matrix of a low density parity check code to decode read information acquired from the flash memory, the base matrix having a size of N * M. The decoder comprises a controller, a variable node (VN) unit and a check node (CN) unit. The controller is used for converting the basic matrix into an N * S compressed matrix, wherein S is smaller than M. The VN unit and the CN unit are used for performing message updating between a variable node and a check node to generate a decoding result converged to a code word. In each iteration operation, the VN unit performs calculation of each column of matrix blocks column by column according to the compression matrix, so that the decoding period of each iteration of the VN unit can be reduced, and the decoding throughput is remarkably increased.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information for the last non-zero coefficient and the coordinate information for the last non-zero coefficient. If the position inversion flag information for the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information for the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

This application provides a decoding method, chip, and related apparatus. By introducing a threshold judgment mechanism, the controller chip can simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput. Simultaneously, the algorithm for calculating the number of bits that do not satisfy the parity check equation for each bit is optimized, reducing the probability of correct bits being incorrectly flipped, thereby reducing the error plane in the decoding.

The invention discloses a data processing method and a related device, the data processing method is applied to a data processing system, the data processing system comprises a plurality of reference computing cards, and the data processing method comprises the following steps: acquiring to-be-processed data; wherein the to-be-processed data is matched with a decoding task and a decision-making task; based on the decoding parameter information of each reference calculation card, determining a first calculation card from all the reference calculation cards, and executing a decoding task by using the first calculation card to obtain a decoding result matched with the to-be-processed data; wherein the decoding parameter information at least comprises decoding time consumption and decoding throughput rate in a historical time period; determining a second computing card from all the reference computing cards based on the decision parameter information of each reference computing card, and executing a decision task by using the second computing card to obtain a target decision result matched with the decoding result; wherein the decision parameter information at least comprises decision time consumption and decision throughput rate in a historical time period. In this way, the processing efficiency of the data processing system can be improved.

A method for decoding video data, comprising: determining, by one or more processors implemented in a circuit, a picture size of a picture. The picture size applies a picture size limit to determine a width of the picture and a height of the picture as respective multiples of a maximum value between 8 and a minimum decoding unit size for the picture. The method further comprises: determining, by one or more processors, a partitioning for partitioning the picture into a plurality of blocks, and generating, by one or more processors, a predicted block for a block among the plurality of blocks. The method further comprises: decoding, by one or more processors, a residual block for the block, and combining, by one or more processors, the predicted block and the residual block to decode the block.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The coefficient decoding method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information and the coordinate information of the last non-zero coefficient. If the position inversion flag information of the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information of the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

The invention provides a data processing method which comprises the steps that a base element group is obtained, the base element group comprises a plurality of base elements, the number of 1 in binary representation of the plurality of base elements is not 0 and is smaller than a first threshold value, a check matrix is constructed according to the plurality of base elements, and the check matrix is used for encoding a data block to generate a check block. In the method, the number of 1 in the binary representation of the base element is smaller than the first threshold value, and the density of the constructed check matrix is relatively low, so that the number of times of XOR calculation can be reduced in a coding process of generating a check block by using the check matrix or a decoding process of recovering incomplete data by using the check matrix, the coding and decoding overhead is reduced, and the decoding efficiency is improved. And the coding and decoding throughput rate is improved.

This application provides a decoding method, a chip, and a related apparatus. A threshold determining mechanism is introduced, so that a controller chip can simultaneously perform calculation of a quantity of check equations that are not met by a bit and a bit flipping process, to reduce a decoding delay of the controller chip and increase a decoding throughput. In addition, an algorithm for calculating, by the controller chip, the quantity of check equations that are not met by each bit is optimized, to reduce a probability that a correct bit is incorrectly flipped, so as to reduce an error floor of decoding.

The invention relates to channel coding in the field of communications. In the existing channel coding technology, a coding end carries out channel coding on a CB, the CB is a long code block, the decoding complexity of the long code block is high, and the decoding efficiency is low. In the application, a coding end divides a CB into a plurality of short code blocks, each short code block is independently coded to generate a plurality of corresponding second check bit sets, and the plurality of short code blocks are coupled together based on N first check bit sets to form a first bit sequence. In the decoding process, each short code block can be decoded based on the plurality of second check bit sets, if the decoding is successful, a decoding result is output, and the first bit sequence is not decoded based on the N first check bit sets any more. Therefore, high-complexity long code block decoding is converted into low-complexity short code block decoding, and the decoding efficiency is improved, so that the decoding throughput is improved.

The present application relates to channel encoding in the field of communications. In existing channel encoding technology, an encoding end performs channel encoding on a CB, wherein CB refers to a long code block. The complexity of decoding long code blocks is relatively high, resulting in low decoding efficiency. In the present application, an encoding end divides a CB into a plurality of short code blocks, and each short code block is independently encoded to generate a plurality of corresponding second check bit sets, and the plurality of short code blocks are coupled together on the basis of N first check bit sets to form a first bit sequence. During decoding, each short code block may be first decoded on the basis of the plurality of second check bit sets, and if the decoding is successful, a decoding result is output, and decoding the first bit sequence on the basis of the N first check bit sets is no longer performed. In this way, the decoding of a high-complexity long code block is converted into the decoding of low-complexity short code blocks, thereby improving the decoding efficiency and thus increasing the decoding throughput.

The invention discloses a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoding method based on a dynamic interlayer parallel architecture, which comprises the following steps of: S1, preprocessing a basis matrix to obtain a non-negative value generated address matrix for indicating a data position and an offset matrix for cyclic shift alignment; s2, initializing information, obtaining a to-be-decoded information sequence from a Gaussian noise channel, and respectively calculating to obtain an initial LLR value of each frame of decoded information sequence; s3, iteratively updating variable nodes, check nodes and posterior LLR information; in the iterative updating process of variable nodes, parallel reading and iterative updating of a plurality of row addresses are achieved by rearranging row sequences and combining rows without address conflicts and offset matrixes of the rows; and S4, carrying out decoding termination judgment after each iteration update, and stopping if a condition is met. Parallel reading and updating of multiple rows of addresses are realized through a dynamic interlayer parallel architecture, access conflicts are reduced by adopting a self-adaptive scheduling strategy, and the method has the advantages of improving decoding throughput, reducing delay and dynamically adapting to different QC-LDPC code structures.

According to the multi-code-rate low-density parity check code construction method and device, the number of non-zero elements in a multi-code-rate check matrix and the number of decoding iterations of each code rate are comprehensively considered, a global normalization throughput index is introduced, the number of decoding iterations is set to be smaller than a preset iteration number threshold value, and the number of decoding iterations is set to be smaller than the number of decoding iterations. And setting a basic model graph matrix which has the maximum global normalized throughput index value and meets the first constraint condition and the second constraint condition when the column weight of the check matrix is greater than a preset minimum column weight value, and constructing a multi-code-rate low-density parity check (LDPC) code based on the matrix, the decoding throughput is further improved while hardware resource occupation is reduced, it is ensured that the generated multi-code-rate LDPC code is low in hardware resource occupation, the application requirement of a resource limited scene is met, and the applicability of the LDPC code is improved.

The application discloses an RLL(1,4) encoding and decoding method and device for optical storage and an optical storage system, and belongs to the technical field of optical storage, and comprises the following steps: in the encoding process, four-block joint encoding, three-block joint encoding, double-block joint encoding and single-block encoding are sequentially performed on user data according to a pre-established mapping table, so that every 3-bit user data is encoded into 5-bit channel symbols; in the mapping table of multi-block joint encoding, the first 5-bit sub-block of a code word starts with a bit '0' or is a specific 5-bit sequence starting with a bit '1'; in the decoding process, the 5-bit sub-block starting with a bit '1' is first identified as a boundary to complete a division, and then the specific 5-bit sub-block starting with a bit '1' is identified as a boundary to complete a secondary division; and the code word obtained through the division is demapped into a user data block according to the mapping table. The application can improve the encoding and decoding throughput of optical storage, suppress error propagation in the encoding and decoding process, and improve the performance and reliability of optical storage.