5 results about "Decoding throughput" patented technology

The invention discloses a QC-LDPC decoding FPGA pipeline implementation method and device. The method comprises the steps that a first lookup table, a second lookup table, a first storage array and a second storage array are constructed on an FPGA; receiving demodulated code word soft information, calculating the log-likelihood ratio of each bit, and writing the log-likelihood ratio into a first storage array; decoding iteration is executed according to a row traversal mode after parameter initialization, and an intermediate message and a log-likelihood ratio are updated; dividing the operation of each row of verification equations into a plurality of serial assembly lines; after all check nodes finish one-time pipeline processing, if the current iteration number is smaller than the maximum iteration number and a check equation which does not meet the parity check constraint exists, iteration is returned, and otherwise, decoding is ended; and performing hard decision on the symbol of the final log-likelihood ratio to obtain a decoding bit sequence, and outputting the decoding bit sequence. According to the invention, the occupation of FPGA storage resources is reduced, the compromise between performance and complexity is realized, the decoding throughput rate is improved, and the time delay is reduced.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information for the last non-zero coefficient and the coordinate information for the last non-zero coefficient. If the position inversion flag information for the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information for the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The coefficient decoding method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information and the coordinate information of the last non-zero coefficient. If the position inversion flag information of the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information of the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

The invention discloses a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoding method based on a dynamic interlayer parallel architecture, which comprises the following steps of: S1, preprocessing a basis matrix to obtain a non-negative value generated address matrix for indicating a data position and an offset matrix for cyclic shift alignment; s2, initializing information, obtaining a to-be-decoded information sequence from a Gaussian noise channel, and respectively calculating to obtain an initial LLR value of each frame of decoded information sequence; s3, iteratively updating variable nodes, check nodes and posterior LLR information; in the iterative updating process of variable nodes, parallel reading and iterative updating of a plurality of row addresses are achieved by rearranging row sequences and combining rows without address conflicts and offset matrixes of the rows; and S4, carrying out decoding termination judgment after each iteration update, and stopping if a condition is met. Parallel reading and updating of multiple rows of addresses are realized through a dynamic interlayer parallel architecture, access conflicts are reduced by adopting a self-adaptive scheduling strategy, and the method has the advantages of improving decoding throughput, reducing delay and dynamically adapting to different QC-LDPC code structures.

The application discloses an RLL(1,4) encoding and decoding method and device for optical storage and an optical storage system, and belongs to the technical field of optical storage, and comprises the following steps: in the encoding process, four-block joint encoding, three-block joint encoding, double-block joint encoding and single-block encoding are sequentially performed on user data according to a pre-established mapping table, so that every 3-bit user data is encoded into 5-bit channel symbols; in the mapping table of multi-block joint encoding, the first 5-bit sub-block of a code word starts with a bit '0' or is a specific 5-bit sequence starting with a bit '1'; in the decoding process, the 5-bit sub-block starting with a bit '1' is first identified as a boundary to complete a division, and then the specific 5-bit sub-block starting with a bit '1' is identified as a boundary to complete a secondary division; and the code word obtained through the division is demapped into a user data block according to the mapping table. The application can improve the encoding and decoding throughput of optical storage, suppress error propagation in the encoding and decoding process, and improve the performance and reliability of optical storage.