10 results about "Decoding throughput" patented technology

A method and device for constructing a multi-rate low-density parity-check code, the embodiments of the present disclosure comprehensively consider the number of non-zero elements in the multi-rate check matrix and the decoding iteration number of each rate, introduce a global normalized throughput index, set the decoding iteration number to be less than a preset iteration number threshold, and set the column weight of the check matrix to be greater than a preset minimum column weight value, determine a base pattern matrix that has the maximum global normalized throughput index value and satisfies the first and second constraint conditions through a global search method, and construct a multi-rate low-density parity-check (LDPC) code based on the matrix, thereby reducing the hardware resource occupation and further improving the decoding throughput, ensuring that the generated multi-rate LDPC code has low hardware resource occupation, meeting the application requirements of resource-constrained scenarios, and improving the applicability of the LDPC code.

The invention discloses a QC-LDPC decoding FPGA pipeline implementation method and device. The method comprises the steps that a first lookup table, a second lookup table, a first storage array and a second storage array are constructed on an FPGA; receiving demodulated code word soft information, calculating the log-likelihood ratio of each bit, and writing the log-likelihood ratio into a first storage array; decoding iteration is executed according to a row traversal mode after parameter initialization, and an intermediate message and a log-likelihood ratio are updated; dividing the operation of each row of verification equations into a plurality of serial assembly lines; after all check nodes finish one-time pipeline processing, if the current iteration number is smaller than the maximum iteration number and a check equation which does not meet the parity check constraint exists, iteration is returned, and otherwise, decoding is ended; and performing hard decision on the symbol of the final log-likelihood ratio to obtain a decoding bit sequence, and outputting the decoding bit sequence. According to the invention, the occupation of FPGA storage resources is reduced, the compromise between performance and complexity is realized, the decoding throughput rate is improved, and the time delay is reduced.

The invention provides a flash memory controller and a flash memory access method. The flash memory controller includes a decoder. The decoder is configured to perform a decoding operation of a base matrix of a low density parity check code to decode read information acquired from the flash memory, the base matrix having a size of N * M. The decoder comprises a controller, a variable node (VN) unit and a check node (CN) unit. The controller is used for converting the basic matrix into an N * S compressed matrix, wherein S is smaller than M. The VN unit and the CN unit are used for performing message updating between a variable node and a check node to generate a decoding result converged to a code word. In each iteration operation, the VN unit performs calculation of each column of matrix blocks column by column according to the compression matrix, so that the decoding period of each iteration of the VN unit can be reduced, and the decoding throughput is remarkably increased.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information for the last non-zero coefficient and the coordinate information for the last non-zero coefficient. If the position inversion flag information for the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information for the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

This application provides a decoding method, chip, and related apparatus. By introducing a threshold judgment mechanism, the controller chip can simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput. Simultaneously, the algorithm for calculating the number of bits that do not satisfy the parity check equation for each bit is optimized, reducing the probability of correct bits being incorrectly flipped, thereby reducing the error plane in the decoding.

This invention provides a method for improving coefficient coding / decoding throughput, coding / decoding speed, and compression efficiency in high-bit-depth, high-bit-rate, high-quality, or lossless video coding / decoding scenarios. [Solution] The coefficient decoding method analyzes the bitstream to obtain video flag information. If the video flag information indicates that the video satisfies a predetermined condition, the bitstream is analyzed to obtain the position inversion flag information and the coordinate information of the last non-zero coefficient. If the position inversion flag information of the last non-zero coefficient indicates that the position inversion of the last non-zero coefficient is to be used, the position of the last non-zero coefficient is determined by calculating the coordinate information of the last non-zero coefficient. According to a predetermined scan order, all coefficients prior to the position of the last non-zero coefficient are decoded to determine the coefficient of the current block.

The invention relates to channel coding in the field of communications. In the existing channel coding technology, a coding end carries out channel coding on a CB, the CB is a long code block, the decoding complexity of the long code block is high, and the decoding efficiency is low. In the application, a coding end divides a CB into a plurality of short code blocks, each short code block is independently coded to generate a plurality of corresponding second check bit sets, and the plurality of short code blocks are coupled together based on N first check bit sets to form a first bit sequence. In the decoding process, each short code block can be decoded based on the plurality of second check bit sets, if the decoding is successful, a decoding result is output, and the first bit sequence is not decoded based on the N first check bit sets any more. Therefore, high-complexity long code block decoding is converted into low-complexity short code block decoding, and the decoding efficiency is improved, so that the decoding throughput is improved.

The present application relates to channel encoding in the field of communications. In existing channel encoding technology, an encoding end performs channel encoding on a CB, wherein CB refers to a long code block. The complexity of decoding long code blocks is relatively high, resulting in low decoding efficiency. In the present application, an encoding end divides a CB into a plurality of short code blocks, and each short code block is independently encoded to generate a plurality of corresponding second check bit sets, and the plurality of short code blocks are coupled together on the basis of N first check bit sets to form a first bit sequence. During decoding, each short code block may be first decoded on the basis of the plurality of second check bit sets, and if the decoding is successful, a decoding result is output, and decoding the first bit sequence on the basis of the N first check bit sets is no longer performed. In this way, the decoding of a high-complexity long code block is converted into the decoding of low-complexity short code blocks, thereby improving the decoding efficiency and thus increasing the decoding throughput.

The invention discloses a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) decoding method based on a dynamic interlayer parallel architecture, which comprises the following steps of: S1, preprocessing a basis matrix to obtain a non-negative value generated address matrix for indicating a data position and an offset matrix for cyclic shift alignment; s2, initializing information, obtaining a to-be-decoded information sequence from a Gaussian noise channel, and respectively calculating to obtain an initial LLR value of each frame of decoded information sequence; s3, iteratively updating variable nodes, check nodes and posterior LLR information; in the iterative updating process of variable nodes, parallel reading and iterative updating of a plurality of row addresses are achieved by rearranging row sequences and combining rows without address conflicts and offset matrixes of the rows; and S4, carrying out decoding termination judgment after each iteration update, and stopping if a condition is met. Parallel reading and updating of multiple rows of addresses are realized through a dynamic interlayer parallel architecture, access conflicts are reduced by adopting a self-adaptive scheduling strategy, and the method has the advantages of improving decoding throughput, reducing delay and dynamically adapting to different QC-LDPC code structures.

The application discloses an RLL(1,4) encoding and decoding method and device for optical storage and an optical storage system, and belongs to the technical field of optical storage, and comprises the following steps: in the encoding process, four-block joint encoding, three-block joint encoding, double-block joint encoding and single-block encoding are sequentially performed on user data according to a pre-established mapping table, so that every 3-bit user data is encoded into 5-bit channel symbols; in the mapping table of multi-block joint encoding, the first 5-bit sub-block of a code word starts with a bit '0' or is a specific 5-bit sequence starting with a bit '1'; in the decoding process, the 5-bit sub-block starting with a bit '1' is first identified as a boundary to complete a division, and then the specific 5-bit sub-block starting with a bit '1' is identified as a boundary to complete a secondary division; and the code word obtained through the division is demapped into a user data block according to the mapping table. The application can improve the encoding and decoding throughput of optical storage, suppress error propagation in the encoding and decoding process, and improve the performance and reliability of optical storage.