Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method

Abstract

The invention discloses a low-storage capacity high-speed QC-LDPC (quasi-cyclic low-density parity check) code decoder based on an FPGA (field-programmable gate array) and a decoding method, which are mainly used for solving the problem of low utilization efficiency of memory resources of a node update processing unit and an RAM (random access memory) of the decoder in the prior art. The decoder can simultaneously process two frames of decoding data, the decoder is used for setting an external information value of the first frame of data as all-zero and setting the second frame of data as a channel for receiving likelihood ratio information in the data initialization phase, so that a variable node processing unit and a check node processing unit can completely alternately process the two data frames in parallel in the whole decoding process, effectively shorten the work clock cycle required for processing the two frames of data and enable the decoding throughput to be about two times as that of a traditional design method. According to the decoder disclosed by the invention, a dynamic address access management method is adopted in external information access, and the parallel access of the two frames of decoding data can be realized in the single RAM; and compared with the existing decoder, the utilization efficiency of BRAM (broadcast recognition access method) resources is doubled in comparison with the existing decoders, and the decoder can be used for error correction in information transmission of a physical layer based on LDPC codes.

Description

technical field [0001] The invention belongs to the technical field of communication, and relates to a channel error correction code decoder, in particular to an FPGA-based quasi-cyclic low density check code decoder and a decoding method, which can be used for error correction of physical layer information transmission based on LDPC codes . Background technique [0002] The traditional quasi-cyclic low-density check QC-LDPC code decoder is mainly composed of a variable node calculation module VNU, a check node calculation module CNU, a check equation calculation module PCU and several storage modules. The storage module includes three parts, namely Channel initial information storage module RAM_F, iterative external information storage module RAM_M and decoding code word storage module RAM_C, such as figure 1 shown. For a QC-LDPC code decoder with a base matrix partition number of m×n, the VNU module contains n specific variable node computing units VNU j , 1≤j≤n, the CN...

AI Technical Summary

Problems solved by technology

Since the VPU and CPU alternately process two different data frames, the throughput of the decoder designed by this method is close to twice that of the traditional design method, but since each RAM port in the FPGA can only read and write data on one address at a time, Using the traditional static address management method, the reading and writing of each external information needs to occupy two different ports, and the number of ports for each RAM resource is at most 2, so the two frames of data of the decoder must be stored in the Among the different two RAMs, the RAM resource requirement of the decoder is twice that of the traditional method

In addition, because only the VNU is in the working state at the beginning of decoding, and the CNU has idle time slots, this method does not achieve the complete parallel work of the two processing units of the VNU and the CNU.

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