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Ultrahigh-speed and low-power-consumption QC-LDPC code decoder based on TDMP

A decoder and restorer technology, applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, data representation error detection/correction, etc., can solve decoding complexity and performance degradation Medium, low decoding complexity, poor performance, etc.

Inactive Publication Date: 2012-10-17
FUDAN UNIV
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Problems solved by technology

The first algorithm has the lowest decoding complexity, but poor performance; the second and third algorithms achieve a compromise between decoding complexity and performance

Method used

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  • Ultrahigh-speed and low-power-consumption QC-LDPC code decoder based on TDMP
  • Ultrahigh-speed and low-power-consumption QC-LDPC code decoder based on TDMP
  • Ultrahigh-speed and low-power-consumption QC-LDPC code decoder based on TDMP

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Embodiment Construction

[0098] The decoder adopts an improved TDMP (Turbo-Decoding Message-Passing) decoding algorithm, that is, the soft-input and soft-output engine (SISO Engine) in the TDMP algorithm is replaced by the Normalized Min-Sum algorithm. Each row block corresponds to a subcode (sub-iteration); all subcodes concatenated together correspond to one iteration. Information is passed not only between different iterations, but also between different subcodes (sub-iterations). At the same time, each line only needs to save the check node information components: minimum and second minimum absolute value, minimum value position, sign and flag. Therefore, the decoder can not only achieve the same fast convergence speed as the TDMP algorithm, but also reduce memory resources to the greatest extent. In addition, horizontal update and vertical update adopt dual-channel parallel computing and two-phase complete overlapping technology, which further improves the throughput of the decoder and the utili...

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Abstract

The invention belongs to the technical field of wireless communication and micro-electronics, in particular to an ultrahigh-speed low-power-consumption and low-density parity check code (QC-LDPC) decoder based on TDMP. Through symmetrizing six grades of production lines, interlacing row blocks and line blocks, re-sequencing nonzero sub matrixes, carrying out four-quadrant division on a sum value register pile and adopting the technology of reading and writing the bypass, the decoder carries out serial scanning in the row sequence, two nonzero sub matrixes are respectively processed in each clock period during horizontal updating and vertical updating. The horizontal updating and the vertical updating are fully overlapped. Particularly, the sum value register pile stores the sum values of variable nodes, and is also used as an FIFO for storing transient external information transferred between two phases. The structure of the decoder has strong configurability, can be easily transplanted into any other irregular or irregular QC-LDPC codes, and has the excellent decoding performance, the peak frequency can reach 214 MHz, the thuoughput can reach about 1 gigabit per second, and the chip power consumption is only 397 milliwatts.

Description

technical field [0001] The invention belongs to the technical field of wireless communication and microelectronics, in particular to an ultra-high-speed low-power configurable QC-LDPC code decoder, which can be applied to ultra-high-speed wireless digital communication, optical fiber communication, satellite communication, multimedia digital broadcasting and magnetic Optical storage and many other systems. Background technique [0002] Low-Density Parity-Check Codes (LDPC, Low-Density Parity-Check Codes) were invented by Dr. Gallager in the early 1960s. Due to its high decoding complexity, it was not taken seriously for more than 30 years. Until it was rediscovered and proved to have quite good power efficiency in the mid-1990s, LDPC codes were developed rapidly and widely used. Quasi-cyclic LDPC (QC-LDPC) code, as a very important branch, has linear coding complexity and a very favorable partial parallel decoding structure, and is widely used in DVB-S2, IEEE 802.11n (Wire...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 向波鲍丹黄双渠曾晓洋
Owner FUDAN UNIV
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