13results about How to "Reduce visits" patented technology

The application discloses a control method and device of a neural network execution, equipment and a storage medium, relates to the technical field of neural network inference, and comprises the following steps: acquiring an activated neuron set of a current neural network layer and corresponding weight data of the activated neuron set; performing calculation of the current neural network layer based on the activated neuron set and the weight data; in the process of performing calculation, determining an activated neuron set of a next neural network layer based on an intermediate result of calculation, and accordingly, pre-fetching weight data corresponding to the activated neuron set of the next neural network layer. According to the application, the activated neuron set of the next layer is determined in advance and the corresponding weight data is pre-fetched based on the intermediate result in the calculation process of the current layer, so that only the weight data related to the activated neuron needs to be loaded, the data access amount is reduced, and efficient inference is realized under the condition of limited bandwidth.

The invention relates to a quintuple matching method and device, computer equipment and a readable storage medium. The method comprises the steps that under the condition that a target quintuple of a to-be-processed message contains an internet protocol IP address, the IP address contained in the target quintuple is matched with a target IP filtering table to obtain an initial query address, the target IP filtering table stores the IP address associated with each IP matching rule table and the query address in a memory, and the initial query address is stored in the memory; the IP addresses of the quintuple matching rules associated with the same IP matching rule table are the same, determining a hierarchical query strategy of the target quintuple according to the quintuple information type contained in the target quintuple, and performing rule matching on the target quintuple by adopting the hierarchical query strategy and the initial query address. By adopting the method, the matching efficiency of the quintuple can be improved on the basis of reducing the access times of the memory.

The embodiment of the application belongs to the field of financial technology, and relates to a data batch request method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining batch request parameters according to a batch request instruction; obtaining preset parameter saving information, saving the batch request parameters in a predetermined time period according to the parameter saving information to obtain effective request parameters; requesting cached data according to the batch request parameters, and detecting whether the return result of the cached data is empty; if the return result of the cached data is not empty, obtaining update information of the cached data, updating the cached data according to the update information to obtain batch request data; and if the return result of the cached data is empty, screening the effective request parameters according to the update information to obtain to-be-requested parameters, and sending the to-be-requested parameters to a database for data request to obtain the batch request data. The application can effectively improve the data reading efficiency when data is requested in batches.

The invention discloses a data security processing method, a client, electronic equipment and a storage medium, and relates to the technical field of information security. The method comprises the steps that a file uploading request of an application program is intercepted through an adaptation library of a user mode file system; obtaining a physically isolated master key in the hardware cryptographic device, and deriving a unique file encryption key in combination with the target file information; calling a national secret algorithm library, performing symmetric encryption on file data by using the file encryption key, and performing asymmetric encryption on the file encryption key by using a public key; and generating an encrypted file header containing the encryption parameter and the ciphertext file key, and uploading and storing the encrypted file header. Through deep fusion of the hardware cryptographic device and the user mode file system, hardware-level physical isolation protection of the key, national cryptographic algorithm compliance support and transparent encryption and decryption are realized, key leakage is effectively prevented, and data security is improved.

The invention relates to the technical field of video processing, and provides a two-dimensional video processor, a video processing system, a video processing method and a program product, the two-dimensional video processor comprises more than two video processing sub-cores, each video processing sub-core comprises a plurality of image processing modules, and each image processing module is used for executing an image processing operation; when more than two video processing sub-cores are cascaded, the first video processing sub-core is used for reading a first video frame from the memory; the image processing modules in different video processing sub-cores are used for executing more than two image processing operations on the first video frame to obtain a processed video frame; and the at least one second video processing sub-core is used for writing the processed video frame into the memory, so that the number of access times to the memory during video frame processing can be effectively reduced, the video frame processing rate is accelerated, and the power consumption is reduced.

The application discloses an industrial process control data access method supporting a multi-user data exchange protocol and relates to the technical field of data access.The application sets a cache space, analyzes data information corresponding to each data in underlying data, obtains a data evaluation coefficient, and judges whether the data is suitable for being stored in the cache space, so that the data frequently accessed can be stored in the cache space, the number of access to the underlying data can be reduced, the data access speed is improved, whether expansion is needed is judged, the capacity of the cache space can be increased, more data can be stored in the cache, the situation that the cache hit rate is low can be reduced, the data access speed and response time are improved, the priority of each user data stream is set, limited resources can be more effectively allocated to important data streams, and the transmission rate and response time of the important data streams are improved.

The application discloses a convolutional neural network acceleration method and a convolutional neural network accelerator, and belongs to the technical field of computers. The convolutional neural network acceleration method comprises the following steps: obtaining model parameters of a pre-trained convolutional neural network, wherein the model parameters comprise convolution kernel parameters in each convolution layer; obtaining the average value of the central symmetric elements of each layer of convolution kernel, and replacing the average value with the parameters of the convolution kernel in each convolution layer; given an input / output sample pair, training the convolutional neural network based on the input / output sample pair, and ending the training process when a specified error range or a maximum number of times is reached. The processing mode of the convolution kernel center adopted by the application reduces the space required for weight storage and the access frequency of external memory, so that the acceleration of the convolutional neural network has the purpose of high operation efficiency and less required storage space.

Embodiments of the present application provide a physical volume access method and device, computer equipment and a storage medium, and belong to the field of disk storage. The method comprises the following steps: obtaining, according to first identification information of a volume group in a currently executed LVM command, second identification information of a physical volume involved in the execution of the LVM command from a mapping relationship file stored in an in-memory file system; and accessing the physical volume corresponding to the second identification information. The method greatly improves the access efficiency of the physical volume and the execution efficiency of the LVM command.

The application discloses an NPU on-chip storage and weight broadcast architecture and method based on inter-layer data residence. The architecture comprises a host processor / model compiler, an on-chip configuration and data bus, and a functional area, wherein the functional area comprises an inter-layer residence management area, an on-chip storage area, a data carrying area, a weight broadcast area, an NPU computing array area, and an output and recycling area. The architecture makes the intermediate feature maps that can be reused between network layers be reserved in the on-chip SRAM as much as possible, and makes the weight data be read once through a broadcast network and shared by multiple PEs, so that the number of external storage access times is reduced, power consumption is reduced, and inference throughput and on-chip storage utilization are improved.

The present application relates to a product quota checking method and device based on a cache index and a computer device. The method comprises the following steps: obtaining a product quota demand initiated by a user; obtaining a node index; performing a first check on the nodes in the node index to obtain a unique initial node matching the product quota demand; accessing a database using the initial node, and performing a second check on the initial node by the database to determine whether the initial node meets a product quota deduction condition; if the product quota deduction condition is met, determining that the initial node is a node to be deducted, and performing a quota deduction on the node to be deducted in the database; if the product quota deduction condition is not met, selecting other nodes from the node index as new unique initial nodes, and repeatedly determining whether the product quota deduction condition is met; updating the node information after the quota deduction asynchronously, and repeating the above steps. The present application improves the efficiency of product sales quota checking and deduction, reduces the number of database accesses by the application, and relieves the access pressure of the database.

The invention provides an arithmetic logic unit, an instruction processing method and computer equipment. The arithmetic logic unit comprises an internal cache space, an address allocation module and an operation module; the internal cache space is used for caching a reusable first source operand; the address allocation module is used for allocating a first cache address of a target operand in a first source operand to the first instruction under the condition that the target operand with the same storage address exists in a second source operand required by the first instruction to be processed and the first source operand; the storage address is an address of the corresponding source operand in an external storage space deployed outside the arithmetic logic unit; the first cache address is a cache address of the target operand in the internal cache space; and the operation module is used for executing an operation corresponding to the first instruction based on the target operand in the first cache address.

The invention relates to a memory graph database implementation method and device, electronic equipment and a storage medium, and belongs to the technical field of graph databases. The method comprises the steps that a vertex table is created, and vertexes corresponding to similar entities are stored in the same vertex table; edge blocks are established, the outgoing edge and the incoming edge of the same vertex are stored in different edge blocks, and the edges stored in the edge blocks correspond to the same vertex; creating a vertex label table and an edge label table, storing attribute field information of a single vertex table in the single vertex label table, and storing attribute information of an edge in the edge label table; for each vertex table, establishing a primary key mapping between a vertex attribute primary key and a vertex identifier; and establishing label mapping between the label table names corresponding to the various entities and the identifiers of the label tables. Therefore, the graph database is not limited by disk I / O and does not need to be managed by a buffer pool, large-range traversal can be reduced, the number of access times of the database can be reduced, and the retrieval efficiency and success rate of social networks, recommendation systems and knowledge graphs are greatly improved.

This application discloses a neural network processing method, apparatus, device, and storage medium, belonging to the field of neural network technology. The method includes: first, obtaining the bit width and on-chip memory capacity of a computer device, and the convolutional layer parameters of each convolutional layer in at least one convolutional layer of the neural network to be processed; then, exhaustively enumerating the block partitioning strategies for each convolutional layer based on the bit width, memory capacity, and convolutional layer parameters, obtaining multiple block partitioning strategies for each convolutional layer; and finally, determining a target block partitioning strategy from the multiple block partitioning strategies for each convolutional layer. The target block partitioning strategy for each convolutional layer refers to the block partitioning strategy that minimizes the number of accesses to off-chip memory among the multiple block partitioning strategies; that is, it is the more suitable block partitioning strategy for that convolutional layer. Thus, when executing each convolutional layer, the convolutional layer data is partitioned into blocks according to the determined suitable target block partitioning strategy, resulting in fewer accesses to off-chip memory and lower power consumption.