Montgomery analog multiplication algorithm and its analog multiplication and analog power operation circuit

A computing circuit and algorithm technology, applied in the fields of Montgomery modular multiplication algorithm, modular multiplication, and modular exponentiation circuit, can solve problems such as unsatisfactory computing speed, and achieve fast computing speed, increased flexibility, and less access times

Active Publication Date: 2004-04-28
DATANG MICROELECTRONICS TECH CO LTD
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Problems solved by technology

Since the coprocessor needs to frequently access

Method used

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  • Montgomery analog multiplication algorithm and its analog multiplication and analog power operation circuit
  • Montgomery analog multiplication algorithm and its analog multiplication and analog power operation circuit
  • Montgomery analog multiplication algorithm and its analog multiplication and analog power operation circuit

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Embodiment Construction

[0069] The algorithm of the present invention is based on the multi-precision Montgomery algorithm, based on the multi-precision CIOS algorithm and improved. In the algorithm, the same parameters as the existing multi-precision CIOS algorithm have the same meaning, constant R, multiplier x, multiplicand y, and modulus N are all s-bit r-ary integers (generally very large binary numbers, such as 1024 or 512 bits long), x=x s-1 x s-2 … x 1 x 0 , y=y s-1 the y s-2 ...y 1 the y 0 , n=n s-1 no s-2 …n 1 no 0 ;S used to save calculation results (and intermediate results) has s+1 bits, that is, S=S s S s-1 …S 1 S 0 ;r=2 k , K is the operation word length of the machine, which can be 8, 16, 32 or more; C 1 , T 1 , n’[0] are one-bit r-ary numbers, with a fixed K-bit machine word length, where C 1 Used to store the high bit or carry / borrow of the operation result, T 1 It is used to temporarily store the low-order or sum of the operation result, and n’[0] is a constant. ...

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Abstract

The analog multiplication algorithm of the present invention is one improvement of available multiple precision CIOS algorithm with reduced inner loop number from two to one and reduced external variable access times. The analog multiplication arithmetic circuit consists of addition, multiplication, address and loop computation module, data register, logic control module, inner circuit and some special functional modules; and has less operation steps, raised operation speed and data length capable of being set. The analog exponent operation circuits consist of the analog multiplication arithmetic circuit, CPU and system RAM, and under the control of the CPU, several times of analog multiplication operation are completed. Between two times of the analog multiplication operation, the basic address is altered based on dynamic data address pointer technology with greatly speeded analog exponent operation speed.

Description

technical field [0001] The invention relates to an encryption / decryption algorithm and a hardware circuit, in particular to a Montgomery modular multiplication algorithm, and a modular multiplication and modular exponentiation circuit applying the algorithm. Background technique [0002] With the continuous expansion of the application field of smart card technology, people's requirements for information security continue to increase. Among many encryption / decryption algorithms, the RSA algorithm is a popular public key algorithm, which can be used to realize digital signature, data encryption and other applications. [0003] The encryption process of the RSA encryption algorithm can be expressed as: E=C e mod N; the decryption process is C=E d mod N, where C, E, e, d, N are very large binary numbers, usually 512 bits, 1024 bits or longer, where C is the plaintext to be transmitted, (e, N) is the encryption key, e It is public, and the ciphertext E is generated after the ...

Claims

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Application Information

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IPC IPC(8): G06F7/38
Inventor 孙东昱龚宗跃赵红敏于鹏
Owner DATANG MICROELECTRONICS TECH CO LTD
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