144 results about "Memory architecture" patented technology

The invention is suitable for the technical field of natural language processing, relates to a hierarchical memory and context awareness retrieval method of a large role model and a related product, and aims to solve the problems of limited model memory duration, insufficient retrieval correlation and insufficient personality consistency in a long dialogue. According to the invention, a short-term-middle-term-long-term three-level memory architecture is adopted, and a memory attenuation and migration mechanism is combined, so that dynamic metabolism of memory is realized; related memories are recalled accurately through a context semantics and role personality double-sensitive double-stage retrieval algorithm; relying on a personality-linked memory fusion and response generation strategy, the reply is ensured to fit personality setting; and a closed-loop adaptive learning mechanism of dialogue-memory-retrieval-generation-feedback is constructed, and the memory quality is continuously optimized. According to the method, the role large model can have the human-like continuous memory ability, the continuity, retrieval accuracy and personality consistency of long dialogues are remarkably improved, and the long-term personalized interaction requirements of scenes such as digital personality assistants and dialogue agents are met.

The invention relates to the field of distributed information retrieval, and particularly discloses a memory architecture vector approximate retrieval method based on a graph neural network, which comprises the following steps of: constructing and dynamically maintaining a historical query-hit vector association graph for modeling a deep semantic relationship between a historical query and a successful retrieval result; inputting the features of the current query vector, the information of the current query vector subjected to neighborhood sampling and feature aggregation in the graph and the service scene label into a lightweight graph neural network, and predicting the approximate retrieval tolerance level of the query; on the basis of the prediction result, an optimal retrieval strategy is generated in a self-adaptive mode; and in combination with asynchronous result return and a progressive refinement mechanism based on residual error reordering, a user is responded at the first time, and continuous optimization and pushing of a better result are realized. According to the method, a query-level personalized retrieval strategy is realized, the retrieval precision, the response delay and the system resource consumption are effectively balanced, and the method is suitable for a large-scale high-dimensional vector retrieval scene.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention relates to the technical field of direct-current large-current power supply testing, in particular to a direct-current large-current power supply testing method and device. According to the invention, temperature, voltage and current are synchronously acquired through multiple channels, and data validity is marked; after smoothing processing, calculating compensation resistance by using a two-item temperature compensation formula; according to current characteristics, an abnormal threshold value is dynamically adapted in a current increasing / stabilizing / decreasing period, and a normal / early warning / shutdown instruction is output in a grading manner; performing correlation analysis on temperature-resistance and voltage-current characteristics to identify hidden defects; the weighted linear regression predicts future temperature / resistance and gives an early warning; data are stored in a layered mode, visualized display is achieved, and a report containing A / B / C grade rating is automatically generated. The device comprises a corresponding functional unit and a processor-memory architecture, and is suitable for large-current testing of multi-scene electrical equipment.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

The invention provides a memory-based man-machine interaction method, electronic equipment, a medium and a program product, and relates to the technical field of artificial intelligence. Based on an interaction scene corresponding to the multi-modal interaction input information, performing long and short term memory hierarchical storage processing, memory mixed retrieval processing and / or memory active forgetting processing on the multi-modal interaction input information to obtain processed target memory data; and generating a multi-modal interaction output result based on the target memory data. By adopting the method and the device, memory-based dynamic response can be realized in human-computer interaction based on a scenarized layered humanoid memory architecture.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

The invention belongs to the technical field of software development, and particularly provides a research and development-oriented long and short-term memory framework construction method and system, which adopts a layered memory architecture to construct four core modules including a short-term memory compressor, a medium-term memory aggregator, a long-term memory graph and a cross-layer memory router. The system takes multi-source input such as research and development dialogues, code snippets and project documents as a starting point, extracts research and development elements through semantic analysis and entity recognition technologies, compresses lengthy dialogues into structured short-term memory by utilizing an attention distillation mechanism, upgrades high-frequency short-term memory into medium-term knowledge fragments based on a time sequence attenuation algorithm, and improves the research and development efficiency. And constructing a long-term knowledge graph containing developer portraits, project dependence and normative standards by adopting a graph convolutional network. Context understanding accuracy, multi-round dialogue continuity and personalized service quality of a large model in a research and development scene are remarkably improved, and the method is suitable for mainstream research and development tool scenes such as IDE plug-ins, code review and architecture design.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

The present disclosure provides a method for implementing transformer models in analog compute-in-memory hardware. The method comprises training a target neural network using one or more operators on one or more graphics processing units, generating one or more datasets from full network traces to capture input-output relationships of non-vector-matrix multiplication operations, training one or more multi-layer perceptrons to approximate the non-vector-matrix multiplication operations using the one or more datasets, replacing the original non-vector-matrix multiplication operations with the trained one or more multi-layer perceptrons, and mapping the resulting multi-layer perceptron-only neural network to an analog compute-in-memory architecture. The non-vector-matrix multiplication operations comprise layer normalization operations, softmax operations, and GELU activation operations. The analog compute-in-memory architecture comprises crossbar arrays of memory elements that store weight values as analog quantities using conductance or capacitance properties.

The invention provides a knowledge base retrieval method and device based on a page type storage architecture, and relates to the technical field of artificial intelligence, and the method comprises the following steps: receiving a knowledge retrieval request sent by a current large model; matching a semantic vector corresponding to the knowledge retrieval request with a semantic vector of each knowledge block in a page table, and determining memory block numbers and page numbers of a plurality of target knowledge blocks; reading each target knowledge block in the memory based on the memory block number of each target knowledge block, and combining each target knowledge block based on the page number of each target knowledge block to generate a knowledge retrieval result corresponding to the knowledge retrieval request; and sending a knowledge retrieval result to the current large model. According to the method and the device provided by the invention, through an innovative index construction mode and a retrieval mechanism, in combination with a page type storage architecture and a vector distance retrieval technology, the knowledge acquisition efficiency of a large model is improved, efficient processing, rapid retrieval and flexible updating of knowledge data are realized, and the overall performance of a knowledge base is improved.

Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface and executes the one or more layers.

The application discloses a memory driving, emotion sensing and output controllable AI implementation method based on end-side privacy calculation, a storage medium and a terminal device, and belongs to the technical field of artificial intelligence. The application aims at the core bottleneck of the prior art: firstly, the RAG memory architecture is an external module, which is disconnected with the whole cognitive process, and the human-like interaction capability is insufficient; secondly, the cloud output is uncontrollable, and the privacy security, full-scene deployment and expansion capability cannot be considered. The core innovation of the application is as follows: a special memory system taking cognitive causal weight as a grading standard is constructed, memory is taken as a dynamic kernel of the AI cognitive process, and is deeply bound with output constraint rules; an end-side anchored core cognitive closed loop is designed, a three-fold coincidence checking mechanism of the cloud returned content is newly added, a double-mode large model calling is compatible, and end-side cloud encryption expansion is originally supported. The application significantly improves the human-like interaction capability and output stability, realizes controllable user data sovereignty, and can be widely applied to AI scenes such as emotional accompaniment and personalized assistant.

An agricultural system includes a sink region sensor configured to collect information regarding a sink region; a vehicle sensor configured to collect information regarding current vehicle weight when proximate to the sink region; and a controller. The controller includes processor and memory architecture executing control logic to: receive the sink region information and extract sink region characteristics; receive the current vehicle weight; determine a potential soil compaction impact of the agricultural work vehicle traversing the sink region in view of the sink region characteristics and the current vehicle weight; generate commands associated with a sink region path to at least partially avoid the sink region when the potential soil compaction impact exceeds a soil compaction constraint for the sink region; and generate commands to proceed along the default path when the potential soil compaction impact does not exceed the soil compaction constraint.

In the disclosed embodiment, a graphics processing unit (GPU) is configured to operate data in multiple memory spaces. Data cache switching logic can cache data for the GPU switching logic, including data from multiple memory spaces. The data cache switching logic can include tag switching logic configured to compare the following information from access requests to the data cache switching logic with tags of entries in the data cache switching logic: memory space information and a tag portion of a requested address. The tag portion of a requested address can be different for at least two of the multiple memory spaces (e.g., a different set of bit indices within the address). The disclosed techniques can advantageously enable caching for different clients with different cache line sizes, address spaces, etc., e.g., in uniform memory architectures.

This application discloses a verification apparatus, verification method, storage medium, and chip for a memory controller. The verification apparatus includes: an information extraction module for acquiring memory configuration information based on memory architecture feature data; an information processing module for generating a physical address to be accessed in the memory based on the logical address to be accessed, the memory type, and the memory configuration information; and an access module for accessing the memory via a backdoor based on the physical address to be accessed, to write verification data into the memory, and / or read data to be verified from the memory. The information processing module is further used to generate verification data and / or perform data analysis on the data to be verified to verify the memory controller. This verification apparatus establishes a verification environment for assisting in the verification of the memory controller and facilitates rapid modification of the verification environment.

This invention discloses a method, device, electronic device, storage medium, and process for implementing an emotional intelligent agent and its memory system based on a state machine, belonging to the field of artificial intelligence and human-computer interaction technology. The method includes: constructing a multi-dimensional emotional state machine, defining state vectors containing basic and advanced emotions, and combining a natural decay mechanism and an empathy adjustment algorithm to achieve dynamic emotion updates; establishing a hierarchical memory system with emotion binding, binding emotional states as metadata to memory entries, and achieving memory compression, archiving, and enhanced retrieval through a three-level architecture of short-term, medium-term, and long-term combined with importance scoring; adopting a hierarchical streaming response mechanism, splitting the response process into two layers: rapid emotional feedback and substantive content generation, and reducing interaction latency using streaming output and speculative execution; and using emotional states as the core driving source to synchronously control text tone, speech synthesis intonation, and virtual character animation. This invention, by integrating an emotional state machine and a hierarchical memory architecture, enhances the agent's personality continuity and long-term companionship ability, achieving low-latency, multimodal synchronous natural human-computer interaction.

A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and / or far memory host controller (FMHC) makes decisions about the power and / or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and / or performance state of the FM for a given time. The power and / or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

The invention discloses an ICU (Intensive Care Unit) long-time-sequence decision-making auxiliary method based on hierarchical memory and dynamic abstract, which comprises the following steps of: organizing electronic health record data of a patient into a hierarchical memory architecture which comprises instantaneous working memory, abstract scene memory and archiving retrieval memory, and when a diagnosis and treatment query is received, storing the data into a database; a dynamic prompt assembler dynamically assembles a final prompt by extracting and retrieving data from three memory hierarchies, and finally submits the final prompt to a large language model to generate a diagnosis and treatment suggestion. According to the method, the cognitive process of clinical experts can be simulated, structured and hierarchical management can be performed on ICU long-time-sequence data, and latest dynamic and medium-term trends and key historical events are intelligently integrated when clinical query is responded, so that the problems of context length limitation and information submergence confronted when LLM processes long-time-sequence clinical data are fundamentally solved.

An artificial-intelligence computing device integrates at least two compute stacks and a hybrid memory subsystem of volatile and non-volatile high-bandwidth memory within an all-silicon domain. The volatile memory stores frequently written activations and key-value caches, while the non-volatile memory stores largely static model weights. Compute stacks communicate over silicon interconnects exceeding one hundred terabits per second, enabling sustained trillion-parameter inference locally without external storage and with energy below one picojoule per bit.

The invention discloses a cross-point array memory of a high-density three-dimensional ferroelectric capacitor, and belongs to the field of semiconductor memories. According to the invention, a horizontal BL / vertical WL cross-point array type three-dimensional ferroelectric memory architecture is designed by utilizing the three-dimensional stacking capability and the character / bit line symmetry characteristic of the cross-point array type three-dimensional ferroelectric memory, and compared with the traditional vertical BL / horizontal WL type three-dimensional memory architecture, the cross-point array type three-dimensional ferroelectric memory architecture has the advantages that the structure is simple; according to the invention, the influence of the limitation of signal margin on the extension of the three-dimensional ferroelectric memory in the vertical direction is eliminated, so that the three-dimensional cross-point array type ferroelectric memory is supported to realize the stacking of higher layers, and the bit density potential is ultrahigh.

The present invention relates to the technical field of compute-in-memory. Disclosed are a compute-in-memory system, a control method, a control apparatus, and an electronic device. The compute-in-memory system comprises: a memory circuit, a sensing circuit, and a control circuit. The memory circuit converts an input signal into an output signal on the basis of stored weight data; and the sensing circuit senses the output signal. The control circuit controls, during a first time period, the memory circuit to be in a first operating state and the sensing circuit to be in a disabled state, and controls, during a second time period, the memory circuit to be in a second operating state and the sensing circuit to be in an enabled state. In this way, the control circuit controls a memory cell group to implement establishment of a stable state in advance, thereby establishing conditions in advance for computation of the memory cell group; the sensing circuit is disabled in the condition establishment process, thereby preventing sensing and outputting of a non-computation result; and then the memory cell group is triggered to perform computation, and sensing of a computation result is triggered. This greatly improves computing efficiency, thereby improving computing performance of a compute-in-memory architecture.

Provided are a deep learning network performance simulation method and system in a PIM architecture. The deep learning network performance simulation method according to an embodiment of the present invention designs a noise model simulating noise in a PIM architecture and simulates deep learning network operation performance on the basis of the noise model. In addition, a deep learning network performance simulation method according to another embodiment of the present invention checks / evaluates whether network pruning can reduce a loss in accuracy of a deep learning network due to noise generated in the PIM architecture and contribute to robust operation.

This disclosure relates to a control system and controller for a work vehicle. A control system for a work vehicle includes: a power source comprising an engine configured to generate power and at least one electric motor; a transmission comprising a plurality of clutches coupled together and configured to selectively engage according to a plurality of transmission modes to transmit power from the engine and at least one electric motor along a power flow path to drive an output shaft of a powertrain; and a controller coupled to the power source and the transmission. The controller has a processor memory architecture configured to: monitor the electric motor speed of the at least one electric motor; and when the electric motor speed is less than a first predetermined stall speed threshold, generate and execute a clutch modulation command for the transmission, such that at least one clutch portion of the plurality of clutches along the power flow path engages.

It is proposed an in-memory computing (IMC) circuit (116), comprising:-an array comprising a matrix of memory cells (112) having a plurality of rows and columns wherein the memory cells (112) within the same column are connected by a common bit line and the memory cells within the same row are connected by a common word line, wherein the memory unit (112) is configured for storing weights of a trained neural network architecture, wherein the order of the weights is pre-disorganized; -at least one decoder (126) configured for outputting, using the key, a number of shift operations to be performed by each of the plurality of shift registers (128); -the plurality of shift registers (128) configured to shift an output of the array according to an output of the decoder (126).

Methods and systems, including computer-readable media, are described for implementing auto-indexing mechanisms for reduction-based processing-in-memory architectures of an integrated memory device. A method includes, for a first PiM command, storing a first location index corresponding to a row and column of a memory bank from which a first weight scale is obtained and executing a computation using the first weight scale based on the first PiM command. The method includes, for a second PiM command, computing a distance value based on the first location index and location information of a second weight, determining, based on the distance value, a second weight scale index for obtaining a second weight scale and executing, based on the second PiM command, a computation using the second weight scale obtained using the second weight scale index.

Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.