312 results about "Memory architecture" patented technology

A system and method for implementing a convergent intelligence fabric (CIF) for distributed artificial intelligence operations. The CIF architecture integrates tensor-theoretic foundations, probabilistic cache management, precision-aware memory operations, quantum-resistant security, and neural-based optimization within a unified framework. The system orchestrates asynchronous, multi-hop data flow among computational resources while maintaining data security through per-block encryption and identity-based access control. Key components include a universal multi-model KV cache subsystem, agent-parallel disaggregation pipelines, reinforcement learning-based orchestration, and neuromorphic memory integration. Advanced implementations incorporate graphon-enhanced memory for sparse graph sequences, multi-modal cognitive persistent memory, and quantum-resistant asynchronous multi-domain trust protocols. The system enables efficient cross-agent collaboration, sophisticated knowledge sharing, and secure cross-domain operations while optimizing computational resources and maintaining strict privacy guarantees across distributed AI deployments.

The invention relates to the field of artificial intelligence hardware acceleration, and discloses a memristor-based multilevel compression collaborative optimization neural network deployment method and device, and a storage medium. The method comprises the following steps: carrying out progressive structured pruning on a pre-training model based on a dual-drive scoring mechanism of an L1 norm and gradient sensitivity and hardware feedback, and generating a hardware-friendly sparse weight structure; the characteristics of the memristor are simulated through a micro-nonlinear conductance modeling function, and network weight and conductance parameters are synchronously optimized to reduce errors by adopting mixed precision quantification of four bits of a convolutional layer and two bits of a full-connection layer; a conductance drift and read-write noise model is injected, and the anti-interference capability of the model is improved in combination with adaptive noise enhancement and KL divergence loss; and mapping the optimized model to a memristor memory architecture to complete weight coding and reasoning. Through collaborative optimization of pruning, quantification and distillation, the problems of insufficient storage density, non-ideal characteristic interference and algorithm and hardware mismatch in memristor deployment are solved.

The embodiment of the invention provides a memory processing method based on an intelligent agent, a storage medium and an electronic device, a memory architecture of the intelligent agent comprises a first memory layer, a second memory layer and a third memory layer, the first memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent, and the second memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent. The second memory layer is used for storing structured events extracted from historical dialogue information, and the third memory layer is used for storing pattern induction memory obtained by performing pattern induction on the structured dialogue events; the method comprises the steps that in response to current round dialogue input information of a target interaction object, target storage information associated with the current round dialogue input information is retrieved from at least one memory layer in a memory architecture, and the current round dialogue input information and the target storage information are assembled into a current cue word; and submitting the current prompt word to a specified interaction model through the intelligent agent, and outputting a response result of the specified interaction model to the interaction object.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

The invention is suitable for the technical field of natural language processing, relates to a hierarchical memory and context awareness retrieval method of a large role model and a related product, and aims to solve the problems of limited model memory duration, insufficient retrieval correlation and insufficient personality consistency in a long dialogue. According to the invention, a short-term-middle-term-long-term three-level memory architecture is adopted, and a memory attenuation and migration mechanism is combined, so that dynamic metabolism of memory is realized; related memories are recalled accurately through a context semantics and role personality double-sensitive double-stage retrieval algorithm; relying on a personality-linked memory fusion and response generation strategy, the reply is ensured to fit personality setting; and a closed-loop adaptive learning mechanism of dialogue-memory-retrieval-generation-feedback is constructed, and the memory quality is continuously optimized. According to the method, the role large model can have the human-like continuous memory ability, the continuity, retrieval accuracy and personality consistency of long dialogues are remarkably improved, and the long-term personalized interaction requirements of scenes such as digital personality assistants and dialogue agents are met.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention relates to the technical field of artificial intelligence interaction, in particular to a full-life-cycle AI accompanying agent system and method.The full-life-cycle AI accompanying agent system comprises a core engine layer, a business service layer, a basic tool layer, a data layer and an interface layer, and the full-life-cycle AI accompanying agent method comprises the steps that multi-modal data, including biological signals, behavior data, voice data, expression data and environment data, of a user are collected; constructing a user digital twinborn model, and updating model parameters through a weighted learning algorithm; identifying a user cognition development stage, and dynamically adjusting interaction complexity and an expression mode; emotional connection is established, and resonance feedback is generated through multi-mode emotional recognition and memory retrieval; according to the method, interaction memory is stored, cross-stage retrieval is realized, data management is performed by adopting a hierarchical memory architecture, and accurate judgment of a cognitive stage is realized by synchronously collecting multi-dimensional data such as behavior tracks, language texts and biological signals of a user and combining a development psychology theoretical model to construct a feature association map.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes first computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising one or more first columns and a first plurality of rows of a CIM array. The apparatus also include a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising the one or more first columns and a second plurality of rows of the CIM array. The first plurality of rows may be different than the second plurality of rows.

The invention relates to the field of distributed information retrieval, and particularly discloses a memory architecture vector approximate retrieval method based on a graph neural network, which comprises the following steps of: constructing and dynamically maintaining a historical query-hit vector association graph for modeling a deep semantic relationship between a historical query and a successful retrieval result; inputting the features of the current query vector, the information of the current query vector subjected to neighborhood sampling and feature aggregation in the graph and the service scene label into a lightweight graph neural network, and predicting the approximate retrieval tolerance level of the query; on the basis of the prediction result, an optimal retrieval strategy is generated in a self-adaptive mode; and in combination with asynchronous result return and a progressive refinement mechanism based on residual error reordering, a user is responded at the first time, and continuous optimization and pushing of a better result are realized. According to the method, a query-level personalized retrieval strategy is realized, the retrieval precision, the response delay and the system resource consumption are effectively balanced, and the method is suitable for a large-scale high-dimensional vector retrieval scene.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention relates to the technical field of direct-current large-current power supply testing, in particular to a direct-current large-current power supply testing method and device. According to the invention, temperature, voltage and current are synchronously acquired through multiple channels, and data validity is marked; after smoothing processing, calculating compensation resistance by using a two-item temperature compensation formula; according to current characteristics, an abnormal threshold value is dynamically adapted in a current increasing / stabilizing / decreasing period, and a normal / early warning / shutdown instruction is output in a grading manner; performing correlation analysis on temperature-resistance and voltage-current characteristics to identify hidden defects; the weighted linear regression predicts future temperature / resistance and gives an early warning; data are stored in a layered mode, visualized display is achieved, and a report containing A / B / C grade rating is automatically generated. The device comprises a corresponding functional unit and a processor-memory architecture, and is suitable for large-current testing of multi-scene electrical equipment.

The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

The invention discloses an intelligent storage integrated memory storage architecture. The intelligent storage integrated memory storage architecture comprises a computing type memory semantic solid state disk which is used for providing a unified memory address space based on a computing expression link protocol and supporting a host to perform byte granularity access through a loading / storage instruction; an internal intelligent layering and granularity management mechanism is arranged; a flexible data placement mechanism capable of perceiving semantics is set; the host operating system is connected with the computing type memory semantic solid state disk and is used for receiving the long-delay prompt sent by the computing type memory semantic solid state disk and carrying out context switching; and a uniform abstract interface layer is arranged, and is used for uniformly managing byte granularity memory access to the computing type memory semantic solid state disk and transmission of data placement semantic prompts, and submitting a task unloading request to the embedded computing engine. By means of the mode, the problem of multi-impedance mismatch of traditional hierarchical storage in performance, cost, energy efficiency and intelligent processing can be solved.

Methods, systems, and apparatus, including computational instructions / programs encoded on non-transitory computer-readable media, are disclosed for decreasing state transition latency by determining a target type of idle mode. A system determines a first sequence of mode transitions. Each mode transition in the first sequence is a transition from an execution mode of to an idle mode of the memory device. The system determines, before occurrence of each mode transition in the first sequence, a type of idle mode from multiple among multiple mode types based on a dynamically updated energy model. The system iteratively generates and pre-programs a first set of control signals based on the corresponding type of idle mode for each mode transition in the first sequence, and based on the first set of control signals, the system iteratively triggers occurrence of each mode transition in the first sequence. Each triggered occurrence causes the memory device to transition to a corresponding type of idle mode.

The invention provides a memory-based man-machine interaction method, electronic equipment, a medium and a program product, and relates to the technical field of artificial intelligence. Based on an interaction scene corresponding to the multi-modal interaction input information, performing long and short term memory hierarchical storage processing, memory mixed retrieval processing and / or memory active forgetting processing on the multi-modal interaction input information to obtain processed target memory data; and generating a multi-modal interaction output result based on the target memory data. By adopting the method and the device, memory-based dynamic response can be realized in human-computer interaction based on a scenarized layered humanoid memory architecture.

Processor(s) can receive a first natural language (NL) based input as part of a dialog between a user of a client device and an automated assistant that is accessible at the client device; process, using a first machine learning (ML) model, the first NL based input to generate a first inference associated with the user and a confidence indicator for the first inference, the confidence indicator for the first inference indicative of a degree of confidence that the first inference is true; store the first inference and the confidence indicator for the first inference in a database; process, using a second ML model, the first inference and additional data to generate a modified confidence indicator for the first inference and store the modified confidence indicator in the database; and determine, based at least on the modified confidence indicator for the first inference, whether to process, using a first large language model (LLM), the first inference with a second NL based input to generate a first NL based response.

The invention provides a near-memory computing system based on an RISC-V instruction set architecture, and belongs to the technical field of near-memory computing. The system comprises a near storage architecture instruction set module based on software and hardware collaboration, an instruction set model module, an energy efficiency instruction path module and a storage and calculation integrated module. The near storage architecture instruction set module integrates an operation code configuration and operation mechanism in each instruction of the RISC-V instruction set, so that the special instruction set realizes corresponding execution control; the instruction set model module adopts an instruction arrangement mode of neural network layer structure mapping, and minimizes the number of instructions through a loop instruction to support an iteration process; the special instruction set of the energy efficiency instruction path module follows an instruction path for sequentially executing each stage; and the storage and calculation integrated module dynamically switches a calculation path according to an instruction demand by fusing storage and calculation. According to the customized RISC-V ISA for the NMC system provided by the invention, neural network reasoning with energy efficiency optimization is realized.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

The invention discloses a software and hardware collaborative optimization method for a hybrid in-memory architecture, which comprises the following steps of: performing joint feature representation on a target AI algorithm and an in-memory computing architecture, extracting context features, and parameterizing in-memory computing unit configuration, a neural network processor assembly line, a multi-core interconnection topology and a storage level interface of the in-memory computing architecture; an off-line reference data set is constructed, a predictive agent model is trained, discrete architecture parameters are processed by the model by adopting an embedding method, feature association is learned by applying an encoder with a self-attention mechanism, joint prediction of multi-dimensional PPA indexes is realized through a parallel prediction network, and a feasible region constraint learning mechanism is introduced in training; the trained agent model is embedded into a multi-objective evolutionary algorithm, the energy efficiency ratio, the average computing power utilization rate, the model execution delay and the like serve as optimization objectives, chip area efficiency and power consumption constraints are met at the same time, and a Pareto optimal in-memory computing architecture configuration set is searched.

The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.

A compact collision detector can be configured for low power operation to facilitate collision avoidance. In one embodiment, a nanoscale collision detector can be based on a photodetector, stacked on top of a non-volatile and programmable memory architecture that imitates the escape response of LGMD neuron at a frugal energy expenditure of few nanojoules (nJ) and at the same time can offer orders of magnitude benefit in device footprint (e.g. by having a relatively small size). Embodiments of the collision detector can be utilized in smart, low-cost, task-specific, energy efficient and miniaturized collision detection systems configured for collision avoidance.

The invention belongs to the technical field of software development, and particularly provides a research and development-oriented long and short-term memory framework construction method and system, which adopts a layered memory architecture to construct four core modules including a short-term memory compressor, a medium-term memory aggregator, a long-term memory graph and a cross-layer memory router. The system takes multi-source input such as research and development dialogues, code snippets and project documents as a starting point, extracts research and development elements through semantic analysis and entity recognition technologies, compresses lengthy dialogues into structured short-term memory by utilizing an attention distillation mechanism, upgrades high-frequency short-term memory into medium-term knowledge fragments based on a time sequence attenuation algorithm, and improves the research and development efficiency. And constructing a long-term knowledge graph containing developer portraits, project dependence and normative standards by adopting a graph convolutional network. Context understanding accuracy, multi-round dialogue continuity and personalized service quality of a large model in a research and development scene are remarkably improved, and the method is suitable for mainstream research and development tool scenes such as IDE plug-ins, code review and architecture design.

A multi-stack computing chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of compute stacks, and each compute stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the compute stacks to at least one other compute stack for sharing the memory in a coherent manner across the plurality of compute stacks.

An integrated circuit memory device can include a plurality of banks of memory, each of the banks of memory including a first pair of sub-arrays comprising first and second sub-arrays, the first pair of sub-arrays configured to store data in memory cells of the first pair of sub-arrays, a first row buffer memory circuit located in the integrated circuit memory device adjacent to the first pair of sub-arrays and configured to store first row data received from the first pair of sub-arrays and configured to transfer the row data into and / or out of the first row buffer memory circuit, and a first sub-array level processor circuit in the integrated circuit memory device adjacent to the first pair of sub-arrays and operatively coupled to the first row data, wherein the first sub-array level processor circuit is configured to perform column oriented processing a sparse matrix kernel stored, at least in-part, in the first pair of sub-arrays, with input vector values stored, at least in part, in the first pair of sub-arrays to provide output vector values representing products of values stored in columns of the sparse matrix kernel with the input vector values.

Methods, systems, and apparatus, including computational instructions / programs encoded on non-transitory computer-readable media, are disclosed to implement collaborative controls for dynamic voltage & frequency scaling ("DVFS") using an integrated circuit comprising a System-on-Chip ("SoC") and a memory device coupled to the SoC. The system identifies user-experience criteria for generating an output of a machine-learning ("ML") model implemented at the integrated circuit and determines a performance target required to satisfy the user-experience criteria. The system computes a first target operating point of a processing-in-memory ("PiM") block inside the memory device and a second target operating point of the host core. The system performs computations at the PiM block using the target operating point established based on the control signals. The first and second target operating points achieve the best energy efficiency, while the PiM block and the host core collaboratively satisfy the user-experience criteria.

The invention provides a static memory cell and a memory architecture which can improve the storage stability and reduce the area overhead at the same time. The static memory cell includes: a first inverter circuit having an output electrically connected to a first storage node and an input electrically connected to a second storage node; the output end of the second inverter circuit is electrically connected to the second storage node, and the input end of the second inverter circuit is electrically connected to the first storage node; a read operation transistor having a gate electrically connected to the first storage node, a drain electrically connected to a read bit line, and a source electrically connected to a read word line; and a write pass transistor having a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.