239 results about "Memory architecture" patented technology

The embodiment of the invention provides a memory processing method based on an intelligent agent, a storage medium and an electronic device, a memory architecture of the intelligent agent comprises a first memory layer, a second memory layer and a third memory layer, the first memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent, and the second memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent. The second memory layer is used for storing structured events extracted from historical dialogue information, and the third memory layer is used for storing pattern induction memory obtained by performing pattern induction on the structured dialogue events; the method comprises the steps that in response to current round dialogue input information of a target interaction object, target storage information associated with the current round dialogue input information is retrieved from at least one memory layer in a memory architecture, and the current round dialogue input information and the target storage information are assembled into a current cue word; and submitting the current prompt word to a specified interaction model through the intelligent agent, and outputting a response result of the specified interaction model to the interaction object.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

The invention is suitable for the technical field of natural language processing, relates to a hierarchical memory and context awareness retrieval method of a large role model and a related product, and aims to solve the problems of limited model memory duration, insufficient retrieval correlation and insufficient personality consistency in a long dialogue. According to the invention, a short-term-middle-term-long-term three-level memory architecture is adopted, and a memory attenuation and migration mechanism is combined, so that dynamic metabolism of memory is realized; related memories are recalled accurately through a context semantics and role personality double-sensitive double-stage retrieval algorithm; relying on a personality-linked memory fusion and response generation strategy, the reply is ensured to fit personality setting; and a closed-loop adaptive learning mechanism of dialogue-memory-retrieval-generation-feedback is constructed, and the memory quality is continuously optimized. According to the method, the role large model can have the human-like continuous memory ability, the continuity, retrieval accuracy and personality consistency of long dialogues are remarkably improved, and the long-term personalized interaction requirements of scenes such as digital personality assistants and dialogue agents are met.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention relates to the technical field of artificial intelligence interaction, in particular to a full-life-cycle AI accompanying agent system and method.The full-life-cycle AI accompanying agent system comprises a core engine layer, a business service layer, a basic tool layer, a data layer and an interface layer, and the full-life-cycle AI accompanying agent method comprises the steps that multi-modal data, including biological signals, behavior data, voice data, expression data and environment data, of a user are collected; constructing a user digital twinborn model, and updating model parameters through a weighted learning algorithm; identifying a user cognition development stage, and dynamically adjusting interaction complexity and an expression mode; emotional connection is established, and resonance feedback is generated through multi-mode emotional recognition and memory retrieval; according to the method, interaction memory is stored, cross-stage retrieval is realized, data management is performed by adopting a hierarchical memory architecture, and accurate judgment of a cognitive stage is realized by synchronously collecting multi-dimensional data such as behavior tracks, language texts and biological signals of a user and combining a development psychology theoretical model to construct a feature association map.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes first computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising one or more first columns and a first plurality of rows of a CIM array. The apparatus also include a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising the one or more first columns and a second plurality of rows of the CIM array. The first plurality of rows may be different than the second plurality of rows.

The invention relates to the field of distributed information retrieval, and particularly discloses a memory architecture vector approximate retrieval method based on a graph neural network, which comprises the following steps of: constructing and dynamically maintaining a historical query-hit vector association graph for modeling a deep semantic relationship between a historical query and a successful retrieval result; inputting the features of the current query vector, the information of the current query vector subjected to neighborhood sampling and feature aggregation in the graph and the service scene label into a lightweight graph neural network, and predicting the approximate retrieval tolerance level of the query; on the basis of the prediction result, an optimal retrieval strategy is generated in a self-adaptive mode; and in combination with asynchronous result return and a progressive refinement mechanism based on residual error reordering, a user is responded at the first time, and continuous optimization and pushing of a better result are realized. According to the method, a query-level personalized retrieval strategy is realized, the retrieval precision, the response delay and the system resource consumption are effectively balanced, and the method is suitable for a large-scale high-dimensional vector retrieval scene.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention relates to the technical field of direct-current large-current power supply testing, in particular to a direct-current large-current power supply testing method and device. According to the invention, temperature, voltage and current are synchronously acquired through multiple channels, and data validity is marked; after smoothing processing, calculating compensation resistance by using a two-item temperature compensation formula; according to current characteristics, an abnormal threshold value is dynamically adapted in a current increasing / stabilizing / decreasing period, and a normal / early warning / shutdown instruction is output in a grading manner; performing correlation analysis on temperature-resistance and voltage-current characteristics to identify hidden defects; the weighted linear regression predicts future temperature / resistance and gives an early warning; data are stored in a layered mode, visualized display is achieved, and a report containing A / B / C grade rating is automatically generated. The device comprises a corresponding functional unit and a processor-memory architecture, and is suitable for large-current testing of multi-scene electrical equipment.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

The invention provides a memory-based man-machine interaction method, electronic equipment, a medium and a program product, and relates to the technical field of artificial intelligence. Based on an interaction scene corresponding to the multi-modal interaction input information, performing long and short term memory hierarchical storage processing, memory mixed retrieval processing and / or memory active forgetting processing on the multi-modal interaction input information to obtain processed target memory data; and generating a multi-modal interaction output result based on the target memory data. By adopting the method and the device, memory-based dynamic response can be realized in human-computer interaction based on a scenarized layered humanoid memory architecture.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

The invention discloses a software and hardware collaborative optimization method for a hybrid in-memory architecture, which comprises the following steps of: performing joint feature representation on a target AI algorithm and an in-memory computing architecture, extracting context features, and parameterizing in-memory computing unit configuration, a neural network processor assembly line, a multi-core interconnection topology and a storage level interface of the in-memory computing architecture; an off-line reference data set is constructed, a predictive agent model is trained, discrete architecture parameters are processed by the model by adopting an embedding method, feature association is learned by applying an encoder with a self-attention mechanism, joint prediction of multi-dimensional PPA indexes is realized through a parallel prediction network, and a feasible region constraint learning mechanism is introduced in training; the trained agent model is embedded into a multi-objective evolutionary algorithm, the energy efficiency ratio, the average computing power utilization rate, the model execution delay and the like serve as optimization objectives, chip area efficiency and power consumption constraints are met at the same time, and a Pareto optimal in-memory computing architecture configuration set is searched.

The invention belongs to the technical field of software development, and particularly provides a research and development-oriented long and short-term memory framework construction method and system, which adopts a layered memory architecture to construct four core modules including a short-term memory compressor, a medium-term memory aggregator, a long-term memory graph and a cross-layer memory router. The system takes multi-source input such as research and development dialogues, code snippets and project documents as a starting point, extracts research and development elements through semantic analysis and entity recognition technologies, compresses lengthy dialogues into structured short-term memory by utilizing an attention distillation mechanism, upgrades high-frequency short-term memory into medium-term knowledge fragments based on a time sequence attenuation algorithm, and improves the research and development efficiency. And constructing a long-term knowledge graph containing developer portraits, project dependence and normative standards by adopting a graph convolutional network. Context understanding accuracy, multi-round dialogue continuity and personalized service quality of a large model in a research and development scene are remarkably improved, and the method is suitable for mainstream research and development tool scenes such as IDE plug-ins, code review and architecture design.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

An agricultural system includes a sink region sensor configured to collect information regarding a sink region within the field; a vehicle sensor configured to collect information regarding current vehicle weight when proximate to the sink region within the field; and a controller. The controller includes processor and memory architecture executing control logic to: receive the sink region information and extract sink region characteristics; receive the current vehicle weight; determine a potential soil compaction impact of the agricultural work vehicle traversing the sink region in view of the sink region characteristics and the current vehicle weight; and generate commands associated with a sink region prescription to address the sink region at a later time when the potential soil compaction impact exceeds a sink region constraint; and generate commands to proceed along the default path when the potential soil compaction impact does not exceed the sink region constraint.

The present disclosure relates to an apparatus using a chipset-based storage architecture. The memory architecture includes: a plurality of accelerator memory devices on a package substrate; a front-end chip on the package substrate and configured to perform communication with a host device; and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, and coupled to each other in a daisy chain scheme.

A Fully Analog STate-Space Compute-In-Memory (FAST-CIM) architecture implements cascaded CIM arrays that maintain continuous analog signal flow throughout neural network computations. Sequential data patches are processed through cascaded CIM arrays, where a feedforward CIM array performs initial vector-matrix multiplication using analog computations within memory cells, and the analog output flows directly through a gain circuit to a recurrent CIM array without digital conversion. The gain circuit converts analog current signals to voltage signals, enabling direct analog connection between the cascaded arrays. The recurrent CIM array executes State-Space Model (SSM) computations, processing the cascaded analog signals along with previous state information maintained by a State Write and Propagate (SWAP) circuit that stores states using capacitive elements. The cascaded array configuration eliminates analog-to-digital and digital-to-analog converters between processing stages, achieving reduced power consumption and latency compared to conventional implementations that require digital interfaces between CIM arrays.

The present disclosure provides a method for implementing transformer models in analog compute-in-memory hardware. The method comprises training a target neural network using one or more operators on one or more graphics processing units, generating one or more datasets from full network traces to capture input-output relationships of non-vector-matrix multiplication operations, training one or more multi-layer perceptrons to approximate the non-vector-matrix multiplication operations using the one or more datasets, replacing the original non-vector-matrix multiplication operations with the trained one or more multi-layer perceptrons, and mapping the resulting multi-layer perceptron-only neural network to an analog compute-in-memory architecture. The non-vector-matrix multiplication operations comprise layer normalization operations, softmax operations, and GELU activation operations. The analog compute-in-memory architecture comprises crossbar arrays of memory elements that store weight values as analog quantities using conductance or capacitance properties.

A torque determination system for a driveline of a work vehicle includes a driveline component having a housing, intermeshing torque transmitting components within the housing, and a shaft supporting the transmitting components for rotation about an axis of the shaft. A shaft connected to the housing for relative rotation is configured to transfer an axial thrust load from the transmission component to the housing along an axis of the shaft. The system includes a strain sensor mounted on the housing to sense local strain caused by the axial thrust load and output a corresponding strain value. A control unit equipped with a processing and memory architecture executes logic to receive the strain value, derive a torque value associated with the transmission component based on the strain value, and output the derived torque value for use on the work vehicle.

The disclosure describes systems and methods for mixed‑mode, mixed‑precision computation using a configurable compute engine for vector–matrix operations. A processing system selects an operating mode including at least a floating‑point mode or an integer mode for the compute engine. Operand storage and format preprocessing route differently sized element representations through shared lanes. In floating‑point mode, compute circuitry generates a mantissa product and a product exponent, and alignment applies power‑of‑two control through a selection network, including as part of a fused multiply‑accumulate path. Parallel adder trees feed a hierarchical output accumulator sized to the selected precision. Normalization operates at a wider intermediate precision, applies block‑level scaling with dequantization, and, in lower‑precision operation, performs groupwise normalization with an intermediate‑precision combine to preserve a constant compute‑block size. Implementations integrate the compute engine within a memory macro with double buffering or deploy the compute engine as a standalone accelerator.

The invention provides a knowledge base retrieval method and device based on a page type storage architecture, and relates to the technical field of artificial intelligence, and the method comprises the following steps: receiving a knowledge retrieval request sent by a current large model; matching a semantic vector corresponding to the knowledge retrieval request with a semantic vector of each knowledge block in a page table, and determining memory block numbers and page numbers of a plurality of target knowledge blocks; reading each target knowledge block in the memory based on the memory block number of each target knowledge block, and combining each target knowledge block based on the page number of each target knowledge block to generate a knowledge retrieval result corresponding to the knowledge retrieval request; and sending a knowledge retrieval result to the current large model. According to the method and the device provided by the invention, through an innovative index construction mode and a retrieval mechanism, in combination with a page type storage architecture and a vector distance retrieval technology, the knowledge acquisition efficiency of a large model is improved, efficient processing, rapid retrieval and flexible updating of knowledge data are realized, and the overall performance of a knowledge base is improved.

This invention relates to techniques for performing memory indirect addressing for memory architectures. Various embodiments generally relate to apparatus, methods, and other techniques for receiving a request from a core associated with a memory operation to read or write data, the request including a first address and an offset, the first address identifying a memory location. Embodiments include: a first iteration of performing a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to be used to perform a memory operation on a computing resource or a second iteration of performing the memory indirect addressing operation.

Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.

The present application relates to the technical field of intelligent health management, and particularly relates to a multi-modal intelligent health management method and system based on continuous memory, comprising: multi-modal preprocessing of voice, text, images and sensor data input by a user to obtain multi-modal health data; adopting a hierarchical continuous memory storage strategy to obtain a long-term memory item set through three-layer memory architecture step-by-step compression processing; constructing a health memory graph network based on a memory consolidation and association integration strategy; adopting a global health portrait incremental update and memory portrait driven parameter mapping strategy to map a health portrait into a role parameter vector; adopting a memory retrieval and knowledge graph enhanced reasoning strategy to combine historical memory recall, knowledge graph reasoning and drug information management results to generate and output a health management response. The present application realizes the organic unification of continuous memory accumulation, personalized accompaniment and intelligent health reasoning for a health management scene.

Disclosed are a memory circuit, a processing-in-memory apparatus, and an electronic device. The memory circuit comprises a memory cell group, which comprises a plurality of memory cells. Each memory cell comprises a first transistor, a second transistor, and a capacitor. A first terminal of the first transistor and a second driving terminal of the second transistor are connected to the capacitor. In each memory cell in the memory cell group, a first driving terminal of the first transistor is connected to a first control terminal, a second terminal is connected to a second control terminal, and the first control terminal and the second control terminal are configured to control weight data stored in the memory cell. Among the plurality of memory cells in the memory cell group, third terminals of the second transistors are respectively connected to a plurality of input terminals, and fourth terminals are connected to an output terminal. The memory cell group receives a plurality of input signals by means of the plurality of input terminals, converts the plurality of input signals into an output signal on the basis of the weight data stored in the plurality of memory cells, and outputs the output signal at the output terminal. The memory circuit can be used in processing-in-memory architectures, and has higher reliability and processing efficiency.