386 results about "Memory architecture" patented technology

A system and method for implementing a convergent intelligence fabric (CIF) for distributed artificial intelligence operations. The CIF architecture integrates tensor-theoretic foundations, probabilistic cache management, precision-aware memory operations, quantum-resistant security, and neural-based optimization within a unified framework. The system orchestrates asynchronous, multi-hop data flow among computational resources while maintaining data security through per-block encryption and identity-based access control. Key components include a universal multi-model KV cache subsystem, agent-parallel disaggregation pipelines, reinforcement learning-based orchestration, and neuromorphic memory integration. Advanced implementations incorporate graphon-enhanced memory for sparse graph sequences, multi-modal cognitive persistent memory, and quantum-resistant asynchronous multi-domain trust protocols. The system enables efficient cross-agent collaboration, sophisticated knowledge sharing, and secure cross-domain operations while optimizing computational resources and maintaining strict privacy guarantees across distributed AI deployments.

The invention relates to the field of artificial intelligence hardware acceleration, and discloses a memristor-based multilevel compression collaborative optimization neural network deployment method and device, and a storage medium. The method comprises the following steps: carrying out progressive structured pruning on a pre-training model based on a dual-drive scoring mechanism of an L1 norm and gradient sensitivity and hardware feedback, and generating a hardware-friendly sparse weight structure; the characteristics of the memristor are simulated through a micro-nonlinear conductance modeling function, and network weight and conductance parameters are synchronously optimized to reduce errors by adopting mixed precision quantification of four bits of a convolutional layer and two bits of a full-connection layer; a conductance drift and read-write noise model is injected, and the anti-interference capability of the model is improved in combination with adaptive noise enhancement and KL divergence loss; and mapping the optimized model to a memristor memory architecture to complete weight coding and reasoning. Through collaborative optimization of pruning, quantification and distillation, the problems of insufficient storage density, non-ideal characteristic interference and algorithm and hardware mismatch in memristor deployment are solved.

The embodiment of the invention provides a memory processing method based on an intelligent agent, a storage medium and an electronic device, a memory architecture of the intelligent agent comprises a first memory layer, a second memory layer and a third memory layer, the first memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent, and the second memory layer is used for storing historical dialogue information of interactive dialogue between at least one interactive object and the intelligent agent. The second memory layer is used for storing structured events extracted from historical dialogue information, and the third memory layer is used for storing pattern induction memory obtained by performing pattern induction on the structured dialogue events; the method comprises the steps that in response to current round dialogue input information of a target interaction object, target storage information associated with the current round dialogue input information is retrieved from at least one memory layer in a memory architecture, and the current round dialogue input information and the target storage information are assembled into a current cue word; and submitting the current prompt word to a specified interaction model through the intelligent agent, and outputting a response result of the specified interaction model to the interaction object.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

The invention provides a cache replacement method, device and system, and relates to the field of computers. And the computing node in the distributed system sends a first read operation request to the memory node, wherein the first read operation request is used for indicating to read the access information of the plurality of data objects from the memory node. Then, the computing node uses a first cache replacement algorithm in a plurality of cache replacement algorithms to respectively compute the popularity of the plurality of data objects based on the access information of the plurality of data objects; and finally, when the computing node needs to carry out cache replacement, sending a cache replacement request to the memory node according to the popularity of the plurality of data objects, so as to indicate to replace cold data in the plurality of data objects with the data object to be inserted into the memory node. In this way, the computing node executes the cache replacement algorithm according to the global access information, and accurate cache replacement is achieved in the distributed system of the separated memory architecture.

The present application relates to the field of computers, and provides a cache replacement method and device, and a system. A compute node in a distributed system sends to a memory node a first read operation request used for instructing to read access information of a plurality of data objects from the memory node; then, the compute node uses a first cache replacement algorithm among a plurality of cache replacement algorithms to respectively calculate the popularities of the plurality of data objects on the basis of the access information of the plurality of data objects; finally, when needing to perform cache replacement, on the basis of the popularities of the plurality of data objects, the compute node sends to the memory node a cache replacement request used for instructing to replace cold data in the plurality of data objects with a data object to be inserted into the memory node. In this way, the compute node executes a cache replacement algorithm on the basis of global access information, thereby realizing accurate cache replacement in the distributed system of a disaggregated memory architecture.

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

A computing device includes a first circuit package including a first electronic integrated circuit (EIC) and a first photonic integrated circuit (PIC). The first circuit package includes a plurality of compute nodes, a first plurality of routers connected to the plurality of compute nodes, and a plurality of intra-chip bidirectional photonic channels connecting the first plurality of routers into an intra-chip network. The computing system includes a second circuit package including a second EIC and a second PIC. The second circuit package includes a plurality of memory nodes and a second plurality of routers connected to the plurality of memory nodes. The computing system includes at least one inter-chip bidirectional photonic channel connecting the first plurality of routers and the second plurality of routers into an inter-chip bidirectional photonic network configured to transmit messages between the first circuit package and the second circuit package.

The invention relates to a multi-back-end separated memory system and an optimization control method thereof, the multi-back-end separated memory system comprises an intelligent far memory multi-back-end management control module and a multi-back-end far memory switch, the intelligent far memory multi-back-end management control module analyzes and processes calling of page errors and page switching triggering, and the multi-back-end far memory switch is used for switching the multi-back-end far memory switch. Switching instruction information and parameter regulation and control instruction information are obtained; and the multi-rear-end remote memory exchanger receives and executes the switching instruction information and the parameter regulation and control instruction information, runs applications on the separated memory architecture and the multi-rear-end remote memory software system, and releases resources after running is finished. By supporting a memory exchange strategy and a system architecture of a plurality of heterogeneous far-end separated memory rear ends, parallel access of a plurality of paths of far memories is realized to improve data throughput, application characteristics are analyzed, and intelligent rear end switching and data exchange parameter adjustment are realized; parallel access of a plurality of memory exchange back-end devices, fine-grained parameter configuration of a remote memory data access path, real-time switching of a plurality of memory exchange back-ends and an intelligent control and management method of the remote memory access path can be realized.

An approach is provided for an adaptive memory architecture for an artificial intelligence (AI) environment. The approach involves, for example, configuring a first memory component configured as a first-level (L1) memory cache equivalent to store first data that is transient. The approach also involves configuring a second memory component as a second-level (L2) memory cache equivalent to store second data that is not held within the in-memory data store and is accessed at greater than an L2 frequency threshold. The approach further involves configuring a third memory component as a third-level (L3) memory cache equivalent to store third data that is accessed at less than the L2 frequency threshold and at greater than an L3 frequency threshold. The approach further involves configuring a fourth memory component as a fourth-level (L4) memory cache equivalent to store fourth data that is accessed at less than the L3 frequency threshold.

The invention is suitable for the technical field of natural language processing, relates to a hierarchical memory and context awareness retrieval method of a large role model and a related product, and aims to solve the problems of limited model memory duration, insufficient retrieval correlation and insufficient personality consistency in a long dialogue. According to the invention, a short-term-middle-term-long-term three-level memory architecture is adopted, and a memory attenuation and migration mechanism is combined, so that dynamic metabolism of memory is realized; related memories are recalled accurately through a context semantics and role personality double-sensitive double-stage retrieval algorithm; relying on a personality-linked memory fusion and response generation strategy, the reply is ensured to fit personality setting; and a closed-loop adaptive learning mechanism of dialogue-memory-retrieval-generation-feedback is constructed, and the memory quality is continuously optimized. According to the method, the role large model can have the human-like continuous memory ability, the continuity, retrieval accuracy and personality consistency of long dialogues are remarkably improved, and the long-term personalized interaction requirements of scenes such as digital personality assistants and dialogue agents are met.

In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention relates to the technical field of artificial intelligence interaction, in particular to a full-life-cycle AI accompanying agent system and method.The full-life-cycle AI accompanying agent system comprises a core engine layer, a business service layer, a basic tool layer, a data layer and an interface layer, and the full-life-cycle AI accompanying agent method comprises the steps that multi-modal data, including biological signals, behavior data, voice data, expression data and environment data, of a user are collected; constructing a user digital twinborn model, and updating model parameters through a weighted learning algorithm; identifying a user cognition development stage, and dynamically adjusting interaction complexity and an expression mode; emotional connection is established, and resonance feedback is generated through multi-mode emotional recognition and memory retrieval; according to the method, interaction memory is stored, cross-stage retrieval is realized, data management is performed by adopting a hierarchical memory architecture, and accurate judgment of a cognitive stage is realized by synchronously collecting multi-dimensional data such as behavior tracks, language texts and biological signals of a user and combining a development psychology theoretical model to construct a feature association map.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes first computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising one or more first columns and a first plurality of rows of a CIM array. The apparatus also include a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising the one or more first columns and a second plurality of rows of the CIM array. The first plurality of rows may be different than the second plurality of rows.

The invention relates to the field of distributed information retrieval, and particularly discloses a memory architecture vector approximate retrieval method based on a graph neural network, which comprises the following steps of: constructing and dynamically maintaining a historical query-hit vector association graph for modeling a deep semantic relationship between a historical query and a successful retrieval result; inputting the features of the current query vector, the information of the current query vector subjected to neighborhood sampling and feature aggregation in the graph and the service scene label into a lightweight graph neural network, and predicting the approximate retrieval tolerance level of the query; on the basis of the prediction result, an optimal retrieval strategy is generated in a self-adaptive mode; and in combination with asynchronous result return and a progressive refinement mechanism based on residual error reordering, a user is responded at the first time, and continuous optimization and pushing of a better result are realized. According to the method, a query-level personalized retrieval strategy is realized, the retrieval precision, the response delay and the system resource consumption are effectively balanced, and the method is suitable for a large-scale high-dimensional vector retrieval scene.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention discloses a two-stage data pool data loading method based on a CXL memory architecture. According to the method, a CXL memory serves as a cold data pool to store data with low use frequency, and a DRAM memory of a server node serves as a hot data pool to store data with high use frequency. When data in a CXL memory is used for many times, the data monitor judges whether the data can be transferred into hot data or not through a delay caching strategy and caches the hot data. In addition, a self-adaptive caching strategy is adopted to keep the hot data in a server for a certain time through a hot data pool, so that the application performance is improved. And dynamically learning a caching strategy by the hot data pool. And when the hot data is added or expelled every time, a caching strategy is selected according to the weight of the LRU-S, the weight of the LFU-S and the weight of the FIFO expert. And meanwhile, the hot data pool comprises a historical list, the decision regret expelling behavior of the cache strategy is allowed, and wrong decisions are punished.

The invention relates to the technical field of direct-current large-current power supply testing, in particular to a direct-current large-current power supply testing method and device. According to the invention, temperature, voltage and current are synchronously acquired through multiple channels, and data validity is marked; after smoothing processing, calculating compensation resistance by using a two-item temperature compensation formula; according to current characteristics, an abnormal threshold value is dynamically adapted in a current increasing / stabilizing / decreasing period, and a normal / early warning / shutdown instruction is output in a grading manner; performing correlation analysis on temperature-resistance and voltage-current characteristics to identify hidden defects; the weighted linear regression predicts future temperature / resistance and gives an early warning; data are stored in a layered mode, visualized display is achieved, and a report containing A / B / C grade rating is automatically generated. The device comprises a corresponding functional unit and a processor-memory architecture, and is suitable for large-current testing of multi-scene electrical equipment.

The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

The disclosure provides for systems and methods for improving bandwidth and latency associated with executing data requests in disaggregated memory by leveraging usage indicators (also referred to as usage value), such as “freshness” of data operators and processing “gravity” of near memory compute functions. Examples of the systems and methods disclosed herein generate data operators comprising near memory compute functions offloaded proximate to disaggregated memory nodes, assign a usage value to each data operator based on at least one of: (i) a freshness indicator for each data operators, and (ii) a gravity indicator for each near memory compute function; and allocate data operations to the data operators based on the usage value.

Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.

Embodiments of the present application provide a memory processing method based on an agent, a storage medium and an electronic device, wherein the memory architecture of the agent includes a first memory layer, a second memory layer and a third memory layer, the first memory layer is used to store historical dialogue information of an interactive dialogue between at least one interactive object and the agent, the second memory layer is used to store structured events extracted from the historical dialogue information, and the third memory layer is used to store pattern induction memories obtained by pattern induction on the structured events; the method includes: in response to current round dialogue input information of a target interactive object, retrieving target stored information associated with the current round dialogue input information from at least one memory layer in the memory architecture, and assembling the current round dialogue input information and the target stored information into a current prompt; submitting the current prompt to a specified interactive model through the agent, and outputting a response result of the specified interactive model to the interactive object.

The invention discloses an intelligent storage integrated memory storage architecture. The intelligent storage integrated memory storage architecture comprises a computing type memory semantic solid state disk which is used for providing a unified memory address space based on a computing expression link protocol and supporting a host to perform byte granularity access through a loading / storage instruction; an internal intelligent layering and granularity management mechanism is arranged; a flexible data placement mechanism capable of perceiving semantics is set; the host operating system is connected with the computing type memory semantic solid state disk and is used for receiving the long-delay prompt sent by the computing type memory semantic solid state disk and carrying out context switching; and a uniform abstract interface layer is arranged, and is used for uniformly managing byte granularity memory access to the computing type memory semantic solid state disk and transmission of data placement semantic prompts, and submitting a task unloading request to the embedded computing engine. By means of the mode, the problem of multi-impedance mismatch of traditional hierarchical storage in performance, cost, energy efficiency and intelligent processing can be solved.

The invention discloses a giant page memory management method and system for a hierarchical large memory architecture, and the method comprises the steps: when an application program requests memory allocation, if the memory allocation is based on mmap and the size of the requested memory is smaller than the length of a single physical giant page memory, executing memory allocation; whether free memory fragments meeting a first condition exist in the head or not is judged, and if yes, the memory with the size of the requested memory is distributed to the application program; and if not, judging whether the tail residual idle memory meets the condition, and if so, allocating the memory with the size of the requested memory to the application program. According to the method, whether the free memory meeting the request memory size exists or not is traversed in all the physical giant page memories allocated for the application program, the request memory size can be allocated to the used physical giant page memories when the conditions are met, and therefore the memory space is fully utilized, memory waste is reduced, and system resources are saved.