37 results about "Multilevel memory" patented technology

An apparatus has cache circuitry providing a cache storage to store data for access by processing circuitry, and request handling circuitry arranged to process requests, each request providing an address indication for associated data. The request handling circuitry determines with reference to the address indication whether the associated data is available in the cache circuitry. The cache circuitry forms a given level of a multi-level memory hierarchy, and the request handling circuitry is responsive to determining that the associated data is unavailable in the cache circuitry to issue an onward request to cause the associated data to be retrieved into the cache circuitry from a lower level of the multi-level memory hierarchy than the given level. Prefetch circuitry issues, as one type of request to be handled by the request handling circuitry, prefetch requests, and the request handling circuitry is arranged in response to a given prefetch request to retrieve into the cache circuitry the associated data in anticipation of that associated data being requested by the processing circuitry. In addition, trigger circuitry, responsive to a specified condition being detected in respect of the given prefetch request, issues a prefetch trigger signal for receipt by control circuitry associated with further cache circuitry at a higher level of the multi-level memory hierarchy, to cause a higher level prefetch procedure to be triggered by the control circuitry to retrieve the associated data from the cache circuitry into the further cache circuitry.

A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.

Data is often stored in a multi-level memory (e.g., a quad-level cell (QLC)) using a mapping that balances the bit error rate among the various pages in the memory. The number of sense operations needed to read each page is also relatively balanced. The data storage device presented herein can decide to store data using a non-balanced mapping if there is a desire to later read a low-resolution version of the data. With a non-balanced mapping, fewer sense operations are needed to read the lower page of data, which contains the low-resolution version of the data. Other pages can be read if a higher-resolution version of the data is desired, and techniques can be used to mitigate the higher bit error rate that may be encountered in those other pages because of use of the non-balanced mapping.

The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

[0009] Provided herein are systems and methods for efficient data relocation within a multilevel memory cache. In particular, the method may include (i) storing particular data structures, or tiles, in a first memory cache containing open order data representing open orders for either buying or selling financial instruments at successive price levels that fall within a defined price range between a most aggressive price and a least aggressive price, (ii) storing multiple tiles in a second memory cache containing open order data representing open orders for either buying or selling financial instruments at prices that are outside the defined price range, and relocating the tiles between the first and second memory caches in response to changes in the open order data for either buying or selling financial instruments at the most aggressive price.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuity memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

The invention belongs to the field of memories, and particularly discloses a multi-level memory based on a superlattice phase change material and a preparation method thereof, and the memory comprises a substrate, a waveguide layer, and a superlattice phase change material layer. The waveguide layer covers the substrate, the superlattice phase change material layer covers the substrate, and the superlattice phase change material layer is formed by periodically and alternately stacking two different phase change materials; the waveguide layer is used for receiving an incident light pulse and uniformly transmitting the energy of the light pulse to the superlattice phase change material layer; and the superlattice phase change material layer is used for controlling the ratio of a crystalline state to an amorphous state by utilizing the conversion between the crystalline state and the amorphous state through a thermo-optic effect according to the power and the pulse width of the optical pulse, and adjusting the projection rates under different powers and pulse widths. According to the invention, multi-level information storage can be realized, and the information capacity and the storage efficiency of the memory are improved.

The invention relates to a high speed imager circuit. Disclosed is a high dynamic range (HDR) imaging system in which the speed of digitization and storage of image data is improved by efficient signal management without additional resources. By managing data transfer processes in successive approximation register (SAR) analog-to-digital converter (ADC) circuits, using techniques such as control signal synchronization, multi-level memory, and time multiplexing, higher frame rates can be achieved without relying on increasing bandwidth with additional channels and without increasing power consumption or complexity of the imaging system.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

This disclosure provides a memory device including a NOR memory string and a method of operating the same. The memory device of this disclosure implements partial polarization to provide a reference signal for read operations. The reference signal realizes a third logic state in a ferroelectric memory transistor that is distinguishable from a first logic state and a second logic state (e.g., a logic state associated with a write state and an erase state). The memory device of this disclosure provides a reference signal for read operations by averaging a first signal associated with the write state and a second signal associated with the erase state of the ferroelectric memory transistor. The memory device of this disclosure also provides a multilevel memory cell that stores multiple logic bits in each memory cell by implementing one or more partial polarization states.

The invention relates to a multi-level memory cell read and write back system. A memory device includes an array of memory cells including at least first and second memory cells. Each of the cells may be configured to store charge at two or more non-zero charge levels. A first local amplifier circuit may be configured to provide a first comparison result at a first amplifier output node and during a first read phase based on a first cell voltage signal and a first voltage reference signal of the first memory cell and a second read based on the first cell voltage signal and a second voltage reference signal A second comparison result is provided during the sampling stage. First and second latch circuits may be configured to store information about the first comparison result and the second comparison result, respectively. In an example, information from the first and second memory cells may be used together to provide a 3-bit codeword.

The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

The invention relates to techniques for managing parity information for data transfer operations. A memory system may generate additional parity information for data stored in a set of multi-level memory cells. The memory system may receive a command to store data and may use a mapping to determine whether a destination physical address of the data includes a weak wordline. The memory system may use a mapping between a first set of single-level memory cells and a second set of multi-level memory cells configured to store a plurality of data bits to generate parity information for the data. The memory system may store the data and the parity information to the first set of single-level memory cells and may transfer the data and the parity information from the first set of single-level memory cells to the second set of multi-level memory cells.

A memory device includes an array of memory cells including at least first and second memory cells. Each of the cells can be configured to store a charge at two or more non-zero charge levels. A first local amplifier circuit can be configured to provide, at a first amplifier output node and during a first read phase, a first comparison result based on a first cell voltage signal of the first memory cell and a first voltage reference signal, and to provide, during a second read phase, a second comparison result based on the first cell voltage signal and a second voltage reference signal. First and second latch circuits can be configured to store information about the first and second comparison results, respectively. In an example, information from the first and second memory cells can be used together to provide a 3-bit codeword.

A memory device includes first combinatory logic configured to receive multiple-digit representations of stored voltage values from each of N respective memory cells in a first memory array, and each of the memory cells is configured to store a charge having one of at least three different charge levels. The first combinatory logic can provide a first multiple-bit word, based on the received multiple-digit representations of the stored voltage values, and a number of bits in the first multiple-bit word is greater than N. 

An IC device includes first and second terminals that receive bit and source line signals configured by a control circuit, a resistive memory device having first and second resistance levels in first and second states, and a switching device including control and body terminals and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, the current path, responsive to a first voltage level at the control terminal, has a first conductance level in a first programmed state and a second conductance level greater than the first conductance level in a second programmed state, and the control circuit sets the resistive memory device to one of the first or second resistance levels after programming the switching device to the second conductance level and while increasing the second conductance level responsive to a second voltage level at the body terminal.

Embodiments of the present invention may relate to a memory controller that may include a memory interface and logic circuitry coupled to the memory interface. In some embodiments, the logic circuitry is used to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array associated with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations at least in part based on the result of the determination of the temperature difference. Other embodiments may be described and / or claimed.

Systems and methods are herein disclosed that relate to generating read enabling windows in a multi-rank memory system that includes a memory controller connected to a plurality of memory ranks via a shared physical channel. The systems and methods disclosed herein provide for opening and closing read enabling windows for a memory controller in response to processing of data strobe signals output by a memory rank connected to the memory controller. By processing of the data strobe signals, a preamble can be detected that precedes a data transmission from a memory rank to the memory controller and a post-amble that follows the data transmission can also be detected. Detection of the preamble triggers opening of the read enabling window, and detection of the post-amble triggers closing of the read enabling window.

An apparatus has cache circuitry providing a cache storage to store data for access by processing circuitry, and request handling circuitry arranged to process requests, each request providing an address indication for associated data. The request handling circuitry determines with reference to the address indication whether the associated data is available in the cache circuitry. The cache circuitry forms a given level of a multi-level memory hierarchy, and the request handling circuitry is responsive to determining that the associated data is unavailable in the cache circuitry to issue an onward request to cause the associated data to be retrieved into the cache circuitry from a lower level of the multi-level memory hierarchy than the given level. Prefetch circuitry issues, as one type of request to be handled by the request handling circuitry, prefetch requests, and the request handling circuitry is arranged in response to a given prefetch request to retrieve into the cache circuitry the associated data in anticipation of that associated data being requested by the processing circuitry. In addition, trigger circuitry, responsive to a specified condition being detected in respect of the given prefetch request, issues a prefetch trigger signal for receipt by control circuitry associated with further cache circuitry at a higher level of the multi-level memory hierarchy, to cause a higher level prefetch procedure to be triggered by the control circuitry to retrieve the associated data from the cache circuitry into the further cache circuitry.

The application discloses a data synchronization method and device based on gray isolation, equipment and medium. Including: receiving a data request for updating function, the data request is used for obtaining at least one request data; for each request data, according to the order from low to high of the memory level, using the preset gray strategy to read the request field from the first level memory in the multi-level memory step by step, and the field value obtained by reading the request field from each memory is taken as the return data; in the case of reading the first return data from the Pth memory, it is checked whether there is second return data consistent with the gray of the target program in the P return data, the target program is the program receiving the data request; the memory where the second return data is located is the target memory, and the bubble strategy is used to synchronize the second return data to all memories with memory level less than the target memory.

To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.

A hardware-based electronic trading system is disclosed that minimizes external memory accesses, thereby reducing overall latency. Order data for all open orders of a particular symbol, side, and price may be organized into a defined data structure, or tile, that can be fetched from an external memory cache. Once loaded into an internal memory cache of an FPGA or other fixed logic, the tile may be accessed often with minimal delay to obtain order data for multiple open orders having the same symbol, side, and price. To further minimize the number of external memory accesses, external memory can be provisioned as an asymmetric, multi-level memory cache that is tailored for handling large data sets of matching engine books and ticker plant services. In particular, the multi-level memory cache can be implemented using external memory units in the form of DRAMs for storing tiles according to a price priority scheme.

An IC device includes first and second terminals that receive bit and source line signals configured by a control circuit, a resistive memory device having first and second resistance levels in first and second states, and a switching device including control and body terminals and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, the current path, responsive to a first voltage level at the control terminal, has a first conductance level in a first programmed state and a second conductance level greater than the first conductance level in a second programmed state, and the control circuit sets the resistive memory device to one of the first or second resistance levels after programming the switching device to the second conductance level and while increasing the second conductance level responsive to a second voltage level at the body terminal.

In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.

The invention belongs to the technical field of image processing and computer vision, and particularly relates to an infrared sequence small target detection method based on multilevel memory fusion, which comprises the following steps: coding infrared video data after frame extraction processing of infrared video sequence data to obtain different scale features and generate pseudo coding information of a first frame; a memory value vector and a memory key vector are obtained through coding of the working memory vector coding module, a memory matching result is obtained through the working memory vector reading module, and meanwhile, a short-term memory strategy and a long-term memory strategy are fused; and the memory reading result and the cross-layer connection feature information are sent into a cross-layer attention gate module to obtain fused information, feature mapping of the small target is obtained through layer-by-layer up-sampling of a decoder, and the small target is successfully segmented from the infrared image. According to the invention, through mutual cooperation of multi-level memory strategies, association information of front and back frames is fully extracted, the detection precision of a small target under a complex background is effectively improved, and the false alarm rate is significantly reduced.