22 results about "Multilevel memory" patented technology

Data is often stored in a multi-level memory (e.g., a quad-level cell (QLC)) using a mapping that balances the bit error rate among the various pages in the memory. The number of sense operations needed to read each page is also relatively balanced. The data storage device presented herein can decide to store data using a non-balanced mapping if there is a desire to later read a low-resolution version of the data. With a non-balanced mapping, fewer sense operations are needed to read the lower page of data, which contains the low-resolution version of the data. Other pages can be read if a higher-resolution version of the data is desired, and techniques can be used to mitigate the higher bit error rate that may be encountered in those other pages because of use of the non-balanced mapping.

The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

[0009] Provided herein are systems and methods for efficient data relocation within a multilevel memory cache. In particular, the method may include (i) storing particular data structures, or tiles, in a first memory cache containing open order data representing open orders for either buying or selling financial instruments at successive price levels that fall within a defined price range between a most aggressive price and a least aggressive price, (ii) storing multiple tiles in a second memory cache containing open order data representing open orders for either buying or selling financial instruments at prices that are outside the defined price range, and relocating the tiles between the first and second memory caches in response to changes in the open order data for either buying or selling financial instruments at the most aggressive price.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuity memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

This disclosure provides a memory device including a NOR memory string and a method of operating the same. The memory device of this disclosure implements partial polarization to provide a reference signal for read operations. The reference signal realizes a third logic state in a ferroelectric memory transistor that is distinguishable from a first logic state and a second logic state (e.g., a logic state associated with a write state and an erase state). The memory device of this disclosure provides a reference signal for read operations by averaging a first signal associated with the write state and a second signal associated with the erase state of the ferroelectric memory transistor. The memory device of this disclosure also provides a multilevel memory cell that stores multiple logic bits in each memory cell by implementing one or more partial polarization states.

The invention relates to a multi-level memory cell read and write back system. A memory device includes an array of memory cells including at least first and second memory cells. Each of the cells may be configured to store charge at two or more non-zero charge levels. A first local amplifier circuit may be configured to provide a first comparison result at a first amplifier output node and during a first read phase based on a first cell voltage signal and a first voltage reference signal of the first memory cell and a second read based on the first cell voltage signal and a second voltage reference signal A second comparison result is provided during the sampling stage. First and second latch circuits may be configured to store information about the first comparison result and the second comparison result, respectively. In an example, information from the first and second memory cells may be used together to provide a 3-bit codeword.

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

A memory device includes an array of memory cells including at least first and second memory cells. Each of the cells can be configured to store a charge at two or more non-zero charge levels. A first local amplifier circuit can be configured to provide, at a first amplifier output node and during a first read phase, a first comparison result based on a first cell voltage signal of the first memory cell and a first voltage reference signal, and to provide, during a second read phase, a second comparison result based on the first cell voltage signal and a second voltage reference signal. First and second latch circuits can be configured to store information about the first and second comparison results, respectively. In an example, information from the first and second memory cells can be used together to provide a 3-bit codeword.

A memory device includes first combinatory logic configured to receive multiple-digit representations of stored voltage values from each of N respective memory cells in a first memory array, and each of the memory cells is configured to store a charge having one of at least three different charge levels. The first combinatory logic can provide a first multiple-bit word, based on the received multiple-digit representations of the stored voltage values, and a number of bits in the first multiple-bit word is greater than N. 

An IC device includes first and second terminals that receive bit and source line signals configured by a control circuit, a resistive memory device having first and second resistance levels in first and second states, and a switching device including control and body terminals and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, the current path, responsive to a first voltage level at the control terminal, has a first conductance level in a first programmed state and a second conductance level greater than the first conductance level in a second programmed state, and the control circuit sets the resistive memory device to one of the first or second resistance levels after programming the switching device to the second conductance level and while increasing the second conductance level responsive to a second voltage level at the body terminal.

Systems and methods are herein disclosed that relate to generating read enabling windows in a multi-rank memory system that includes a memory controller connected to a plurality of memory ranks via a shared physical channel. The systems and methods disclosed herein provide for opening and closing read enabling windows for a memory controller in response to processing of data strobe signals output by a memory rank connected to the memory controller. By processing of the data strobe signals, a preamble can be detected that precedes a data transmission from a memory rank to the memory controller and a post-amble that follows the data transmission can also be detected. Detection of the preamble triggers opening of the read enabling window, and detection of the post-amble triggers closing of the read enabling window.

An apparatus has cache circuitry providing a cache storage to store data for access by processing circuitry, and request handling circuitry arranged to process requests, each request providing an address indication for associated data. The request handling circuitry determines with reference to the address indication whether the associated data is available in the cache circuitry. The cache circuitry forms a given level of a multi-level memory hierarchy, and the request handling circuitry is responsive to determining that the associated data is unavailable in the cache circuitry to issue an onward request to cause the associated data to be retrieved into the cache circuitry from a lower level of the multi-level memory hierarchy than the given level. Prefetch circuitry issues, as one type of request to be handled by the request handling circuitry, prefetch requests, and the request handling circuitry is arranged in response to a given prefetch request to retrieve into the cache circuitry the associated data in anticipation of that associated data being requested by the processing circuitry. In addition, trigger circuitry, responsive to a specified condition being detected in respect of the given prefetch request, issues a prefetch trigger signal for receipt by control circuitry associated with further cache circuitry at a higher level of the multi-level memory hierarchy, to cause a higher level prefetch procedure to be triggered by the control circuitry to retrieve the associated data from the cache circuitry into the further cache circuitry.

To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.

An IC device includes first and second terminals that receive bit and source line signals configured by a control circuit, a resistive memory device having first and second resistance levels in first and second states, and a switching device including control and body terminals and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, the current path, responsive to a first voltage level at the control terminal, has a first conductance level in a first programmed state and a second conductance level greater than the first conductance level in a second programmed state, and the control circuit sets the resistive memory device to one of the first or second resistance levels after programming the switching device to the second conductance level and while increasing the second conductance level responsive to a second voltage level at the body terminal.

This invention provides a data storage device and method for unbalanced mapping for variable readout resolution. [Solution] In a data storage device, when data is received from a host to be stored in a multi-level memory (e.g., a quad-level cell (QLC)) that is stored using a mapping that balances the bit error rate (BER) between different pages in the memory, the controller determines whether the data is intended to be read with dynamic read resolution 610, and if it determines that the data is not intended to be read with dynamic read resolution, it communicates with the memory and has the data written with a standard mapping (e.g., a 4-3-4-4 mapping) 620, and if it determines that the data is intended to be read with dynamic read resolution, it communicates with the memory and has the data written with a non-standard mapping (e.g., a 1-2-4-8 mapping) 630.

The invention provides a method and device for testing multi-level memory and performance of a DSP embedded system, and the method comprises the steps: setting an address region of a protected region and an address region of a security test region according to preset memory layout information in an initialization stage of the DSP embedded system; analyzing a test instruction set sent by the upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction; responding to the internal RAM test instruction, adopting dynamic memory mapping management, identifying and avoiding a protected area necessary for program operation, and executing a memory test algorithm only in the security test area to obtain a first test result; in response to the RAM test instruction of the external communication chip, backing up data of a to-be-tested block of the external communication chip to a temporary buffer area, and testing the to-be-tested block to obtain a second test result; and returning the first test result and the second test result to the upper computer. The security and coverage rate of the system test can be improved.

A memory structure including three-dimensional NOR memory strings and method of operation is disclosed. In some embodiments, the memory device implements partial polarization to provide a reference signal for read operation. The reference signal realizes a third logical state distinguishable from the first and second logical stages in the ferroelectric memory transistor, such as associated with the program and erase states. In another embodiment, the memory device provides a reference signal for read operation by averaging a first signal associated with a program state and a second signal associated with an erased state of the ferroelectric memory transistor. In some embodiments, the memory device implements one or more partial polarization states to provide a multi-level memory cell with more than one logical bit stored in each memory cell.

Embodiments of a memory programmer apparatus can include a first level programmer to program a first level cell portion of a multi-level memory in a first pass, a coarse programmer to coarsely program a second level cell portion of the multi-level memory in the first pass, where the second level cell portion includes more levels than the first level cell portion, and a fine programmer to finely program the second level cell portion of the multi-level memory in a second pass according to data programmed in the first level cell portion in the first pass.