60 results about "Resistance drift" patented technology

In a variable resistance memory device such as a PCRAM memory device having an array variable resistance memory cells, a process is performed to detect when the on / off resistance of each variable resistance memory cell has drifted beyond predetermined tolerance levels. When resistance drift beyond the predetermined tolerance levels is detected, at least one reset pulse is applied to the cell to return the cell to its original resistance profile. The reset pulse may be applied in the form of a “hard” write signal, a “hard” erase signal, a “soft” write signal or a “soft” erase signal as appropriate, depending on the direction of the drift and the programmed state of the cell. The “hard” write and erase signals have voltage levels which may be slightly greater in magnitude than the voltage levels of normal write and erase signals, respectively, or may have slightly longer pulse widths than those of the normal write and erase signals, or both. Similarly, the “soft” write and erase signals have voltage levels which are less than that of normal write and erase signals, or may have pulse widths which are less than that of normal write and erase signals, or both.

A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

A method and apparatus are provided for implementing enhanced data partial erase for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, and a data re-write after the partial erase to the MLC memory is performed using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase cycle includes a duration and voltage level based upon a degradation of the MLC memory cells.

A method and system are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A fast rise / fall time, pulse-shaped q-switched laser or an ultra-fast laser may be used. Beam shaping optics may be used to generate a flat-top beam profile. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The wavelength is short enough to produce desired short-wavelength benefits of small spot size, tight tolerance, high absorption and reduced or eliminated heat-affected zone (HAZ) along the trim path, but not so short so as to cause microcracking. In this way, resistance drift after the trimming process is reduced.

A method, system and scan lens for use therein are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A fast rise / fall time, pulse-shaped q-switched laser or an ultra-fast laser may be used. Beam shaping optics may be used to generate a flat-top beam profile. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The wavelength is short enough to produce desired short-wavelength benefits of small spot size, tight tolerance, high absorption and reduced or eliminated heat-affected zone (HAZ) along the trim path, but not so short so as to cause microcracking. In this way, resistance drift after the trimming process is reduced.

The invention discloses a negative temperature coefficient (NTC) material utilized at a high temperature, and a preparation method thereof. The NTC material comprises 2 to 10 wt% of La2O3, 5 to 20 wt% of ZrO2, and the rest of Ni0.6Mn1.8Al0.6O4. In the invention, oxides which comprise MnO2, NiO and Al2O3 and are traditional materials for preparation of NTC materials are utilized as base materials;a rare earth oxide La2O3 is added into the base materials to improve a stability of the base materials and reduce a ageing rate; and simultaneously, non-conducting ZrO2 is added into the base materials to improve a resistivity of the base materials and an activation energy thereby improving a constant B of the base materials. The NTC material can be utilized at a temperature more than 400 DEG C, and has a room temperature resistivity of 27900 to 64520 omega cm, a constant B of 4529 to 7895 K and a resistance drift rate of 0.6 to 2.3%.

Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.

A system, apparatus and method for providing a digital variable resistor with high resolution and efficient use of substrate area is described. In one embodiment of the invention, a digital variable resistor string comprises a serial array of resistors that is connected to a parallel array of resistors through a switching network. A compensation network is coupled in parallel to the parallel array of resistors in order to compensate for resistance drift caused by non-linear responses of components within the variable resistor. For example, the compensation network may interpolate the digital variable resistor to a preferred resistance value that is within an error margin tolerance.

A method, system and scan lens for use therein are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A fast rise / fall time, pulse-shaped q-switched laser or an ultra-fast laser may be used. Beam shaping optics may be used to generate a flat-top beam profile. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The wavelength is short enough to produce desired short-wavelength benefits of small spot size, tight tolerance, high absorption and reduced or eliminated heat-affected zone (HAZ) along the trim path, but not so short so as to cause microcracking. In this way, resistance drift after the trimming process is reduced.

The invention discloses a negative temperature coefficient two-phase composite heat-sensitive material and a method for preparing the same characterized by mixing and milling the copper acetate, ferric oxalate, manganese acetate, nickel acetate and oxalate according to the mol ratio of 0.2-0.6: 1: 3.48-3.08: 1.32: 7.2, calcining the mixture after drying, mixing the prepared powder with partial stable cubic zirconia powder according to the mol ratio of 1: 1.5-4, getting two-phase composite powder after milling and drying, getting the negative temperature coefficient material with a relative density more than 94% after sintering. The material has a stable structure, a sintering temperature between 1200 and 1250 DEG C, a higher mechanical strength than the single-phase spinel ceramic, a B value less than 2800K, a resistivity of 1000omega.cm, a resistance drift less than 3% when accelerated ageing 1000 hours at 150 DEG C, a very good NTC property between -60 DEG C to +50 DEG C, and is suitable for the negative temperature coefficient heat sensitive sensor material in the modern aerostat.

Resistance drift can be addressed by refreshing the nonvolatile memory cells and reference cells. Different approaches include performing the refresh upon a program operation, and upon satisfaction of a condition after the program operation. Refreshes are performed on a reference resistance stored in a reference cell that can be compared by a sense amplifier to the resistance stored in a memory cell. In one approach, upon programming the first memory cell, a stored refresh status is updated to indicate that the first resistance of the first memory cell and the first reference resistance of the first reference cell are to be refreshed upon satisfaction of a condition. In another approach, upon programming the first memory cell, the first reference cell is programmed.

The invention belongs to the technical field of film resistance strain gauges and provides a high-temperature film half-bridge resistance strain gauge with a temperature self-compensation function and a preparation method of the high-temperature film half-bridge resistance strain gauge. The high-temperature film half-bridge resistance strain gauge is suitable for a high-temperature environment in which the in-situ temperature cannot be directly measured or the temperature is in a dynamic fluctuation state. The half-bridge resistance strain gauge comprises a nickel-based alloy substrate, a buffering layer, an insulating layer, a functional layer and a protective layer which are sequentially stacked from bottom to top; the functional layer is composed of two graphical strain sensing units with the same structure; the two graphical strain sensing units are vertical to each other to jointly form a half-bridge structure; apparent strain errors caused by temperature fluctuation (change) and drifting strain errors caused by resistance drifting of a sensing layer in a testing process can be effectively self-compensated by connecting the film half-bridge resistance strain gauge into a Wheatstone bridge circuit, so that the testing precision and accuracy of the strain gauge are improved; in addition, the high-temperature film half-bridge resistance strain gauge with the temperature self-compensation function is simple in preparation process, low in preparation cost and beneficial to industrial production.

The invention provides a method of forming a semiconductor structure. The method comprises the steps of providing a semiconductor substrate with a transistor forming on the surface thereof; forming a first interlayer dielectric layer covering the semiconductor substrate and the transistor; forming a plug in the first interlayer dielectric layer; forming a sacrificial layer covering the first interlayer dielectric layer and the plug; etching the sacrificial layer, and forming a first trench in the sacrificial layer; forming a second interlayer dielectric layer filled in the first trench; removing the remaining sacrificial layer, and forming a second trench which exposes the surface of the plug; and forming a wiring layer filled in the second trench, the bottom of the wiring layer being electrically connected with the plug and the top of the wiring layer having a size smaller or equal to that of the bottom. The effective contact area between the wiring layer and the plug is increased, the resistance drift phenomenon of a metal interconnect structure is improved, damage to the interlayer dielectric layers from the etching process is avoided, the parasitic capacitance is reduced, and the device electrical performance is optimized.

The invention relates to a thermistor based on a high-entropy oxide, and a preparation method thereof. The thermistor is composed of oxides of five elements of cobalt, manganese, nickel, iron and zinc, a single spinel phase high-entropy oxide powder material is prepared through a high-temperature solid-phase chemical reaction, and then the powder is subjected to pre-pressing forming, isostatic pressing, sintering, slicing, heat treatment, electrode manufacturing, scribing and packaging to form the NTC thermistor. The resistance value (25 DEG C) of the NTC thermistor is 6.5-12 K omega.cm, the material constant B value is 3500-3800 K, the material constant B value and the resistance value are high in consistency and good in interchangeability, after the NTC thermistor is aged for 1000 h at the temperature of 125 DEG C, the resistance drift rate is smaller than 0.05%, the stability of the NTC thermistor can be greatly improved, and the thermistor can be applied to seawater temperature measurement and control for a long time.

The invention relates to a high-stability phase change memory cell and a preparation method thereof. The high-stability phase change memory cell comprises a substrate layer, an electrode material, a dielectric isolation material, a phase change material region and a transition layer material between the phase change material and the dielectric isolation material. The phase change memory unit formed in the invention can inhibit growth of phase change material grains, improve the thermal stability of a phase change memory, effectively inhibit diffusion and volatilization of each element in the phase change material, reduce the resistance drift coefficient and reduce the power consumption of a device.

The invention relates to a lithium ion power battery cap and a welding method thereof, which belong to the technical field of lithium ion batteries. The lithium ion power battery cap comprises a top cover, an anti-explosion membrane, a gasket and a polar plate, wherein the top cover, the anti-explosion membrane, the gasket and the polar plate are sequentially combined. The invention is characterized in that a groove is formed on the top cover or on the anti-explosion membrane, brazing materials of the top cover and the anti-explosion membrane are arranged in the groove, and the top cover and the anti-explosion membrane are in a connection structure in a brazing mode. The welding method of the lithium ion power battery cap has the following steps: sequentially assembling the top cover, the anti-explosion membrane, the gasket and the polar plate; and additionally adding a sealing ring. The invention is characterized in that when the top cover and the anti-explosion membrane are processed, firstly, the groove is manufactured on the top cover and the anti-explosion membrane, the brazing materials are placed in the groove of the top cover or the anti-explosion membrane, and the top cover and the anti-explosion membrane are welded into an integral structure through brazing. The invention has the advantages of novel technology, convenient processing, firm contact, small contact resistance, no resistance drift, high safety grade, long service life of the battery, wide application range and the like.

Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

The invention discloses a phase change storage unit amorphous state and crystalline state cutting method based on digital bidirectional pulses. Through application of a RESET pulse and a SET pulse with different polarities on two electrodes of a phase change storage unit, the volume of the non-crystallizing region in the phase change storage unit changes under action of the pulse modulation effect, and the shape is similar to a cylinder. Through adjustment of amplitudes, widths, intervals and polarities of two electric pulses, the resistance and the pulse modulation mode of the phase change storage unit are in a linear relation. The RESET pulse and the SET pulse with different polarities are employed to apply on two electrodes of the phase change storage unit respectively or at the same time to achieve a cylindrical non-crystallizing region, thus the non-crystallizing resistance and the pulse modulation mode are in a linear relation, and accurate control of the non-crystallizing resistance is achieved. The generated temperature gradient extends to the temperature of the non-crystallizing region and is less than the crystallization temperature, annealing processing of the non-crystallizing region can be achieved, and the problems of resistance drift and random fluctuation are reduced effectively.

The invention relates to a high-stability NTC (negative temperature coefficient) thermistor suitable for a medium-temperature zone and a preparation method of the thermistor. The thermistor comprises oxides of four metallic elements including Co, Mn, Fe and Zn, the oxides are subjected to preparation with a coprecipitation method, forming, sintering, slicing, electrodefiring, cutting and packaging, then the high-stability NTC thermistor suitable for the medium-temperature zone is obtained, the standard resistance of the thermistorat the temperature of 25 DEG C ranges from 50-180 kilohms, and the material constant ranges from 3,990 K to 4.270 K. The thermistor device has the standard resistance and material constantsuitable for the medium-temperature zone, can be applied to temperature measurement, control, compensation and the like of equipment such as an automobile, an air conditioner, a microwave oven and the like and has very good stability, consistency and interchangeability, the resistance drift rate is smaller than 0.1% after the thermistor is aged for 1,000 h at the temperature of 150 DEG C, the stability of the conventional NTC thermistor can be improved greatly, the measurement accuracy of the NTC thermistor can be improved, and the service life of the NTC thermistor can be prolonged.

The invention relates to a preparation method of a ternary thermistor material with a negative temperature coefficient. According to the method, the ternary thermistor material with the negative temperature coefficient and the high stability is prepared from oxides of three metal elements including Co, Mn and Fe through the processes of wet ball-milling preparing, presintering, forming, sintering and the like. The ternary thermistor material which has the negative temperature coefficient and is obtained through the method has the performance parameters that the standard resistance (25-DEG C resistance) is 1,002-1,797 ohm, the material constant is 3,671 k to 3,994 K, and after the material is aged for 500 h at 150 DEG C, the resistance drift rate is 0.16%-0.19%. The ternary thermistor material has the good stability, consistency and interchangeability and can be widely applied to occasions such as temperature measurement, temperature compensation and surge current inhibition.

The invention relates to the technical field of thermistors, and particularly discloses a negative temperature coefficient thermistor chip and a preparation method thereof. The negative temperature coefficient thermistor chip is prepared from the following raw materials in parts by weight: 771.24-771.34 parts of Mn3O4; 215.82-215. 92 parts of NiO; 12.79-12.89 parts of Al2O3; the preparation methodcomprises the following steps: S1, weighing materials; s2, mixing; s3, calcining; s4, carrying out micro-crushing; s5, carrying out spray granulation; s6, tabletting and forming; s7, pre-sintering; s8, sintering; s9, polishing; s10, brushing silver. The negative temperature coefficient thermistor chip has the advantages that the consistency of the resistance value and the B value is good, the resistance drift rate is smaller than 1% after the thermistor chip is used in a high-temperature environment for a long time, the service life is long, and the stability is high; in addition, the preparation method has the advantages of being high in particle dispersion degree, not prone to agglomeration and high in chip breaking strength.

Resistive memory device and programming method of the same. In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and / or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

The invention discloses a diagnosis method for diagnosing the sampling resistance drift, a diagnosis system and a digital control system. The diagnosis method comprises the following steps of (1) constructing sampling circuits Uhx and Ux, and acquiring the sampling circuits; (2) carrying out threshold comparison on the Uhx and the Ux to obtain compared output signals; (3) based on the output signals, acquiring the diagnosis result of the sampling resistance drift. The diagnosis system comprises a sampling module and a diagnosis module. The sampling module is used for acquiring a Uhx signal and a Ux, and transmitting the Uhx signal and the Ux to the diagnosis module respectively. The diagnosis module is used for comparing the Uhx signal with the Ux, and obtaining an output signal according to the comparison result. According to the invention, the sampling resistance drift faults of analog input can be diagnosed. Therefore, the predictability of signal input and the reliability of a verification and acquisition channel circuit are guaranteed. The method is novel, unique, practical and applicable.

A system, apparatus and method for providing a digital variable resistor with high resolution and efficient use of substrate area is described. In one embodiment of the invention, a digital variable resistor string comprises a serial array of resistors that is connected to a parallel array of resistors through a switching network. A compensation network is coupled in parallel to the parallel array of resistors in order to compensate for resistance drift caused by non-linear responses of components within the variable resistor. For example, the compensation network may interpolate the digital variable resistor to a preferred resistance value that is within an error margin tolerance.

The invention discloses a high-reliability phase change material, which is a superlattice-like phase change material layer formed by circularly and alternately overlapping first phase change materiallayers and second phase change material layers, wherein a superlattice-like interface is formed between the first phase change material layer and the second phase change material layer, the first phase change material layer is Sb2Te3 as an induction layer, the second phase change material layer is Ge15Te85, and at least three layers of the first phase change material layers and the second phase change material layers are circularly and alternately overlapped. The amorphous Sb2Te3 layer requires low energy for crystallization, stable lattice orientation is easy to form, the selected Sb2Te3 layer can thus be used as the induction layer, the amorphous Ge15Te85 layer has a higher phase change speed in the phase change process, and rapid crystallization of the whole phase change material can bepromoted; in addition, in the energy band structure of the selected Ge15Te85 layer, the defect state is mainly located in the local state of the band tail instead of the defect energy level near theFermi level in the band gap, resistance drift caused by relaxation of the defect energy level is avoided, and therefore the phase change speed is higher in the phase change process.

Aspects of the present application allow for measurement of a calibrated resistance for a resistive film in a sensing element, such that effects from contact resistance and background resistance drifts due to factors such as temperature, strain or aging can be reduced or eliminated. In some embodiments, by taking a plurality of two-terminal resistance measurements between various pairs of electrodes on a resistive film, a contact-resistance-independent resistance of a reference portion of the resistive film can be determined. Further, a contact-resistance-independent resistance of a sensing portion of the resistive film can be determined based on a plurality of two-terminal resistance measurements between pairs of electrodes. The resistance of the reference portion can be removed from the measured resistance of the sensing portion, such that variations in the reference portion resistance that are not caused by a sensed environmental condition may be compensated.

The invention discloses an NTC thermistor chip material, a chip, a resistor and a sensor, and making methods thereof, and belongs to the field of thermistors. The material comprises, by weight, 1000-1200 parts of Mn3O4, 95-105 parts of Co2O3, 190-210 parts of NiO and 590-610 parts of Fe2O3. The NTC thermistor made by using the NTC thermistor chip material has the advantages of difficult breakdown by current, difficult resistance drift and long service life.