15 results about "Nibble" patented technology

The invention discloses a work order demand identification method and platform fused with big data analysis, and relates to the technical field of work order data processing.Accurate work order demand identification under multi-source data fusion is achieved through multi-module collaboration.The method comprises the steps that firstly, a multi-source candidate identifier original character string is obtained and converted into a half-byte sequence; counting the half-byte length, judging a tail filling type label according to the half-byte length, and filtering a non-protocol type pseudo string; processing the half-byte sequence according to a tail filling type label to obtain a pure digital half-byte sequence, intercepting a 14-bit numerical sequence, calculating to generate a 15-bit standard IMEI (International Mobile Equipment Identity), reversely generating a half-byte verification sequence, and comparing to generate a reversibility verification mark; intercepting a model allocation code TAC based on the reversibility verification mark, and querying a model knowledge base in combination with a tail filling type label to obtain model information; and combining 15-bit specification IMEI, TAC and model information into a work order demand identification triple, and writing the triple into a work order structured field to complete package of work order demand identification data.

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

Processor, comprising: decoding circuitry to decode a tile dot product instruction (2102) having fields for an opcode, a destination identifier to identify an M-by-N destination matrix (2118), a first source identifier to identify a first M-by-K source matrix (2104), and a second source identifier to identify a second K-by-N source matrix (2106), each of the matrices to include double-word elements; and an execution circuit (2108) for executing the decoded instruction (2102) by performing a process K times for each element (M,N) of the identified target matrix (2118), the process comprising: Generating eight products by multiplying each nibble of a double-word element (M,K) of the identified first source matrix (2104) by a corresponding nibble of a double-word element (K,N) of the identified second source matrix (2106); Accumulating the eight products with preceding contents of the double word element (M,N) of the identified target matrix (2118) to produce a sum; Saturating the sum to produce a saturated sum if the sum exceeds the range of a double-word integer; and Storing the saturated sum at the double word element (M,N) of the identified target matrix (2118).

Processing unit (3000) comprising: a circuit arrangement for performing operations according to an instruction (2102), the instruction (2102) specifying a first matrix with M rows by K columns of 32-bit elements each having eight 4-bit data elements, a second matrix with K rows by N columns of 32-bit elements each having eight 4-bit data elements, and a third matrix with M rows by N columns, the instruction having a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned, the operations including: for each row m of the M rows of the first matrix and for each column n of the N columns of the second matrix: for each of the K 32-bit elements of row m of the first matrix: Multiplying eight 4-bit data elements of the 32-bit element of row m of the first matrix by corresponding ones of eight 4-bit data elements of a corresponding 32-bit element of column n of the second matrix to produce eight products; and Storing a 32-bit result data item in a row m of the M rows and a column n of the N columns of the third matrix, the 32-bit result data item being based on accumulation of the eight products generated for each of the K 32-bit elements of row m of the first matrix with a 32-bit data item of row m of the first matrix and column n of the second matrix.

Device comprising: an interface logic for differential signaling on a plurality of paths, where the interface logic is configured to transmit a plurality of flits, wherein the plurality of flits has a plurality of nibbles, and wherein a first of the plurality of flits is transmitted with a clean flit boundary such that each of the plurality of paths is used to transmit initial nibbles of the first flit in a first unit interval (UI), and wherein initial nibbles of a second flit of the plurality of flits, together with final nibbles of the first flit, are transmitted on the plurality of paths during a subsequent UI.

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

The present disclosure relates to systems and methods for computing a number product of half-words in two block operands. In one example, an apparatus comprises a plurality of memory controllers, a level two (L2) cache memory, and a processor having a plurality of cores, a core including circuitry to perform an operation corresponding to an instruction, the operation including multiplying eight 4-bit data elements of a 32-bit element of a row m of a first matrix with a respective data element of eight 4-bit data elements of a respective 32-bit element of a column n of a second matrix to generate eight products, and storing a 32-bit result data element at row m in an M row and column n in an N column of a third matrix, the 32-bit result data element to be based on an accumulation of the eight products generated for each of K 32-bit elements of row m of the first matrix with the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

The application relates to a mixed differential byte-level distinguisher search method, and belongs to the technical field of network information security block cipher design and analysis. First, a mixed differential mode coding variable is introduced for each input byte and each output byte of each state matrix in a block cipher using (semi-) byte-level permutation as a linear diffusion layer, and a probability variable is introduced for the XOR operation of each layer of the linear diffusion layer. For the S-box operation of the nonlinear layer in the encryption process, a new coding variable does not need to be generated. The input (semi-) byte mixed differential coding variable, the output (semi-) byte mixed differential coding variable and the probability variable of each XOR operation of each round of the linear diffusion layer are given the restrictions, a mixed integer linear programming problem is established by taking the sum of the probability variables of all the XOR operations of the linear diffusion layer in the block cipher as the target for minimization, and finally a high-probability mixed differential distinguisher is obtained by solving the mixed integer linear programming problem.

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

The present application discloses systems and methods for implementing a 16-bit floating-point matrix dot product instruction. The disclosed embodiments relate to computing the dot product of half bytes in tile operands. In one example, a processor includes: a decoding circuit for decoding a tile dot product instruction having a field for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each matrix containing doubleword elements; and an execution circuit for executing the decoded instruction to perform a K-fold process on each element (m, n) of the specified destination matrix, thereby generating eight products by multiplying each half byte of the doubleword elements (M, K) of the specified first source matrix by the corresponding half byte of the doubleword elements (K, N) of the specified second source matrix, and accumulating and saturating the eight products with the previous contents of the doubleword elements.

The present invention discloses a method for searching for zero-correlation linear discriminators in an SPN-structured block cipher algorithm designed for half-byte / byte blocks, combining linear mask set propagation and CP technology. This method integrates the advantages of existing methods, utilizing the concept of set propagation and combining CP modeling technology to achieve a complete characterization of the LAT table of an S-box using a linear mask propagated with probability 1. This method combines the advantages of existing methods while overcoming their shortcomings. Furthermore, it can fully consider the LAT table to search for conflicts between zero and non-zero sets, and between non-zero and non-zero sets. The method uses model solvability as a criterion, and can be considered together with the extension of the discriminator to form an integrated model.

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

This invention discloses a work order requirement identification method and system integrating big data analysis, relating to the field of work order data processing technology. It achieves accurate work order requirement identification through multi-module collaboration and multi-source data fusion. First, it obtains the original strings of multi-source candidate identifiers and converts them into half-byte sequences. The half-byte length is calculated, and the tail padding type label is determined based on the half-byte length, while filtering out non-protocol pseudo-strings. The half-byte sequence is processed according to the tail padding type label to obtain a pure numeric half-byte sequence. A 14-bit numerical sequence is extracted, and a 15-bit standard IMEI is calculated. Then, a half-byte verification sequence is generated in reverse, and a reversibility verification flag is generated after comparison. Based on the reversibility verification flag, the device allocation code (TAC) is extracted, and the device information is obtained by querying the device knowledge base in conjunction with the tail padding type label. The 15-bit standard IMEI, TAC, and device information are combined into a work order requirement identification triplet and written into the work order structured field, completing the work order requirement identification data encapsulation.

The invention discloses an SPN structure zero-correlation linear discriminator searching method combining linear mask set propagation and CP technology. The method is used for searching a zero-correlation linear discriminator of an SPN structure block cipher algorithm oriented to half-byte / byte design. The method integrates the advantages of the existing method, realizes the complete description of the LAT table of the S box under the condition that the linear mask is propagated with the probability of 1 by utilizing the thought of set propagation and combining the CP modeling technology, has the advantages of the existing method, makes up for the defects of the existing method, and has the advantages of the existing method. And meanwhile, the contradiction between zero and non-zero and between non-zero and non-zero sets can be searched under the condition of completely considering an LAT table, and model solvability is taken as a judgment condition and can form an integral model with expansion of a differentiator to be considered.

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.