13 results about "32-bit" patented technology

The invention relates to a hardware routing table look-up method based on segmented unified storage. The method comprises the following steps: firstly, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address fields according to 32 bits, allocating a unique forward and backward segment identifier for each field, constructing table entries containing the segment identifiers, 32-bit segment data and a next hop, and uniformly storing the table entries into the same TCAM. During table lookup, segmenting an address to be looked up according to the same rule, querying the TCAM from a first segment by taking segment data as a key, and recording a backward segment identifier and a next hop after hit; and if the backward segment identifier is invalid, directly returning to the corresponding next hop, and if the backward segment identifier is valid, continuing query by taking the identifier and the next segment of data as a joint key. And when the table item is not hit or the identification verification fails, selecting the table item with the longest prefix and the valid next hop in the matched section, and returning to the next hop. According to the invention, IPv4 / IPv6 routing table entries can be uniformly stored, the TCAM space utilization rate is improved, and meanwhile, the hardware table look-up efficiency is guaranteed.

The application discloses a CXL module, an error correction method and a medium, and relates to the technical field of data access, wherein the CXL module comprises a controller and a memory bank connected with the controller, and a plurality of memory particles are arranged on the memory bank; wherein the controller is configured to perform ECC encoding on 512-bit data to be written, generate a check code smaller than or equal to 32 bits, write the 512-bit data to be written and the check code into the memory bank through one burst, read out the 512-bit data to be written and the check code from the memory bank through one burst, and perform error correction processing on the 512-bit data to be written based on the check code; wherein the check code can correct errors of more than 2 bits. The CXL module has higher error correction capability under the premise of paying a smaller capacity cost.

Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and / or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

The invention discloses a segment identifier compression method oriented to a satellite network, which aims at the problem of high SRH head overhead caused by a relatively long path, and is characterized in that a 128-bit SID is compressed into a 32-bit C-SID in combination with satellite network topology position information, and the head length is reduced while segment routing semantics and programmable capability are maintained; one SID or 1-4 C-SIDs are loaded in a 128-bit segment identifier packaging unit carrier of the SRH, the C-SID, the SID and a filling unit are distinguished through CSI and C-Flag, and a segment list is traversed in combination with a segment index SL, so that unified identification and processing of the SID and the C-SID are realized; after the current C-SID takes effect, decoding the current C-SID to generate an IPv6 destination address for forwarding; according to the method, the SRv6 control plane protocol and the SRH fixed head format do not need to be modified, the SRH head overhead in the satellite network can be reduced, and the method is suitable for SRv6 service bearing in the satellite network.

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

The application relates to a hardware routing lookup table method based on segmented unified storage, which comprises the following steps: first, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address segments according to 32 bits, allocating unique forward and backward segment identifiers to each segment, constructing a table item containing a segment identifier, 32-bit segment data and a next hop, and uniformly storing the table item into a same TCAM. When performing lookup, the address to be looked up is segmented according to the same rule, the TCAM is queried with the segment data as the key from the first segment, the backward segment identifier and the next hop are recorded after a hit, if the backward segment identifier is invalid, the corresponding next hop is directly returned, if the backward segment identifier is valid, the identifier and the next segment data are taken as a joint key to continue the query. When a miss or identifier verification fails, a table item with the longest prefix and the valid next hop in the matched segment is selected and the next hop is returned. The application can uniformly store IPv4 / IPv6 routing table items, improve the TCAM space utilization rate, and guarantee the hardware lookup efficiency.

The application provides an optimization method of a low-bit arbitrary-size independent convolution simd, comprising the following steps: S1, processing of convolution kernel data, the data storage mode adopts a convolution calculation mode, which can greatly reduce the loading time, and the data needs to be converted; converting the data; S2, design of convolution calculation and accumulation: since the accumulation sum cannot exceed 16 bits after multiplication and adjacent addition, the data must be processed; first, using the 16-bit accumulation sum to calculate, calculating 14 times each time, since the instruction is multiplied first and then adjacent addition in the calculation, the actual instruction accumulation number is 7 times; then, converting the data in the register into 32 bits and accumulating into a 32-bit register. The application can realize a speed increase of several times, and can increase by about 35 times relative to a C program. The 16-bit accumulation can be used, and the speed can be improved.

The invention discloses a multiply-accumulate operation circuit based on an RISC-V processor and an instruction set expansion method, and the circuit comprises a special multiply-accumulate register pair which is used for storing an accumulated value; the multiplier is used for calculating a product of operands; the adder is used for adding the product and the current accumulated value; the splicing shifter is used for splicing and shifting the final accumulated value; and the CSR read-write interface is used for transmitting data with the general register group. The method is applied to the circuit. According to the circuit and the instruction set expansion method, the special register pair is introduced to store the full-precision intermediate result, so that the precision loss in the operation process is remarkably reduced; by means of programmable splicing shifting operation, multiply-accumulate operation of any Q-format fixed-point number within 32 bits is supported, and high flexibility and high efficiency are achieved; and meanwhile, the original multiplier of the processor is multiplexed, so that the unification of high performance and low hardware overhead is realized.

The application relates to a key leakage detection method of an SM3 hash algorithm, which comprises the following steps: firstly, generating a to-be-processed message at random, taking the to-be-processed message as the input of the SM3 algorithm, introducing a random 4-byte fault by adopting a 4-byte random fault model, obtaining an error output hash value, calculating the corresponding value path of 32 bits of the last-but-one round 4-byte register by an exhaustive method, obtaining an intermediate meeting array, obtaining the intermediate state value of the last-but-one round 4-byte register by extending the message group by the exhaustive method, matching the intermediate state value with the intermediate meeting array, and using a statistical method to obtain the partial value of the correct message group, repeatedly introducing the fault and analyzing the process to obtain the correct message group, and finally deducing the correct to-be-processed message. The method provided by the application is easy to implement, fast and high in accuracy, and can provide an important analysis basis for the security research of the SM3 hash algorithm.

A spaceborne software EDAC fault-tolerance method for COTS platforms is proposed. Based on the spaceborne EDAC hardware implementation, an EDAC verification module and checksum are designed. The checksum uses Hamming code, with each executable codeword being 32 bits long and the checksum being 7 bits, achieving a one-to-two verification function. Through executable code segment instrumentation, EDAC verification module call statements are inserted before the call statements of each module in the original executable code, enabling EDAC verification to be completed before the called module executes. The checksum of each instrumented executable code is calculated and stored as part of the program area. An improved approach of "running code priority verification" is adopted, combining pre-scheduling verification and idle-period verification to perform EDAC verification on the executable code. Simultaneously, a copy of the EDAC algorithm is stored in the program storage area, enabling mutual verification between the two EDAC algorithm modules to ensure the correctness of the EDAC module itself.

The invention discloses a novel coding representation scheme of three-dimensional space sparse octree node voxels. The invention belongs to the research field of three-dimensional space voxel coding in a computer system, and mainly solves the problems that traditional coding is high in memory occupation and slow in node positioning and searching. According to the scheme, 32-bit integers are used for representing spatial voxels. Comprising the steps that floating bit coding is used for representing the size of sparse octree node voxels in a three-dimensional space scene, and coding is used for representing coordinates of voxel nodes in a three-dimensional space. The integer code is formed by 32 bits according to the claim 1. The method is characterized in that 1, integer coding formed by 32 bits is adopted; the method is characterized in that the lowest bit is fixed to be 1, and the subsequent bits represent the coding of the multi-dimensional space coordinates. And 2, based on 1, representing derivative codes of sparse octree voxel nodes.

This invention provides a method for quickly calculating the reciprocal of a positive number based on SIMD instructions, comprising: S1. Loading data, which is loaded in multiples of 32 bits, with a maximum of 512 bits of data per register; single-precision floating-point numbers are 32 bits, and a register can load 16 floating-point numbers, so one SIMD instruction can load or calculate 16 floating-point numbers simultaneously. Let Register1 = Ingenic_simd512_load((float)data); Ingenic_simd512_load is the SIMD instruction for loading data; (float)data is the 16 input 32-bit single-precision floating-point numbers; Register1 is register 1, and the input data is stored in Register1. S2. Use SIMD instructions to calculate the reciprocal of the square root from the data in Register1, and store the result in Register2; S3. Square the reciprocal of the square root from step S2 to obtain the reciprocal. Let Register3 = Ingenic_simd512_float_mul(Register2, Register2); Ingenic_simd512_float_mul is a SIMD instruction for floating-point multiplication. Multiply the data in Register2 with the data in Register2, that is, square the data in Register2, and store the result in Register3; S4. Save the calculation result from the register to memory.

The embodiment of the invention provides a rate matching method and a communication device, and the method comprises the steps: carrying out the coding of a to-be-coded sequence based on a basic sequence corresponding to small packet coding, obtaining a first code word sequence with the length of 32 bits, carrying out the interweaving of the first code word sequence, obtaining a second code word sequence, and finally, carrying out the coding of the to-be-coded sequence. And punching the second code word sequence from back to front based on a numerical value E to obtain a third code word sequence, the numerical value E indicating the number of bits after rate matching of the second code word sequence, and E being a positive integer less than 32. According to the method, the code distance characteristic of the first code word sequence after punching can be improved, so that the Hamming distance between different legal code words is as large as possible, and the decoding performance is improved.