47 results about "32-bit" patented technology

The invention relates to a hardware routing table look-up method based on segmented unified storage. The method comprises the following steps: firstly, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address fields according to 32 bits, allocating a unique forward and backward segment identifier for each field, constructing table entries containing the segment identifiers, 32-bit segment data and a next hop, and uniformly storing the table entries into the same TCAM. During table lookup, segmenting an address to be looked up according to the same rule, querying the TCAM from a first segment by taking segment data as a key, and recording a backward segment identifier and a next hop after hit; and if the backward segment identifier is invalid, directly returning to the corresponding next hop, and if the backward segment identifier is valid, continuing query by taking the identifier and the next segment of data as a joint key. And when the table item is not hit or the identification verification fails, selecting the table item with the longest prefix and the valid next hop in the matched section, and returning to the next hop. According to the invention, IPv4 / IPv6 routing table entries can be uniformly stored, the TCAM space utilization rate is improved, and meanwhile, the hardware table look-up efficiency is guaranteed.

The application discloses a CXL module, an error correction method and a medium, and relates to the technical field of data access, wherein the CXL module comprises a controller and a memory bank connected with the controller, and a plurality of memory particles are arranged on the memory bank; wherein the controller is configured to perform ECC encoding on 512-bit data to be written, generate a check code smaller than or equal to 32 bits, write the 512-bit data to be written and the check code into the memory bank through one burst, read out the 512-bit data to be written and the check code from the memory bank through one burst, and perform error correction processing on the 512-bit data to be written based on the check code; wherein the check code can correct errors of more than 2 bits. The CXL module has higher error correction capability under the premise of paying a smaller capacity cost.

Provided are a video transmission method and device, relating to the technical field of media. According to the method, the consumed bandwidth during video data transmission can be reduced, so that the bandwidth utilization is improved. The method is applicable to a source device or a chip in a source device, and the method comprises: encapsulating video data into at least one active video packet (AVP), pixels being continuously arranged one after another in each row of the video data, and each AVP being encapsulated according to 32 bits in a row; and transmitting the at least one AVP to a sink device.

Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and / or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

The invention discloses a GFP frame searching method based on a 10G Ethernet system. The GFP frame searching method comprises the following steps of 1, splicing and recombining data into four data branches; 2, frame header descrambling: the bit width of the spliced and recombined data under one beat is still 32 bits, and the data of each beat and 32'hB6AB31E0 are subjected to XOR operation to perform descrambling operation; step 3, performing CRC-16 calculation on the 32-bit data of each rhythm after descrambling to search the position of a core frame header, and enabling the calculation result of the CRC-16 and the data subjected to the CRC-16 calculation to be in the same rhythm, namely, each rhythm has a CRC-16 calculation result corresponding to the data of the current rhythm; according to the invention, descrambling, CRC calculation and single-bit error correction processes are removed from a feedback loop for independent calculation, a bit error indication signal is generated, and the process is matched with PLICnt to judge whether a core frame header is matched or not for frame search, so that the logic level of a critical path is effectively reduced, the logic level is controlled within 5 levels, and time sequence optimization is completed.

Provided are a video transmission method and device, relating to the technical field of media. According to the method, the consumed bandwidth during video data transmission can be reduced, so that the bandwidth utilization is improved. The method is applicable to a source device or a chip in a source device, and the method comprises: encapsulating video data into at least one active video packet (AVP), pixels being continuously arranged one after another in each row of the video data, and each AVP being encapsulated according to 32 bits in a row; and transmitting the at least one AVP to a sink device.

An interleaving method and a communication apparatus. The method comprises: on the basis of a PBCH payload interleaver, interleaving a PBCH payload, so as to obtain a first interleaved sequence, wherein the PBCH payload interleaver comprises A positions and values corresponding to the A positions, the A positions correspond to A bits of the PBCH payload on a one-to-one basis, and the value G(j) corresponding to a jth position among the A positions indicates that the bit among the A bits that corresponds to the jth position is interleaved to the G(j) position of the A bits; acquiring a second interleaved sequence having a length of K, wherein the second interleaved sequence is obtained by cascading 24-bit cyclic redundancy check (CRC) to the first interleaved sequence, and K=A+24; and on the basis of a distributed cyclic redundancy check (DCRC) interleaver having the length of K, interleaving the second interleaved sequence, so as to obtain a third interleaved sequence. The method can support PBCH payload interleaving of a PBCH payload with more than 32 bits.

An interleaving method and a communication device, in the method, an A-bit PBCH payload is interleaved based on a PBCH payload interleaver to obtain an interleaving sequence, A is greater than 32, the PBCH payload interleaver comprises A positions and values of the A positions, the A positions are in one-to-one correspondence with the A-bit PBCH payload, the value of the position, corresponding to one bit indicated by a half frame in the PBCH payload, in the A positions is 0, and the value of the position, corresponding to one bit indicated by a half frame in the PBCH payload, in the A positions is 0; the values of the positions corresponding to C bits related to time or frequency indication in the PBCH payload are 1 to C, and the values of the positions corresponding to Nsfn SFN bits in the PBCH payload are serial numbers of Nsfn positions of which the reliability is located at the last Nsfn bit from the (C + 1) th position to the (A-1) th position in the PBCH payload. According to the method, payload interleaving of PBCH payloads exceeding 32 bits can be supported, and the effects of protecting key bits and improving PBCH decoding performance can be achieved.

The invention discloses a segment identifier compression method oriented to a satellite network, which aims at the problem of high SRH head overhead caused by a relatively long path, and is characterized in that a 128-bit SID is compressed into a 32-bit C-SID in combination with satellite network topology position information, and the head length is reduced while segment routing semantics and programmable capability are maintained; one SID or 1-4 C-SIDs are loaded in a 128-bit segment identifier packaging unit carrier of the SRH, the C-SID, the SID and a filling unit are distinguished through CSI and C-Flag, and a segment list is traversed in combination with a segment index SL, so that unified identification and processing of the SID and the C-SID are realized; after the current C-SID takes effect, decoding the current C-SID to generate an IPv6 destination address for forwarding; according to the method, the SRv6 control plane protocol and the SRH fixed head format do not need to be modified, the SRH head overhead in the satellite network can be reduced, and the method is suitable for SRv6 service bearing in the satellite network.

An interleaving method and a communication device, in the method, a PBCH payload is interleaved based on a PBCH payload interleaver to obtain a first interleaving sequence, the PBCH payload interleaver comprises A positions and values corresponding to the A positions, the A positions are in one-to-one correspondence with A bits of the PBCH payload, and the A positions are in one-to-one correspondence with A bits of the PBCH payload; the value G (j) corresponding to the j-th position in the A positions indicates that the bit corresponding to the j-th position in the A bits is interleaved to the G (j)-th position of the A bits; a second interleaving sequence with the length of K is obtained, the second interleaving sequence is obtained by cascading the first interleaving sequence with 24-bit cyclic redundancy check (CRC), and K = A + 24; and interleaving the second interleaved sequence based on a distributed cyclic redundancy check (DCRC) interleaver with the length of K to obtain a third interleaved sequence. According to the method, PBCH payload interleaving of PBCH payloads exceeding 32 bits can be supported.

The application discloses a data recycling method and device in the computer technical field, and a readable storage medium. The application is suitable for a 32T and above large-capacity SSD. A single LMA provided by the application is greater than 32 bits, and more physical addresses can be mapped. In addition, the application also judges the validity of the LMA information set in the P2L table, and can improve the validity and efficiency of data recycling. In the case that the LMA information set does not exceed the LMA range of the solid state disk, the target data is not subjected to a Trim operation, the target PMA information set corresponding to the LMA information set found in the L2P table is consistent with the storage position of the target data in the target super block, the target data is read from the target super block according to the target PMA information set, and the target data is stored into a target super block, so as to complete a garbage recycling operation.

The present invention relates to a method and device for compressing user portrait tag data, belonging to the technical field of data compression. The method includes: obtaining at least one field to be queried from a database according to user portrait tags, obtaining a corresponding plurality of user IDs as user IDs to be stored according to the fields to be queried, the user ID is of int type, and each user ID is represented by 32 bit positions. Splitting each user ID in the user IDs to be stored into a high 8-bit, a middle-high 8-bit, and a low 16-bit, and compressing and storing the user IDs to be stored according to the high 8-bit, the middle-high 8-bit, and the low 16-bit; Compressing and storing a plurality of user IDs corresponding to user portrait tags based on the high 8-bit, the middle-high 8-bit, and the low 16-bit can effectively reduce the storage space for storing user IDs and save storage costs.

The application discloses a register allocation method, device, equipment, medium and product, and the method comprises the steps of obtaining an operation instruction to be allocated, determining an operation width identifier of the operation instruction to be allocated; determining a register allocation mode of the operation instruction to be allocated according to the operation width identifier and a register sharing condition, wherein the register allocation mode comprises a shared register allocation mode and a separate allocation mode; performing physical register allocation on the operation instruction to be allocated based on the register allocation mode, and generating an enhanced renaming table, and each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register. By splitting a single 64-bit physical register into two independent 32-bit sub-registers and realizing shared use, the shared or separate allocation mode is dynamically selected based on the instruction width, space waste caused by using only 32 bits but occupying a complete 64-bit register can be avoided, dynamic power consumption is reduced, and the register utilization rate is significantly improved.

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

The application relates to a hardware routing lookup table method based on segmented unified storage, which comprises the following steps: first, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address segments according to 32 bits, allocating unique forward and backward segment identifiers to each segment, constructing a table item containing a segment identifier, 32-bit segment data and a next hop, and uniformly storing the table item into a same TCAM. When performing lookup, the address to be looked up is segmented according to the same rule, the TCAM is queried with the segment data as the key from the first segment, the backward segment identifier and the next hop are recorded after a hit, if the backward segment identifier is invalid, the corresponding next hop is directly returned, if the backward segment identifier is valid, the identifier and the next segment data are taken as a joint key to continue the query. When a miss or identifier verification fails, a table item with the longest prefix and the valid next hop in the matched segment is selected and the next hop is returned. The application can uniformly store IPv4 / IPv6 routing table items, improve the TCAM space utilization rate, and guarantee the hardware lookup efficiency.

A processor or other device, such as a programmable and / or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

1. The name of this design product: Barrier-type signal receiving module (JP series-RJ45, 32 bits). 2. Purpose of this design product: used to receive signals. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The present invention discloses a SoC system and a real-time encryption and decryption method based on the PRINCE algorithm. The SoC system includes a kernel, a bus, a peripheral bus module and an external memory. The peripheral bus module performs real-time encryption and decryption on important programs and data in the process of the kernel executing user software; the external memory is a peripheral of the kernel, which is accessed through the peripheral bus and is used to store important programs and data that have been encrypted. The SoC system and the real-time encryption and decryption method provided by the present invention apply the 64-bit PRINCE algorithm to an embedded system with a bus width of 32 bits, realize real-time data encryption and decryption for the external memory, the encryption and decryption process does not require software intervention, and is automatically completed by hardware, which well meets the real-time requirements, adopts a data encryption and decryption method based on an access address to support discrete access to the program, and the adaptive width design can flexibly support different data width access methods such as bytes, half words, and words, continuing the advantages of the PRINCE encryption algorithm in real time, low latency, and low cost.

The application relates to a CRC parallel computing method and belongs to the field of data processing. The application fills 0 in non-packet bytes of a message starting word and an ending word; 256-bit input data are divided into 8 lanes, each lane containing 32 bits; recursion of a state register is carried out by using an LFSR circuit, 8 state registers are obtained, the state registers are subjected to XOR operation to obtain a combined state register, the value of the combined state register is subjected to state rollback, and the state register after rollback is the final CRC check value. The application reduces the complexity of CRC state register associated logic by splitting a state transition matrix, and improves circuit timing characteristics; the application eliminates the influence of redundant 0 at the tail of a message on the state register in large-bit-width parallel time through state rollback logic.

The application provides an optimization method of a low-bit arbitrary-size independent convolution simd, comprising the following steps: S1, processing of convolution kernel data, the data storage mode adopts a convolution calculation mode, which can greatly reduce the loading time, and the data needs to be converted; converting the data; S2, design of convolution calculation and accumulation: since the accumulation sum cannot exceed 16 bits after multiplication and adjacent addition, the data must be processed; first, using the 16-bit accumulation sum to calculate, calculating 14 times each time, since the instruction is multiplied first and then adjacent addition in the calculation, the actual instruction accumulation number is 7 times; then, converting the data in the register into 32 bits and accumulating into a 32-bit register. The application can realize a speed increase of several times, and can increase by about 35 times relative to a C program. The 16-bit accumulation can be used, and the speed can be improved.

A decoder for the MIL-STD-1553B bus which operates at a slower clock rate than the 40 MHz industry standard clock rate. This embodiment uses a 10 MHz clock rate. Because the clock rate is slower than the 40 MHz clock rate, the invention will inherently use less power. Additional features of this invention include: flexible resolution timestamp input, error checking and reporting throughout the decode process and 32 bit buffered parallel output of the bus controller and remote terminal communication. In another embodiment the decoder has a plurality of n ancillary clocks which provide partial state timestamps, which are summable to create a system timestamp.

The invention discloses an SOM-Rulkov chaotic system design and kinetic analysis and 3D model hierarchical decryption method, which comprises the following steps: firstly, designing an SOM-Rulkov chaotic system, and finding that the system has an extreme multistable phenomenon and is characterized in that initial values are different, and generated phase diagrams are presented on different levels; secondly, data types of coordinate values of the 3D model are converted into IEEE 754 data standards, and each coordinate value is converted into 32 bits; and finally, applying an extreme multistable phenomenon generated by the SOM-Rulkov chaotic system to 3D model encryption, and performing XOR operation on mantissas of different positions of different phase diagrams and 3D model coordinate values. And at a decryption end, different types of visual effects can be obtained by owning different keys.

The invention discloses a multiply-accumulate operation circuit based on an RISC-V processor and an instruction set expansion method, and the circuit comprises a special multiply-accumulate register pair which is used for storing an accumulated value; the multiplier is used for calculating a product of operands; the adder is used for adding the product and the current accumulated value; the splicing shifter is used for splicing and shifting the final accumulated value; and the CSR read-write interface is used for transmitting data with the general register group. The method is applied to the circuit. According to the circuit and the instruction set expansion method, the special register pair is introduced to store the full-precision intermediate result, so that the precision loss in the operation process is remarkably reduced; by means of programmable splicing shifting operation, multiply-accumulate operation of any Q-format fixed-point number within 32 bits is supported, and high flexibility and high efficiency are achieved; and meanwhile, the original multiplier of the processor is multiplexed, so that the unification of high performance and low hardware overhead is realized.

A non-contact serial bus tester belongs to the technical field of bus communication troubleshooting, and comprises a shell front end cylindrical antenna and a shell body, the shell front end cylindrical antenna is arranged above the shell body, and the front surface of the shell body is sequentially provided with an illuminating lamp, a test button and an information display window from top to bottom. A power switch, a volume regulator, a baud rate selection button, a refresh synchronization button and a bus selection button are sequentially arranged on the side face of the shell body from top to bottom, a loudspeaker and a battery cabin cover are sequentially arranged on the back face of the shell body from top to bottom, and a 32-bit ARM is arranged in the shell body. The cylindrical antenna, the illuminating lamp, the test button, the information display window, the power switch, the volume adjusting button, the baud rate selection button, the refresh synchronization button, the bus selection button, the loudspeaker and the battery cabin cover at the front end of the shell are electrically connected with the 32-bit ARM. The device can be used for troubleshooting bus communication faults, and compared with the prior art, the introduction of new faults is avoided, and the troubleshooting efficiency is also ensured.

1. The name of this design product: Energy Consumption Data Collection Terminal (MR Series-RJ45, 32-bit). 2. Purpose of this design product: used for the collection and management of industrial energy consumption data. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The application relates to a key leakage detection method of an SM3 hash algorithm, which comprises the following steps: firstly, generating a to-be-processed message at random, taking the to-be-processed message as the input of the SM3 algorithm, introducing a random 4-byte fault by adopting a 4-byte random fault model, obtaining an error output hash value, calculating the corresponding value path of 32 bits of the last-but-one round 4-byte register by an exhaustive method, obtaining an intermediate meeting array, obtaining the intermediate state value of the last-but-one round 4-byte register by extending the message group by the exhaustive method, matching the intermediate state value with the intermediate meeting array, and using a statistical method to obtain the partial value of the correct message group, repeatedly introducing the fault and analyzing the process to obtain the correct message group, and finally deducing the correct to-be-processed message. The method provided by the application is easy to implement, fast and high in accuracy, and can provide an important analysis basis for the security research of the SM3 hash algorithm.

Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and / or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

The invention provides a method and a system for converting a FlexBus interface to a PCIe (Peripheral Component Interconnect Express) interface based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: receiving 16-bit data by a FlexBus interface DRAM controller, converting the 16-bit data into 32-bit data through dynamic bit width switching and time-sharing output logic, and storing the 32-bit data into a DRAM; the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission and writes the AXI burst transmission into a DDR specified address; the PCIe BAR space mapping module is used for mapping the DDR address to a PCIe BAR space; and the PCIe equipment initiates a read-write request through the BAR space and converts the read-write request into an AXI signal to interact with the DDR, so that efficient data transmission is achieved. By means of clock domain crossing synchronization, bit width switching, burst transmission optimization and the like, data transmission efficiency and system stability are remarkably improved, and efficient data interaction requirements in the fields of embedded systems and data acquisition are met.

Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and / or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

A spaceborne software EDAC fault-tolerance method for COTS platforms is proposed. Based on the spaceborne EDAC hardware implementation, an EDAC verification module and checksum are designed. The checksum uses Hamming code, with each executable codeword being 32 bits long and the checksum being 7 bits, achieving a one-to-two verification function. Through executable code segment instrumentation, EDAC verification module call statements are inserted before the call statements of each module in the original executable code, enabling EDAC verification to be completed before the called module executes. The checksum of each instrumented executable code is calculated and stored as part of the program area. An improved approach of "running code priority verification" is adopted, combining pre-scheduling verification and idle-period verification to perform EDAC verification on the executable code. Simultaneously, a copy of the EDAC algorithm is stored in the program storage area, enabling mutual verification between the two EDAC algorithm modules to ensure the correctness of the EDAC module itself.