The invention discloses a multi-process packaging
chip heterogeneous
integrated design simulation method and device, and the method comprises the steps: obtaining at least two design files of a
chip design and a packaging design, analyzing the geometric and stacking information in the design files, and generating a
chip three-dimensional model and a packaging three-dimensional model; placing the three-dimensional model of the chip and the three-dimensional model of the
package oppositely to form a stacked structure, and establishing an electrical
interconnection relation between the chip and the
package based on a preset
interconnection mode; a
simulation port is added to the to-be-analyzed network of the stacked structure, and port parameters are defined; respectively configuring different
electromagnetic simulation parameters for the components with different physical scales in the stacked structure; and aiming at the configured model, performing
subdivision by applying an intelligent grid technology, and performing calculation by utilizing a moment method
solver to obtain a
simulation result with packaging. According to the embodiment of the invention, the technical problems of slow simulation operation and low precision in related technologies are solved.