Simulation method and device for heterogeneous integrated design of multi-process packaged chip

Abstract

The invention discloses a multi-process packaging chip heterogeneous integrated design simulation method and device, and the method comprises the steps: obtaining at least two design files of a chip design and a packaging design, analyzing the geometric and stacking information in the design files, and generating a chip three-dimensional model and a packaging three-dimensional model; placing the three-dimensional model of the chip and the three-dimensional model of the package oppositely to form a stacked structure, and establishing an electrical interconnection relation between the chip and the package based on a preset interconnection mode; a simulation port is added to the to-be-analyzed network of the stacked structure, and port parameters are defined; respectively configuring different electromagnetic simulation parameters for the components with different physical scales in the stacked structure; and aiming at the configured model, performing subdivision by applying an intelligent grid technology, and performing calculation by utilizing a moment method solver to obtain a simulation result with packaging. According to the embodiment of the invention, the technical problems of slow simulation operation and low precision in related technologies are solved.

Description

TECHNICAL FIELD

[0001] The application relates to a multi-process packaging chip heterogeneous integration design simulation method and device, and belongs to the technical field of electronic design automation (EDA). BACKGROUND

[0002] With Moore's law approaching the physical limit, heterogeneous integration through advanced packaging technology has become a key path to improve the performance of chip systems. 2.5D / 3D packaging and Chiplet technology can integrate chips of different process technologies and different functions, but face serious challenges in electromagnetic simulation: Modeling is complex: traditional tools are difficult to efficiently process the complex three-dimensional stacking structure of chips, Interposer and packaging across scales (nanometers to centimeters).

[0003] Simulation efficiency is low: existing electromagnetic tools often have slow computing speed, large memory occupation and long iteration period when processing large-scale heterogeneous integration systems.

[0004] Design process is fragmented: chip, packaging and system design simulation are often independent of each other, lack efficient collaborative analysis means, and are prone to design repetition due to collaboration problems. SUMMARY

[0005] Therefore, the application provides a multi-process packaging chip heterogeneous integration design simulation method and device, which can simplify the modeling process of complex heterogeneous integration structure while ensuring accuracy and shorten the model preparation time.

[0006] The first aspect of the embodiment of the application discloses a multi-process packaging chip heterogeneous integration design simulation method, which comprises the following steps: obtaining at least two design files of chip design and packaging design, analyzing the geometric and stacking information in the design files and generating a chip three-dimensional model and a packaging three-dimensional model; placing the chip three-dimensional model and the packaging three-dimensional model relatively to form a stacking structure and establishing an electrical interconnection relationship between the chip and the packaging based on a preset interconnection mode; adding a simulation port to the stacking structure to be analyzed and defining the port parameters; for different physical scale components in the stacking structure, different electromagnetic simulation parameters are configured respectively; for the configured model, the intelligent grid technology is applied for dissection and the method of moments solver is used for calculation to obtain a packaging simulation result.

[0007] Further, the method further comprises: configuring different electromagnetic simulation parameters for different physical scale components in the stacked structure, respectively, including: for a first metal layer and a first via representing a chip, setting a model approximation manner of the first metal layer as a thick film model, setting a model approximation manner of the first via as a lumped model, and applying a first numerical value of a fine mesh; for a second metal layer and a second via representing a package, setting model approximation manners of the second metal layer and the second via as three-dimensional full-wave models, and applying a second numerical value of a sparse mesh, wherein the second numerical value is greater than the first numerical value.

[0008] Further, the method further comprises: establishing an electrical interconnection relationship between the chip and the package based on a preset interconnection manner, including: providing a visual assembly interface; and implementing electrical interconnection of upper and lower chip and package structures in at least one of a bump, a bonding wire, and a hybrid bonding manner; wherein the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; and wherein the local area cutting operation is used for cutting a layout arbitrarily for subsequent simulation on a region of interest.

[0009] Further, the method further comprises: cutting upper and lower chip and package structures of the electrical interconnection based on the local area cutting operation to obtain a single chip three-dimensional model, and further obtaining a simulation result without a package based on the single chip three-dimensional model; and evaluating an influence of a package effect based on the simulation result with the package and the simulation result without the package, wherein the simulation result includes at least one of an S parameter, a power supply impedance, and a DC voltage drop.

[0010] Further, the network to be analyzed is a signal network and / or a power supply network; and the method further comprises: adding a simulation port and defining a port parameter on the network to be analyzed of the stacked structure, including: adding a lumped port and defining a port type and an impedance parameter on the signal network and / or the power supply network.

[0011] A second aspect of the embodiments of the present application discloses a multi-process package chip heterogeneous integration design simulation device, the device comprising: an acquisition module configured to acquire at least two design files of a chip design and a package design, parse geometric and layering information in the design files, and generate a chip three-dimensional model and a package three-dimensional model; an interconnection module configured to relatively place the chip three-dimensional model and the package three-dimensional model to form a stacked structure, and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection manner; a setting module configured to add a simulation port and define a port parameter on a network to be analyzed of the stacked structure; a configuration module configured to configure different electromagnetic simulation parameters for different physical scale components in the stacked structure, respectively; and a simulation module configured to, for a configured model, apply an intelligent mesh technology for subdivision and use a moment method solver for calculation to obtain a simulation result with a package.

[0012] Further, the configuration module comprises: a first setting and applying module, configured to set the model approximation manner of a first metal layer and a first via as a thick film model, set the model approximation manner of the first via as a lumped model, and apply a first number of fine meshes for the first metal layer and the first via; and a second setting and applying module, configured to set the model approximation manner of a second metal layer and a second via as a three-dimensional full-wave model, and apply a second number of sparse meshes for the second metal layer and the second via, wherein the second number is greater than the first number.

[0013] Further, the interconnection module comprises: a providing module, configured to provide a visual assembly interface; and an electrical connection module, configured to realize electrical interconnection of the upper and lower chips and the package structure by using at least one of a bump, a bonding wire, and hybrid bonding; wherein the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; and the local area cutting operation is used to cut the layout arbitrarily for subsequent simulation on a region of interest.

[0014] Further, the device further comprises: a cutting module, configured to cut the upper and lower chips and the package structure of the electrical interconnection based on the local area cutting operation to obtain a single-chip three-dimensional model, and further obtain a simulation result without the package based on the single-chip three-dimensional model; and an evaluation module, configured to evaluate the influence of the package effect based on the simulation result with the package and the simulation result without the package, wherein the simulation result comprises at least one of an S parameter, a power impedance, and a DC voltage drop.

[0015] Further, the network to be analyzed is a signal network and / or a power network; and the setting module is specifically configured to add a lumped port on the signal network and / or the power network and define a port type and an impedance parameter.

[0016] The third aspect of the embodiment of the present application discloses a computer readable storage medium, the computer readable storage medium comprises a stored program, wherein the program controls the processor of the device to execute the multi-process package chip heterogeneous integration design simulation method of the above-mentioned embodiment when the program is running.

[0017] The fourth aspect of the embodiment of the present application discloses a computer device, the computer device comprises a processor and a memory; wherein the memory stores a computer program, the computer program is suitable for being loaded and executed by the processor to execute the multi-process package chip heterogeneous integration design simulation method of the above-mentioned embodiment.

[0018] Compared with the prior art, the embodiment of the present application has the following beneficial effects: 1. Modeling efficiency is greatly improved: through multi-format support, visual stacking, wizard process and intelligent mesh, the modeling process of complex heterogeneous integrated structure is greatly simplified, and the model preparation time is shortened.

[0019] 2. Excellent simulation performance: the method of moments solver (MoM Solver Plus) cooperates with cross-scale mesh technology and three simulation modes, which improves the calculation speed by nearly 10 times and reduces the memory occupation by 1 / 20 compared with traditional methods under the premise of ensuring accuracy.

[0020] 3. Precise cross-scale analysis capability: intelligent mesh and tunneling technology perfectly solve the precision and scale contradiction of nanoscale chip and centimeter scale package collaborative simulation.

[0021] 4. Design iteration is accelerated: "one-stop" multi-process simulation and efficient parallel solution reduce the design iteration times of chip-package-system collaborative analysis and accelerate design convergence. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the structures shown in the drawings.

[0023] Figure 1 The flowchart of the multi-process package chip heterogeneous integrated design simulation method provided by the embodiment of the present application.

[0024] Figure 2 The schematic diagram of importing GDS format design file provided by the embodiment of the present application.

[0025] Figure 3 The schematic diagram of three-dimensional model stacking and editing provided by the embodiment of the present application.

[0026] Figure 4 The schematic diagram of adding edge port provided by the embodiment of the present application.

[0027] Figure 5 The schematic diagram of setting simulation parameters provided by the embodiment of the present application.

[0028] Figure 6 The schematic diagram of setting simulation parameters provided by the embodiment of the present application.

[0029] Figure 7 The structural diagram of the multi-process package chip heterogeneous integrated design simulation device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order for those skilled in the art to better understand the technical scheme of the present application, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] Although the prior art supports partial co-simulation, there is still room for improvement in terms of modeling speed, cross-scale processing accuracy and convenience of system co-simulation process. Therefore, the present application aims to improve the existing technology and proposes a more efficient and accurate rapid modeling method for multi-technology packaged chip heterogeneous integration, in order to build a simulation platform for 2.5D / 3DIC advanced packaging and Chiplet heterogeneous integration design, thereby laying a foundation for solving the above problems. The specific implementation scheme is as follows: Embodiment 1: Figure 1 The flowchart of the multi-technology packaged chip heterogeneous integration design simulation method provided by the embodiments of the present application is shown in Figure Figure 1 As shown in the figure, the method comprises: S101. Obtain at least two design files of chip design and packaging design, parse the geometric and layering information in the design files and generate a chip three-dimensional model and a packaging three-dimensional model.

[0033] First, prepare the chip layout file (such as GDS), the packaging substrate file (such as MCM or GDS) and the corresponding layer mapping file (such as Layer Map). Then, open the electromagnetic simulation platform and create a new project. Finally, as shown in Figure 2 the figure, use the file import function to import the design files of the chip and the packaging in sequence, and the software automatically generates a three-dimensional visual model.

[0034] S102. The chip 3D model and the package 3D model are placed relative to each other to form a stacked structure and an electrical interconnection relationship is established between the chip and the package based on a preset interconnection method.

[0035] In this step, establishing an electrical interconnection between the chip and the package based on a preset interconnection method includes: S1021. Provides a visual assembly interface.

[0036] S1022. Electrical interconnection between upper and lower layer chips and package structure is achieved by using at least one method of bumps, bonding wires and hybrid bonding.

[0037] The visual assembly interface supports flipping, rotating, mirroring, and cutting local areas of any 3D model.

[0038] The local region cutting operation is used to arbitrarily cut the layout for subsequent simulation of the area of ​​interest. It should be noted that local region cutting is equivalent to a removal operation, and its removal range is flexible: it can target a part of a chip or package, cover the entire package, or even remove one or more chips simultaneously.

[0039] For example, such as Figure 3 As shown, in the software's stacking interface, the chip model is set to "Upper Model" and the package model is set to "Lower Model". By dragging and rotating, the chip is precisely placed above the corresponding pads on the package. Then, an appropriate bump model is selected, and connections are added one by one or in batches to the corresponding pads on the chip and package, ultimately completing the three-dimensional electrical interconnection between the chip and the package.

[0040] S103. Add simulation ports and define port parameters on the network to be analyzed in the stacked structure.

[0041] This invention supports multiple methods for creating ports.

[0042] In one embodiment, the network to be analyzed is a signal network and / or a power network. Adding simulation ports and defining port parameters on the network to be analyzed in the stacked structure includes: adding lumped ports on the signal network and / or the power network and defining port type and impedance parameters.

[0043] As an optional implementation, in the 3D view, lumped ports can be added directly to the signal network or power network to be analyzed, and parameters such as port type and impedance can be defined.

[0044] In another embodiment, such as Figure 4 As shown, edge port parameters can be set in the stacked structure.

[0045] S104. Configure different electromagnetic simulation parameters for different physical scale components in the stacked structure respectively.

[0046] In this step, the different electromagnetic simulation parameters for different physical scale components in the stacked structure are configured respectively, including: S1041. For the first metal layer and the first via representing the chip, the model approximation method of the first metal layer is set as a thick film model, the model approximation method of the first via is set as a lumped model, and a first numerical value of fine mesh is applied.

[0047] S1042. For the second metal layer and the second via representing the package, the model approximation method of the second metal layer and the second via is set as a three-dimensional full-wave model, and a second numerical value of sparse mesh is applied, wherein the second numerical value is greater than the first numerical value.

[0048] The core operation of the present application is to implement differentiated settings for the network and model of the chip and the package. Specifically, the metal layer of the chip (nanoscale microstructure) adopts a "Thick" model, the via adopts a "Lumped" model, and the mesh size is set to 5-60 μm; correspondingly, the metal and via of the package (centimeter-level large-size structure) are set as a "3D" full-wave model, and the mesh size is set to 150-250 μm. This is the core of realizing cross-scale accurate simulation (balancing accuracy and calculation scale).

[0049] As a preferred embodiment, the mesh size of the nanoscale microstructure is 10 μm, and the mesh size of the centimeter-level large-size structure is 200 μm. Different mesh sizes and partitioning methods can be set in the table of the Mesh page.

[0050] The above is one of the steps of simulation configuration.

[0051] The configuration of the present embodiment further includes: S1040. According to the analysis target (such as signal integrity S parameter, power DC voltage drop), select the corresponding simulation type (such as signal EM, power DC).

[0052] The configuration of the present embodiment further includes: S1043. According to whether the current design stage is initial verification or final sign-off, select the appropriate mode in the simulation setting: "Speed" mode for rapid iteration, and "Accuracy" mode for high-precision verification.

[0053] The above simulation configuration can be completed through a visual interface.

[0054] S105. For the configured model, apply intelligent meshing technology for partitioning and use a moment method solver for calculation to obtain a simulation result with a package.

[0055] In this step, set the solving parameters as shown in Figure 5 and Figure 6 start the simulation. The software will perform meshing according to the grid size set by different models, and use the efficient MoM solver to calculate, while supporting multi-machine parallel acceleration.

[0056] Specifically, as shown in Figure 5 , select three simulation modes: Speed (speed), Balanced (balance), and Accuracy (accuracy), and set the simulation frequency. The purpose is to enable the electromagnetic simulation engine to accurately calculate the real electrical performance of the designed 2.5D / 3DIC advanced packaging structure at different frequencies.

[0057] Specifically, Figure 6 The setting diagrams of Mesh (meshing) and Advanced (advanced settings) are shown. In the Mesh page, the meshing method can be specified for each layer. The Advanced page is used to configure the solver parameters, such as sweep setting (maximum number of iterations, convergence tolerance) and geometric operation options (such as merging ground vias, removing suspended ground networks, removing redundant vias, etc.), aiming to improve simulation accuracy and speed.

[0058] The core advantage of the accelerated MoM solver is that it provides a fast, efficient and flexible simulation solution for 2.5D / 3DIC and other advanced packaging designs. Through algorithm optimization and distributed computing, the calculation speed is greatly improved and the memory occupation is significantly reduced. The flexible simulation mode can also help engineers to independently weigh efficiency and accuracy, effectively solving the cross-scale simulation problem.

[0059] After the simulation is completed, the software interface displays the S parameter (such as return loss RL, insertion loss IL), power impedance, DC voltage drop, etc. The user can compare the simulation results with and without packaging, and intuitively evaluate the impact of packaging effect, so as to guide the optimization design, as follows: S106. Based on the local area cutting operation, the upper and lower layers of the chip and the packaging structure of the electrical interconnection are cut to obtain a single chip three-dimensional model, and then based on the single chip three-dimensional model, the simulation result without packaging is obtained.

[0060] S107. Based on the simulation result with packaging and the simulation result without packaging, the impact of packaging effect is evaluated, wherein the simulation result includes at least one of S parameter, power impedance and DC voltage drop.

[0061] Figure 7 The structural diagram of the multi-process packaging chip heterogeneous integration design simulation device provided by the embodiment of the application is shown in Figure 7 The device comprises: The acquisition module 701 is configured to acquire at least two design files of a chip design and a package design, parse geometric and layering information in the design files, and generate a chip three-dimensional model and a package three-dimensional model.

[0062] The interconnection module 702 is configured to relatively place the chip three-dimensional model and the package three-dimensional model to form a stacked structure, and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection manner.

[0063] The setting module 703 is configured to add a simulation port to a network to be analyzed of the stacked structure and define a port parameter.

[0064] The configuration module 704 is configured to configure different electromagnetic simulation parameters for different physical scale components in the stacked structure.

[0065] The simulation module 705 is configured to apply an intelligent meshing technology for dissection and a moment method solver for calculation on the configured model, to obtain a simulation result with a package.

[0066] Further, the configuration module comprises: a first setting and applying module configured to set a model approximation manner of a first metal layer of a chip to a thick film model, set a model approximation manner of a first via to a lumped model, and apply a first numerical value of a fine mesh for the first metal layer and the first via; and a second setting and applying module configured to set model approximation manners of a second metal layer of a package and a second via to three-dimensional full-wave models, and apply a second numerical value of a sparse mesh for the second metal layer and the second via, where the second numerical value is greater than the first numerical value.

[0067] Further, the interconnection module comprises: a providing module configured to provide a visual assembly interface; and an electrical connection module configured to realize electrical interconnection of upper and lower chip and package structures by using at least one of a bump, a bonding wire, and a hybrid bonding; where the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; and where the local area cutting operation is used to cut a layout arbitrarily for subsequent simulation on a region of interest.

[0068] Further, the apparatus further comprises: a cutting module configured to cut upper and lower chip and package structures of the electrical interconnection based on the local area cutting operation to obtain a single chip three-dimensional model, and further obtain a simulation result without a package based on the single chip three-dimensional model; and an evaluation module configured to evaluate an influence of a package effect based on the simulation result with the package and the simulation result without the package, where the simulation result comprises at least one of an S parameter, a power impedance, and a DC voltage drop.

[0069] Further, the network to be analyzed is a signal network and / or a power supply network; and the setting module is specifically configured to add a lumped port on the signal network and / or the power supply network and define a port type and an impedance parameter.

[0070] The following effects can be achieved through the above embodiments: 1. Modeling efficiency is greatly improved: through multi-format support, visual stacking, wizard process and intelligent mesh, the modeling process of complex heterogeneous integrated structure is greatly simplified, and the model preparation time is shortened.

[0071] 2. Excellent simulation performance: the method of moments solver (MoM Solver Plus) cooperates with cross-scale mesh technology and three simulation modes, and under the premise of ensuring accuracy, the calculation speed is improved by nearly 10 times compared with traditional methods, and the memory occupation is only 1 / 20.

[0072] 3. Precise cross-scale analysis capability: intelligent mesh and tunneling technology perfectly solve the precision and scale contradiction when simulating the nanoscale chip and centimeter-scale package cooperatively.

[0073] 4. Design iteration is accelerated: "one-stop" multi-process simulation and efficient parallel solution reduce the design iteration times of chip-package-system collaborative analysis, and accelerate the design convergence.

[0074] Embodiment 2: The embodiments of the application further provide a computer device, comprising: a memory storing an executable program; and a processor configured to run the program, wherein the program is configured to execute the method in the embodiments of the application when running.

[0075] The memory described above can refer to a device inside a computer for storing data and programs, and can include a memory, a hard disk, etc., wherein the memory can be used for temporarily storing programs and data being run, the hard disk can be used for long-term storage of programs and data, the memory can be used for the computer to read and write data and execute programs; the processor described above can be responsible for executing instructions in the computer program and processing data, and can be responsible for controlling and executing various operations, including arithmetic operations, logical operations, data transmission, etc.

[0076] Embodiment 3: The embodiments of the application further provide a computer readable storage medium, which comprises a stored executable program, wherein the executable program is configured to control a device where the computer readable storage medium is located to execute the method in the embodiments of the application when running.

[0077] The computer storage medium described above can refer to a medium for storing certain discontinuous physical quantities in a computer memory, and the computer storage medium mainly includes semiconductors, magnetic cores, magnetic drums, magnetic tapes, laser discs, etc.

[0078] Embodiment 4: The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program implements the method in each embodiment of the present application when executed by a processor.

[0079] The computer program product described above can refer to a software program that has been written, tested and released, and can run on a computer or other device. The computer program product can include application programs, operating systems, tool software, etc., and is used to implement specific functions or solve specific problems.

[0080] Embodiment 5: The embodiments of the present application also provide a computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium is used to store a computer program, and the computer program implements the method in each embodiment of the present application when executed by a processor.

[0081] The non-volatile computer readable storage medium described above can refer to a medium for storing data, and the non-volatile computer readable storage medium can keep the data from being lost when power is off. It can be used to store long-term saved data such as operating systems, application programs and user files. The non-volatile storage medium can include hard drives, solid state drives, optical discs and flash memory devices, etc.

[0082] Embodiment 6: The embodiments of the present application also provide a computer program, and the computer program implements the method in each embodiment of the present application described above when executed by a processor.

[0083] The computer program described above can refer to a set of instructions for telling a computer to perform specific tasks or operations. The computer program can be written by a programmer using a specific programming language, and can include algorithms, data structures, logic and control flow, etc. The computer program can be used for various purposes, including application software, operating systems, etc.

[0084] In the above embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0086] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0089] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for multi-technology package chip heterogeneous integration design simulation, characterized in that, The method comprises the following steps: obtaining at least two design files of a chip design and a package design, analyzing geometric and layering information in the design files and generating a chip three-dimensional model and a package three-dimensional model; relatively placing the chip three-dimensional model and the package three-dimensional model to form a stacked structure and establishing an electrical interconnection relationship between the chip and the package based on a preset interconnection mode; adding a simulation port to a network to be analyzed of the stacked structure and defining a port parameter; configuring different electromagnetic simulation parameters for different physical scale components in the stacked structure; applying an intelligent grid technology to perform dissection and using a moment method solver to perform calculation on the configured model to obtain a simulation result with a package.

2. The multi-technology package chip heterogeneous integration design emulation method of claim 1, wherein, The step of configuring different electromagnetic simulation parameters for different physical scale components in the stacked structure comprises: for a first metal layer and a first via hole representing the chip, setting a model approximation mode of the first metal layer as a thick film model, setting a model approximation mode of the first via hole as a lumped model, and applying a first numerical value of a fine grid; for a second metal layer and a second via hole representing the package, setting model approximation modes of the second metal layer and the second via hole as three-dimensional full-wave models, and applying a second numerical value of a sparse grid, wherein the second numerical value is greater than the first numerical value.

3. The multi-technology package chip heterogeneous integration design emulation method of claim 1, wherein, The step of establishing an electrical interconnection relationship between the chip and the package based on a preset interconnection mode comprises: providing a visual assembly interface; adopting at least one of a bump, a bonding wire and a hybrid bonding to realize electrical interconnection of upper and lower chip and package structures; wherein the visual assembly interface supports flip, rotation, mirroring and local area cutting operations on any three-dimensional model; wherein the local area cutting operation is used for cutting a layout arbitrarily for subsequent simulation on a region of interest.

4. The multi-technology package chip heterogeneous integration design emulation method of claim 3, wherein, The method further comprises: cutting upper and lower chip and package structures of the electrical interconnection based on the local area cutting operation to obtain a single chip three-dimensional model, and further obtaining a simulation result without a package based on the single chip three-dimensional model; evaluating an influence of a package effect based on the simulation result with the package and the simulation result without the package, wherein the simulation result comprises at least one of an S parameter, a power supply impedance and a DC voltage drop.

5. The multi-technology package chip heterogeneous integration design emulation method of claim 1, wherein, The network to be analyzed is a signal network and / or a power supply network; The step of adding a simulation port to the network to be analyzed of the stacked structure and defining a port parameter comprises: adding a lumped port to the signal network and / or the power supply network and defining a port type and an impedance parameter.

6. A multi-technology package chip heterogeneous integration design emulation apparatus, comprising: The method comprises the following steps: an obtaining module, configured to obtain at least two design files of a chip design and a package design, analyze geometric and layering information in the design files and generate a chip three-dimensional model and a package three-dimensional model; an interconnection module, configured to relatively place the chip three-dimensional model and the package three-dimensional model to form a stacked structure and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection mode; a setting module, configured to add a simulation port to a network to be analyzed of the stacked structure and define a port parameter; a configuration module, configured to configure different electromagnetic simulation parameters for different physical scale components in the stacked structure; an obtaining module, configured to obtain at least two design files of a chip design and a package design, analyze geometric and layering information in the design files and generate a chip three-dimensional model and a package three-dimensional model; an interconnection module, configured to relatively place the chip three-dimensional model and the package three-dimensional model to form a stacked structure and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection mode; a setting module, configured to add a simulation port to a network to be analyzed of the stacked structure and define a port parameter; a configuration module, configured to configure different electromagnetic simulation parameters for different physical scale components in the stacked structure; The simulation module is configured to apply smart grid technology to divide the configured model and use a moment method solver to obtain a simulation result with encapsulation.

7. The multi-process package chip heterogeneous integration design emulation apparatus of claim 6, wherein, The configuration module comprises: The first setting and applying module is configured to set the model approximation method of the first metal layer to a thick film model and the model approximation method of the first via to a lumped model, and apply a first number of fine meshes for the first metal layer and the first via representing a chip. The second setting and applying module is configured to set the model approximation method of the second metal layer and the second via to a three-dimensional full-wave model, and apply a second number of sparse meshes for the second metal layer and the second via representing a package, wherein the second number is greater than the first number.

8. The multi-process package chip heterogeneous integration design emulation apparatus of claim 6, wherein, The interconnection module comprises: The providing module is configured to provide a visual assembly interface; The electrical connection module is configured to realize electrical interconnection between upper and lower chips and the package structure by at least one of a bump, a bonding wire and a hybrid bonding; The visual assembly interface supports flipping, rotating, mirroring and local area cutting operations on any three-dimensional model. The local area cutting operation is used to cut the layout arbitrarily for subsequent simulation of a region of interest.

9. The multi-process package chip heterogeneous integration design emulation apparatus of claim 8, wherein, Further comprising: The cutting module is configured to cut the upper and lower chips and the package structure of the electrical interconnection to obtain a single chip three-dimensional model based on the local area cutting operation, and further obtain a simulation result without encapsulation based on the single chip three-dimensional model. The evaluation module is configured to evaluate the influence of the package effect based on the simulation result with encapsulation and the simulation result without encapsulation, wherein the simulation result comprises at least one of an S parameter, a power impedance and a DC voltage drop.

10. The multi-technology package chip heterogeneous integration design emulation apparatus of claim 6, wherein, The network to be analyzed is a signal network and / or a power network. The setting module is specifically configured to add a lumped port on the signal network and / or the power network and define a port type and an impedance parameter.

Images