22 results about "Processor element" patented technology

Selecting low-power modes (LPMs) based on monitoring inter-processor interrupt (IPI) arrival intervals in processor devices is disclosed herein. In some aspects, a processor device comprises a plurality of processor elements (PEs) and an LPM selection circuit. The LPM selection circuit is configured to determine an average IPI arrival interval for a PE of the plurality of PEs based on an IPI arrival history table for the PE. The LPM selection circuit then determines whether the average IPI arrival interval is greater than a minimum residency interval for a first LPM of the PE, wherein the first LPM is associated with lower power consumption and higher entry and exit latency relative to a second LPM of the PE. If so, the LPM selection circuit places the PE in the first LPM; otherwise, the LPM selection circuit places the PE in the second LPM.

Example apparatus disclosed herein include an array of processor elements, the array including rows each having a first number of processor elements and columns each having a second number of processor elements. Disclosed example apparatus also include configuration registers to store descriptors to configure the array to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of multiple tensor processing templates, ones of the processor elements to be configured based on the descriptors to implement the one of the tensor processing templates to operate on input activation data and filter data associated with the layer of the convolutional neural network to produce output activation data associated with the layer of the convolutional neural network. Disclosed example apparatus further include memory to store the input activation data, the filter data and the output activation data associated with the layer of the convolutional neural network.

An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

The present disclosure describes apparatuses and methods for implementing a pipelined processor with configurable grouping of processor elements. In aspects, an apparatus comprises a host interface configured for communication with a host system, a media interface configured to enable access to storage media, and a plurality of processor elements operably coupled to at least one of the host interface and the media interface. The plurality of processor elements is organized into multiple stages of a pipelined processor for processing data access commands associated with the host system. In various implementations, the plurality of processor elements can be selectively grouped to form the multiple stages of the pipelined processor and loaded with microcode to implement respective functions of each stage of the pipelined processor. By so doing, the pipelined processor may be configured based on various parameters to improve processing performance when processing the data access commands of the host system.

A processor element is described herein. The processor element includes a silicon layer. The processor element further includes one or more conductive electrodes. The processor element further includes a dielectric material having a non-uniform thickness, the dielectric material being disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field distribution to induce quantum dots at an interface between the silicon layer and the dielectric layer. Methods are also described herein.

It is an object of the present disclosure to provide an arithmetic processing device. An arithmetic processing device (1) configured from a network having a plurality of nodes, each of which includes a plurality of processor elements, includes: a write-out processing unit (12) that writes out data of image information, which is input, divided and transposed for each node, to a predetermined area in a memory device (20);a change processing unit (13) that changes a correspondence relationship between the predetermined area of the memory device and the node in accordance with a tensor shape of the image information; and a read-out processing unit (14) that reads out the data stored in the memory device to a corresponding node.

A data processing apparatus includes interception circuitry for intercepting an incoming signal corresponding to an instruction from a processor element to a PCI device. Respond circuitry provides a response to the incoming signal back to the processor element and the response is either an acceptance of the incoming signal or a refusal of the incoming signal based on a flow control between the data processing apparatus and the PCI device. Forward circuitry performs a transmission, to the PCI device, of an outgoing signal corresponding to the command after the response has indicated acceptance of the incoming signal.

The present disclosure relates to an array of configurable processor elements for implementing a convolutional neural network. An example apparatus disclosed includes an array of processor elements including rows each having a first number of processor elements and columns each having a second number of processor elements. The example apparatus also includes configuration registers to store descriptors for configuring the array of processor elements to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of a plurality of tensor processing templates, some of the processor elements to be configured to implement the one of the tensor processing templates based on the descriptors to operate on input activation data and filter data associated with the layer of the convolutional neural network to generate output activation data associated with the layer of the convolutional neural network. The example apparatus also includes a memory to store the input activation data, the filter data, and the output activation data.

Implementations relate to an electronic add-on module releasably attachable to an injection device prior to injection, a sensor element for detecting a state or process in the injection device, a processor element for evaluating and / or processing a signal of the sensor element, and an energy store for supplying the processor element with energy. The add-on module has a first module part, which is connectable along its longitudinal axis to the injection device in an axially fixed manner by means of a holding mechanism. A second module part is movable for a damped relative movement, such as a deceleration or braking movement, by a delay stoke with respect to the first module part connected to the injection device. By damping a relative movement between two module parts, the force transmission between the add-on module and the injection device is controlled and a maximum force surge is limited to the injection device.

Example apparatus disclosed herein include an array of processor elements, the array including rows each having a first number of processor elements and columns each having a second number of processor elements. Disclosed example apparatus also include configuration registers to store descriptors to configure the array to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of multiple tensor processing templates, ones of the processor elements to be configured based on the descriptors to implement the one of the tensor processing templates to operate on input activation data and filter data associated with the layer of the convolutional neural network to produce output activation data associated with the layer of the convolutional neural network. Disclosed example apparatus further include memory to store the input activation data, the filter data and the output activation data associated with the layer of the convolutional neural network.

A processor of an aspect includes a banked memory. The banked memory has a plurality of memory banks. The processor also includes a single instruction, multiple thread (SIMT) processor. The SIMT processor includes a plurality of processor elements. The processor elements are to perform memory access operations with memory addresses. The processor also includes banked memory access circuitry coupled with the banked memory, and coupled with the SIMT processor. The banked memory access circuitry is to access data in the banked memory with each of the memory addresses. The banked memory access circuitry is reconfigurable during runtime to map the memory addresses to the memory banks in a plurality of different ways. Other processors, methods, systems, and non-transitory machine-readable storage mediums are also disclosed.

Device (1000) for selecting a training and / or usage recommendation and / or a characterization, comprising - Providing and / or contextually inserting at least one element of a selection of a training and / or usage recommendation and / or a characterization, - Presentation of the training and / or usage recommendation and / or a characterization by means of a presentation device, in particular a screen, - Processing of the training and / or usage recommendation and / or a characterization by at least one processor element, characterized by the fact that the provisioning and / or contextual insertion is based on exactly one element, which is selected from a group consisting of the elements scepter (1), surprise bag (3), paragraph (2) and tuning fork type (4).

A multi-processor system and image processing method for a multi-lens camera are disclosed. The system includes a plurality of processor elements and a plurality of links. Each processor element includes a plurality of input / output (I / O) ports and a processing unit. The multi-lens camera captures a field of view having an X degree horizontal field of view and a Y degree vertical field of view, where X<=360 and Y<180. Each link connects one of the plurality of I / O ports of one of the plurality of processor elements to one of the plurality of I / O ports of another of the plurality of processor elements, such that each processor element is connected to one or two adjacent processor elements with two or more links, each link being configured to transmit data in a single direction.

The purpose of the present disclosure is to provide an arithmetic processing device. An arithmetic processing device (1) provided with a network having a plurality of nodes and a plurality of processor elements as one node, the arithmetic processing device comprising: a write processing unit (12) that writes data of image information obtained by dividing and transposing inputted image information for each node into a predetermined region in a storage device (20); a change processing unit (13) that changes the correspondence between a predetermined region and a node in the storage device in accordance with the tensor shape of the image information; and a read-out processing unit (14) that reads out the data stored in the storage device to the corresponding node.

A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.

An arithmetic processing device is configured from a network having a plurality of nodes, each of which includes a plurality of processor elements. The arithmetic processing device includes: a write-out processing unit that writes out data of image information, which is input, divided and transposed for each node, to a predetermined area of a memory device; a change processing unit that changes a correspondence relationship between the predetermined area of the memory device and the node in accordance with a tensor shape of the image information; and a read-out processing unit that reads out the data stored in the memory device to a corresponding node.

Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input / output I / O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.

Provided are systems, methods, and apparatuses for a standalone architecture for processing in memory. In one or more examples, the systems, devices, and methods include assigning, via application code of a host of a memory system in package, a kernel sub grid of a kernel grid to a stack of memory dies; assigning, via a microcontroller of a base die of the stack, execution of a first thread block of the kernel sub grid to a first processor element of the stack; assigning, via the microcontroller, execution of a second thread block of the kernel sub grid to a second processor element of the stack; executing threads of the first thread block on the first processor element; and executing threads of the second thread block on the second processor element.

A hybrid bonding structure includes a local transmission line and a global transmission line each connecting a memory chip to a logic chip. During a read operation, data is directly transmitted from the memory chip to the logic chip through the local transmission line. During a write operation, data is transmitted from the logic chip to the memory chip through the global transmission line. A control signal is transmitted from the logic chip to the memory chip through the global transmission line. Accordingly, a plurality of banks implemented in the memory chip can be simultaneously controlled and a plurality of Processor Element s (Pes) implemented in the logic chip may operate as a single core. The hybrid bonding structure may be used to implement a machine learning accelerator.

Systems, methods, and apparatus are provided for a standalone architecture for in-memory processing. In one or more examples, the systems, devices, and methods include assigning inner core subgrids of a core grid to stacked memory modules by application code of a host of a memory system level package; allocating, by a microcontroller of a base die of the stacked memory module, execution of a first thread block of the inner core sub-grid to a first processor element of the stacked memory module; assigning, by the microcontroller, execution of a second thread block of the inner core sub-grid to a second processor element of the stacked memory module; executing threads of the first thread block on the first processor element; and executing threads of the second thread block on the second processor element.

A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Provided are systems, methods, and apparatuses for a standalone architecture for processing in memory. In one or more examples, the systems, devices, and methods include assigning, via application code of a host of a memory system in package, a kernel sub grid of a kernel grid to a stacked memory module; assigning, via a microcontroller of a base die of the stacked memory module, execution of a first thread block of the kernel sub grid to a first processor element of the stacked memory module; assigning, via the microcontroller, execution of a second thread block of the kernel sub grid to a second processor element of the stacked memory module; executing threads of the first thread block on the first processor element; and executing threads of the second thread block on the second processor element.