70 results about "Vertical field" patented technology

A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor. The bottom source / drain region includes a trench epitaxial layer below the bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source / drain region by a bottom spacer. A top source / drain region is over the topmost surface of the channel fin. The top source / drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure also includes a backside metal contact within the backside interlayer dielectric. The backside metal contact is electrically connected to and vertically aligned with the bottom source / drain region.

The embodiment of the utility model provides a semiconductor device which comprises a first vertical field effect transistor and a second vertical field effect transistor, the first vertical field effect transistor is provided with a first drain electrode / source electrode region and a second drain electrode / source electrode region, and the second vertical field effect transistor is provided with a third drain electrode / source electrode region and a fourth drain electrode / source electrode region. The device includes a first power contact on a front side of the device and coupled to a first drain / source region, a second power contact on a front side of the device and coupled to a third drain / source region, and a contact, the contacts are on the backside of the device and coupled to the second drain / source region and the fourth drain / source region, thereby reducing area of the vertical field effect transistor device, increasing gate density, and reducing metal layer coupling.

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

A cell architecture is provided. A cell architecture may be provided that includes a vertical field effect transistor having: at least two fins acting as vertical channels; a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing a connection therebetween; and a top source / drain including a first top source / drain portion on the first fin and a second top source / drain portion on the second fin. The cell architecture further includes a gate contact structure connected to the third gate portion; a top source / drain contact structure connected to one of the first top source / drain portion and the second top source / drain portion and serving as a horizontal conductive wiring layer; and a metal pattern on the gate contact structure and the top source / drain contact structure and connected thereto through a via, and serving as a vertical conductive wiring layer.

A vertical field effect transistor. The vertical field effect transistor includes: a drift area; a semiconductor fin on or above the drift area; a connection area on or above the semiconductor fin; and a gate electrode, which is formed adjacent to at least one side wall of the semiconductor fin, the semiconductor fin, in a first section, which is situated laterally adjacent to the gate electrode, having a lesser lateral extension than in a second section, which contacts the drift area, and / or than in a third section, which contacts the connection area.

A circuit (400) includes a low voltage flash memory (200) integrated with a vertical field effect transistor and a non-volatile memory element (100). The low voltage flash memory is coupled with the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can provide a lower significant conductance and the non-volatile memory element can provide a higher significant conductance. The low voltage flash memory can include a source and a drain. The source can be separated from the drain by an epitaxial channel. The low voltage flash memory can include a floating gate. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The low voltage flash memory can include a control gate. The control gate can be separated from the floating gate by a second dielectric layer.

The present invention provides a vertical field effect transistor (VFET) device and a method for manufacturing the same. The method for manufacturing a VFET device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer including a bottom source / drain (S / D) region; forming a shallow trench under the top surface of the substrate and through the doped layer and the substrate between the fin structures to isolate the fin structures from each other; filling the shallow trench and the space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above the height of the top surface of the doped layer except in the shallow trench such that a shallow trench isolation (STI) structure having a top surface at or above the height of the top surface of the doped layer is formed in the shallow trench; forming gate structures on the fin structures respectively; and forming top S / D regions on the fin structures.

The invention relates to a vertical field effect transistor (FET). A vertical FET according to the present invention includes a substrate and a first electrode configured as a source or drain of the transistor. The device includes a second electrode configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode at an overlap region. Further, the device includes an active layer sandwiched between the first electrode and the second electrode, and a gate having a gate conductor portion and a gate insulating layer disposed between the active layer and the gate conductor portion to avoid direct contact of the active layer and the gate conductor portion. The active layer includes a 1D material configured with a longitudinal axis substantially parallel to the substrate, and / or a 2D material configured with a plane substantially parallel to the substrate. The invention further comprises a method for manufacturing such a vertical field effect transistor and a method for manufacturing a complementary logic device.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.

A VFET cell implementing a vertical field-effect transistor (VFET) circuit on multiple gate grids includes: a first circuit including at least one VFET and provided on at least one gate grid; and a second circuit including at least one VFET and provided on at least one gate grid formed on the left or right side of the first circuit, wherein the gates of the VFETs of the first circuit are configured to share the gate signal or source / drain signal of the VFETs of the second circuit, and the first circuit is an (X-1) contact polypitch (CPP) circuit, which is (X-1)CPP wide, derived from an X-CPP circuit, the X-CPP circuit being X-CPP wide and performing the same logic function as the (X-1)CPP circuit, where X is an integer greater than 1.

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source / drain region beneath the at least one vertical fin, a top source / drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source / drain region and first and second contact spacers disposed on each side of the contact.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.

A vertical field effect transistor (10) is provided. The vertical field effect transistor has a first semiconductor layer (13) on or above a drift region (12), the first semiconductor layer having a p-conductivity type, a trench structure (50) penetrating the first semiconductor layer (13) vertically, wherein the trench structure (50) has at least one sidewall on which a field effect transistor (FET) channel region is configured, wherein the FET channel region has a III-V heterostructure (15 / 16) for configuring a two-dimensional electron gas on an interface of the III-V heterostructure (15 / 16), a source / drain electrode (21) which is in an electrically conductive connection with the III-V heterostructure (15 / 16), a contact structure (24, 25) at least partially on or above the drift region (12), the contact structure at least configuring a Schottky contact or a hetero contact with the drift region (12), wherein the contact structure (24, 25) is in an electrically conductive connection with the source / drain electrode (21), wherein a region at least vertically between the contact structure (24, 25) and the drift region (12) is free of the first semiconductor layer (13).

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.

A microelectronic structure includes a first vertical field-effect-transistor (FET) and a second vertical FET. The first vertical FET is adjacent to the second vertical FET and the first vertical FET includes a top source / drain. A lateral extending contact that is located on top of the top source / drain and the lateral extending contact extends towards the second vertical FET. A backside contact located between the first vertical FET and the second vertical FET. The backside contact is connected to a backside surface of the lateral extending contact. The backside contact has a first critical dimension located at the backside surface of the backside contact. The backside contact has a second critical dimension located at the backside surface of the lateral extending contact. The first critical dimension is greater than the second critical dimension.

The invention relates to a high-power composite trench gate vertical field effect transistor and a preparation method thereof. The high-power composite trench gate vertical field effect transistor comprises a # imgabs0 # single crystal substrate; the epitaxial layer is epitaxially grown on the # imgabs 1 # single crystal substrate; the vertical trench gate structure is formed by etching the epitaxial layer through inductively coupled plasma; a composite gate dielectric layer # imgabs2 # covering the inner wall of the vertical trench gate structure is provided with a source electrode on the surface of the epitaxial layer, a gate electrode is arranged on the surface of the composite gate dielectric layer, and a drain electrode is arranged on one side, opposite to the epitaxial layer, of the # imgabs3 # single crystal substrate. Compared with the prior art, the composite trench gate vertical transistor is designed, the surface state can be effectively depleted, the device has better gate control capability, and the low-defect-density homoepitaxy # imgabs4 # MOSFET device with the high-quality single crystal as the substrate has high current density and breakdown voltage at the same time and adapts to the requirement of a higher-power application scene.

The invention discloses a dual-band photoelectric detection manganese zinc ferrite vertical field effect transistor and a preparation method thereof. The dual-band photoelectric detection manganese zinc ferrite vertical field effect transistor comprises a substrate, a gate oxide layer and a first channel which are sequentially stacked from bottom to top, a second channel is arranged between the source electrode and the first channel; a drain electrode and a grid electrode are arranged on opposite sides of the source electrode; the first channel is a graphene film, and the second channel is a manganese zinc ferrite film; the first channel and the second channel form a heterojunction; the invention is characterized in that the manganese zinc ferrite film is introduced, and the film has a photoelectric detection function in visible light and ultraviolet light wavebands by adjusting the components and formula of the film. Meanwhile, performance regulation and control can be realized by various means: through coupling with the graphene film, the light-dark current ratio of the transistor can be improved; the photoelectric detection performance of the transistor can be regulated and controlled by regulating and controlling the size and the direction of the external magnetic field.

A fin structure for a vertical field-effect transistor (VFET) and a method thereof are provided. The method includes: forming a plurality of mandrels on a substrate, with at least one first gap between the mandrels; forming a plurality of first spacers on side surfaces of the mandrels, such that at least one second gap smaller than the first gap is formed between the first spacers; forming second spacers on side surfaces of the first spacers; removing the mandrels and the first spacers, retaining the second spacers; removing a predetermined portion of the second spacers, such that the remaining second spacers have a two-dimensional shape in a top view; and removing a portion of the substrate not below the remaining second spacers and the remaining second spacers, such that the portion of the substrate below the remaining second spacers forms the fin structure.

The present invention discloses a vertical field-effect transistor based on a modulated island structure and its fabrication method. This device primarily addresses the problem of existing gallium nitride-based power devices lacking good bidirectional conduction characteristics, which leads to increased circuit cost and decreased performance. From bottom to top, the device comprises: a drain, a substrate layer, a drift layer, an N-type GaN channel layer, a top metal layer, and a passivation layer. A first P-type GaN layer and a second P-type GaN layer are positioned on either side of the N-type GaN channel layer. The first P-type GaN layer is evenly divided into n blocks by grooves to form a modulated island structure. Modulated block metal is positioned on the drift layer, the N-type GaN channel layer, and the first P-type GaN layer. A gate and a gate field plate are positioned on the second P-type GaN layer. MESA isolation trenches are positioned around the entire device. This device reduces the reverse conduction turn-on voltage drop and increases the on-current. It also features low leakage current and high withstand voltage during blocking, exhibiting excellent bidirectional conduction characteristics and suitable for use as a power switching device.

A cell signal measuring device and a manufacturing and operating method thereof are disclosed. The disclosed cell signal measuring device may be a cell signal measuring device comprising a vertical field effect transistor, wherein the vertical field effect transistor includes: a drain electrode including a two-dimensional nanomaterial; a vertical nanostructure vertically disposed on the drain electrode; a source electrode disposed to make electrical contact with the top of the nanostructure or an area adjacent thereto; a gate insulating layer disposed on the surface of the nanostructure; a gate electrode disposed on the gate insulating layer between the drain electrode and the source electrode so as to encompass a part of the nanostructure; and a separation layer filling the space between the gate electrode and the source electrode. The cell signal measuring device can: cause the source electrode to make contact with a cell or penetrate thereinto so as to measure a signal of the cell; and change a gate voltage applied to the gate electrode, so as to adjust the intensity of the signal measured from the cell.

Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.

A vertical field-effect transistor. The vertical field-effect transistor includes: a drift region, a semiconductor fin on or above the drift region, and a source / drain electrode on or above the semiconductor fin. The semiconductor fin includes at least one concave side wall in the region between the drift region and the source / drain electrode.

This disclosure relates to a vertical field-effect transistor (FET). The vertical FET according to the present invention includes a substrate (101) and a first electrode (102) configured as either the source or the drain of the transistor. The device includes a second electrode (104) configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode in an overlapping region. Furthermore, the device includes a gate configuration comprising an active layer (103) sandwiched between the first electrode and the second electrode, a gate conductor portion (107), and a gate insulating layer (106) disposed between the active layer (103) and the gate conductor portion (107) to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) includes a one-dimensional material whose longitudinal axis is oriented parallel to the substrate (101), and / or a two-dimensional material whose plane is oriented substantially parallel to the substrate (101). This disclosure further includes methods (3000) for manufacturing such vertical field-effect transistors and complementary logic devices.

A cell architecture is provided. A cell architecture can be provided that includes a vertical field effect transistor having at least two fins serving as vertical channels, a gate including a first gate portion surrounding a first fin, a second gate portion surrounding a second fin, and a third gate portion providing a connection therebetween, and a top source / drain including a first top source / drain portion on the first fin and a second top source / drain portion on the second fin. The cell architecture further includes a gate contact structure connected to the third gate portion, a top source / drain contact structure connected to one of the first and second top source / drain portions and serving as a horizontal conductive wiring layer, and a metal pattern on and connected to the gate contact structure and the top source / drain contact structure through vias and serving as a vertical conductive wiring layer.

The present invention discloses a high-voltage superjunction VDMOS device terminal structure and its manufacturing method, comprising: growing an epitaxial layer on a heavily doped conductive substrate; forming a transition oxide layer on top of the epitaxial layer; implanting a first doped region, a second doped region, and a third doped region into the top region of the epitaxial layer; etching multiple groups of terminal trenches in the epitaxial layer; forming a vertical field plate dielectric layer on the sidewalls of the terminal trenches; filling the terminal trenches to form a vertical resistive field plate; forming a horizontal resistive field plate on top of the epitaxial region; and forming a drain metal electrode, a source metal electrode, and a floating metal electrode. In the present invention, the terminal structure utilizes superjunction, field plate, and field stop ring technologies. The horizontal resistive field plate can provide a low potential to the vertical resistive field plate and the second doped region. The provision of a stop ring can effectively reduce the electric field spike at the bottom of the resistive field plate, significantly reducing the planar terminal area and achieving device miniaturization.

The present invention is conceived to provide a method for manufacturing a fin structure of a vertical field effect transistor (VFET) and a fin structure manufactured by the method. The method includes: (a) patterning a lower layer and an upper layer deposited on the lower layer to form two patterns extending in two directions perpendicular to each other; (b) forming a first spacer and a second spacer side by side in the two patterns along the sidewalls of the lower layer and the upper layer exposed by patterning; (c) removing the first spacer, the second spacer and the upper layer above the level of the top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed by the two patterns in a top view; (d) removing the lower layer, the upper layer and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except for a portion of the substrate located below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby obtaining a fin structure.

A cell architecture for a vertical field effect transistor (VFET) is provided. The cell architecture includes a top source / drain (S / D) contact structure having a square shape in a top view, a horizontal metal pattern formed on the top S / D contact structure and extending in a first direction, and a vertical metal pattern sending out an output signal of a logic circuit formed by the VFET. The cell architecture also includes a gate contact structure formed on a gate connection pattern connecting gates of the VFET, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

The application belongs to the technical field of semiconductor device preparation, and relates to a metal mesh source electrode for a transistor, a transistor, a preparation method of the transistor and application of the transistor. In view of the problems of serious gate electric field shielding of a source electrode, discontinuous conductive path, difficult control of geometric morphology, and insufficient current injection uniformity and stability in the prior art, the application provides a metal mesh source electrode for a transistor, which comprises a metal conductive layer with mutually interconnected metal stripes and forming a grid gap, the stripe width of the metal stripes is 0.2-20 microns, and the duty cycle is 10-50%. The application further provides a preparation method of the metal mesh source electrode, which forms a crack template on the surface of a substrate and deposits metal, and removes the crack template to obtain a metal mesh conductive layer with controllable structure. Meanwhile, the application further provides application of the metal mesh source electrode in a vertical field effect transistor.