29 results about "Vertical field" patented technology

A cell architecture is provided. A cell architecture may be provided that includes a vertical field effect transistor having: at least two fins acting as vertical channels; a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing a connection therebetween; and a top source / drain including a first top source / drain portion on the first fin and a second top source / drain portion on the second fin. The cell architecture further includes a gate contact structure connected to the third gate portion; a top source / drain contact structure connected to one of the first top source / drain portion and the second top source / drain portion and serving as a horizontal conductive wiring layer; and a metal pattern on the gate contact structure and the top source / drain contact structure and connected thereto through a via, and serving as a vertical conductive wiring layer.

A circuit (400) includes a low voltage flash memory (200) integrated with a vertical field effect transistor and a non-volatile memory element (100). The low voltage flash memory is coupled with the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can provide a lower significant conductance and the non-volatile memory element can provide a higher significant conductance. The low voltage flash memory can include a source and a drain. The source can be separated from the drain by an epitaxial channel. The low voltage flash memory can include a floating gate. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The low voltage flash memory can include a control gate. The control gate can be separated from the floating gate by a second dielectric layer.

The invention relates to a vertical field effect transistor (FET). A vertical FET according to the present invention includes a substrate and a first electrode configured as a source or drain of the transistor. The device includes a second electrode configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode at an overlap region. Further, the device includes an active layer sandwiched between the first electrode and the second electrode, and a gate having a gate conductor portion and a gate insulating layer disposed between the active layer and the gate conductor portion to avoid direct contact of the active layer and the gate conductor portion. The active layer includes a 1D material configured with a longitudinal axis substantially parallel to the substrate, and / or a 2D material configured with a plane substantially parallel to the substrate. The invention further comprises a method for manufacturing such a vertical field effect transistor and a method for manufacturing a complementary logic device.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.

A VFET cell implementing a vertical field-effect transistor (VFET) circuit on multiple gate grids includes: a first circuit including at least one VFET and provided on at least one gate grid; and a second circuit including at least one VFET and provided on at least one gate grid formed on the left or right side of the first circuit, wherein the gates of the VFETs of the first circuit are configured to share the gate signal or source / drain signal of the VFETs of the second circuit, and the first circuit is an (X-1) contact polypitch (CPP) circuit, which is (X-1)CPP wide, derived from an X-CPP circuit, the X-CPP circuit being X-CPP wide and performing the same logic function as the (X-1)CPP circuit, where X is an integer greater than 1.

A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

A vertical field effect transistor (10) is provided. The vertical field effect transistor has a first semiconductor layer (13) on or above a drift region (12), the first semiconductor layer having a p-conductivity type, a trench structure (50) penetrating the first semiconductor layer (13) vertically, wherein the trench structure (50) has at least one sidewall on which a field effect transistor (FET) channel region is configured, wherein the FET channel region has a III-V heterostructure (15 / 16) for configuring a two-dimensional electron gas on an interface of the III-V heterostructure (15 / 16), a source / drain electrode (21) which is in an electrically conductive connection with the III-V heterostructure (15 / 16), a contact structure (24, 25) at least partially on or above the drift region (12), the contact structure at least configuring a Schottky contact or a hetero contact with the drift region (12), wherein the contact structure (24, 25) is in an electrically conductive connection with the source / drain electrode (21), wherein a region at least vertically between the contact structure (24, 25) and the drift region (12) is free of the first semiconductor layer (13).

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.

A microelectronic structure includes a first vertical field-effect-transistor (FET) and a second vertical FET. The first vertical FET is adjacent to the second vertical FET and the first vertical FET includes a top source / drain. A lateral extending contact that is located on top of the top source / drain and the lateral extending contact extends towards the second vertical FET. A backside contact located between the first vertical FET and the second vertical FET. The backside contact is connected to a backside surface of the lateral extending contact. The backside contact has a first critical dimension located at the backside surface of the backside contact. The backside contact has a second critical dimension located at the backside surface of the lateral extending contact. The first critical dimension is greater than the second critical dimension.

A vertical field-effect transistor. The vertical field-effect transistor includes: a drift region, a semiconductor fin on or above the drift region, and a source / drain electrode on or above the semiconductor fin. The semiconductor fin includes at least one concave side wall in the region between the drift region and the source / drain electrode.

This disclosure relates to a vertical field-effect transistor (FET). The vertical FET according to the present invention includes a substrate (101) and a first electrode (102) configured as either the source or the drain of the transistor. The device includes a second electrode (104) configured as the other of the source and drain of the transistor, the second electrode at least partially overlapping the first electrode in an overlapping region. Furthermore, the device includes a gate configuration comprising an active layer (103) sandwiched between the first electrode and the second electrode, a gate conductor portion (107), and a gate insulating layer (106) disposed between the active layer (103) and the gate conductor portion (107) to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) includes a one-dimensional material whose longitudinal axis is oriented parallel to the substrate (101), and / or a two-dimensional material whose plane is oriented substantially parallel to the substrate (101). This disclosure further includes methods (3000) for manufacturing such vertical field-effect transistors and complementary logic devices.

A cell architecture is provided. A cell architecture can be provided that includes a vertical field effect transistor having at least two fins serving as vertical channels, a gate including a first gate portion surrounding a first fin, a second gate portion surrounding a second fin, and a third gate portion providing a connection therebetween, and a top source / drain including a first top source / drain portion on the first fin and a second top source / drain portion on the second fin. The cell architecture further includes a gate contact structure connected to the third gate portion, a top source / drain contact structure connected to one of the first and second top source / drain portions and serving as a horizontal conductive wiring layer, and a metal pattern on and connected to the gate contact structure and the top source / drain contact structure through vias and serving as a vertical conductive wiring layer.

A cell architecture for a vertical field effect transistor (VFET) is provided. The cell architecture includes a top source / drain (S / D) contact structure having a square shape in a top view, a horizontal metal pattern formed on the top S / D contact structure and extending in a first direction, and a vertical metal pattern sending out an output signal of a logic circuit formed by the VFET. The cell architecture also includes a gate contact structure formed on a gate connection pattern connecting gates of the VFET, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

The application belongs to the technical field of semiconductor device preparation, and relates to a metal mesh source electrode for a transistor, a transistor, a preparation method of the transistor and application of the transistor. In view of the problems of serious gate electric field shielding of a source electrode, discontinuous conductive path, difficult control of geometric morphology, and insufficient current injection uniformity and stability in the prior art, the application provides a metal mesh source electrode for a transistor, which comprises a metal conductive layer with mutually interconnected metal stripes and forming a grid gap, the stripe width of the metal stripes is 0.2-20 microns, and the duty cycle is 10-50%. The application further provides a preparation method of the metal mesh source electrode, which forms a crack template on the surface of a substrate and deposits metal, and removes the crack template to obtain a metal mesh conductive layer with controllable structure. Meanwhile, the application further provides application of the metal mesh source electrode in a vertical field effect transistor.

The invention discloses a transistor-memristor (1T1R) unit based on a graphene / molybdenum sulfide vertical transistor, and the 1T1R unit is of a full-vertical stacked structure, and sequentially comprises a substrate, a graphene / molybdenum sulfide vertical field effect transistor and a mortise and tenon structure memristor from bottom to top. The 1T1R unit has ultra-high density integration and high uniformity, the channel area of the 1T1R unit can be miniaturized to be within 10 mu m < 2 >, and the dependence on the advanced photoetching technology is effectively overcome; the resistance switching characteristic shows excellent uniformity, the variable coefficient in a high resistance state is 3.4%, the variable coefficient in a low resistance state is 6.2%, the pulse switching frequency can reach 106, and the resistance state stabilization time is gt; and 104 s, modulation of six discrete quasi-linear conductivity states can be realized through grid regulation and control of a vertical transistor.

A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor. The bottom source / drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source / drain region by a bottom spacer. A top source / drain region is located above a topmost surface of the channel fin. The top source / drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source / drain region.

Structures having vertical transport field effect transistors (FETs) with bottom source connections are described. In an example, an integrated circuit structure includes a channel structure over a substrate. The gate structure laterally surrounds the channel structure. A drain structure is over the gate structure and on the channel structure. A metal source structure is under the substrate and vertically under the channel structure. A conductive via passes through the substrate, the conductive via coupling the metal source structure to the channel structure.

This invention provides a series-connected dual-gate LIGBT device and its manufacturing method. A first dielectric oxide layer and a polysilicon electrode constitute a vertical field plate, which is distributed throughout the drift region of the second conductivity type, forming a uniform field IGBT device with a vertical field plate array. Simultaneously, a low-voltage control voltage circuit, such as a MOS, is formed at the IGBT cathode using a compatible process. Vertical field plate structures are fabricated on both sides of the low-voltage control voltage circuit using a compatible process, with the vertical field plate serving as a dielectric isolation trench for high and low voltage isolation. Taking a MOS as an example, the drain of the low-voltage MOS is shorted to the cathode of the IGBT, forming two devices connected in series, with their gates shorted, controlling both devices simultaneously with the same gate voltage. Since they are connected in series, the current of the MOS is the same as the current of the IGBT. Therefore, the current of the entire device can be limited by changing the gate voltage of the low-voltage MOS, suppressing parasitic p-n-p-n latch-up.

The application provides a vertical two-dimensional field effect device and a manufacturing method thereof. The method comprises the following steps: according to the pattern design of the vertical two-dimensional field effect device, a first forming mask and a first etching mask are arranged on the surface of a substrate and cross each other, the width of the first forming mask is equal to the thickness of a field effect tube unit, the interval of the first etching mask is equal to the length of the field effect tube unit, a first recess with a first depth is formed by first etching; the remaining parts of the lower parts of the first forming mask and the first etching mask form a vertical field effect device prototype and a tension skeleton respectively; a second recess with a second depth is formed by second etching, and a post-processing process is performed to form a source, a gate and a drain. The vertical two-dimensional field effect device obtained by the above method comprises a field effect tube with a vertical plane shape on a substrate, the upper end and the lower end of the field effect tube are respectively a source or a drain, the gate is arranged between the source and the drain, and the periphery of the final field effect tube is filled with a first insulating material.

A method of manufacturing a semiconductor device includes providing an engineered substrate. The method further includes forming an epitaxial gallium nitride (GaN) layer coupled to the engineered substrate; forming a plurality of channels in the epitaxial GaN layer; and forming a plurality of gates in the channel. The method further includes forming a plurality of sources coupled to the epitaxial gallium nitride layer; forming an interconnection structure on the grid electrode and the source electrode; forming a metal bonding layer on the interconnection structure; bonding a conductive carrier to the metal bonding layer; removing the engineered substrate; forming a drain layer on the back surface of the epitaxial gallium nitride layer; the epitaxial gallium nitride layer and at least a portion of the interconnect structure are etched to form at least one gate pad recess and expose the embedded metal trace, and at least one gate electrode is formed in the gate pad recess.

A vertical field effect transistor (200) is provided, having a drift region (204) with a first conductivity type, a semiconductor fin (206) on or above the drift region (204), and a source / drain electrode (214, 216) on or above the semiconductor fin (206), wherein the semiconductor fin (206) has an electrically conductive region (208) electrically conductively connecting the source / drain electrode (214, 216) with the drift region (204), and a confinement structure (210) laterally configured next to the electrically conductive region (208) and extending from the source / drain electrode (214, 216) to the drift region (204), wherein the confinement structure (210) is arranged for confining an electrically conductive channel of the vertical field effect transistor in the semiconductor fin (206) to a region of the electrically conductive region (208).

Methods of forming vertical field effect transistor (VFET) devices are provided. The methods can include forming an initial VFET on a substrate. The initial VFET can include a bottom source / drain region on the substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source / drain region and the patterned sacrificial layer can be surrounded by the insulating layer. The methods can also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer via the contact opening, and forming a gate electrode in the cavity.

A vertical field effect device having a body, gate dielectric, and a gate electrode, which is in a trench that extends into the body from the top surface of the body and is located between first and second source regions. The first and second regions vertically overlap the gate electrode. The first and second channel regions laterally overlap a bottom of the gate electrode, such that each channel formed in the first and second source regions have a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode. In another embodiment, the first and second channel regions also vertically overlap the gate electrode such that each channel formed in the first and second source regions also have a vertical segment where the first and second channel regions vertically overlap the gate electrode.

A microelectronic structure includes a first vertical field-effect-transistor (FET) and a second vertical FET. The first vertical FET is adjacent to the second vertical FET and the first vertical FET includes a top source / drain. A lateral extending contact that is located on top of the top source / drain and the lateral extending contact extends towards the second vertical FET. A backside contact located between the first vertical FET and the second vertical FET. The backside contact is connected to a backside surface of the lateral extending contact. The backside contact has a first critical dimension located at the backside surface of the backside contact. The backside contact has a second critical dimension located at the backside surface of the lateral extending contact. The first critical dimension is greater than the second critical dimension.

A vertical field effect transistor (VFET) device and semiconductor cell structure are provided, the VFET device including a fin structure protruding from a substrate and having an H-shape in a plan view; a gate including a fin sidewall portion formed on a sidewall of the fin structure and a field gate portion extending from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a location inside the lower half of the fin structure; a bottom epitaxial layer including a bottom source / drain (S / D) region and formed underneath the fin structure; a power supply contact landing on the bottom epitaxial layer and configured to receive a power supply signal; a top S / D region formed on top of the fin structure; and a top S / D contact landing on the top S / D region.

A vertical field effect transistor (200, 300, 400, 500, 600) is provided, having a drift region (204), a semiconductor fin (230) on or above the drift region (204), and a connection end region (212) on or above the semiconductor fin (230), a gate electrode (220) configured next to at least one sidewall of the semiconductor fin (230), wherein the semiconductor fin (230) has a smaller lateral extension in a first section (208) laterally arranged next to the gate electrode (220) than in a second section (206) contacting the drift region (204) and / or than in a third section (210) contacting the connection end region (212).

A semiconductor structure includes a first upper source / drain region, a second upper source / drain region, a first lower source / drain contact, a second lower source / drain contact, and a third conductive region. The first upper source / drain contact is disposed at a first elevation. The second upper source / drain contact is disposed at the first elevation. The first lower source / drain contact is disposed at a second elevation. The second lower source / drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source / drain contact and a projection area of the second upper source / drain contact. The third elevation is disposed between the first elevation and the second elevation.

A lateral surface gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate modulates a surface channel and the trench gate includes a controllable depth. The controllable depth may be varied to advantageously adjust output capacitance.

A vertical field effect transistor (VFET) device and a method of fabricating the same are provided. The method includes: providing an intermediate VFET structure including a substrate and, on the substrate, fin structures, gate structures, and a bottom epitaxial layer, the gate structures formed on the fin structures and the bottom epitaxial layer, respectively, each of the fin structures including a fin and a mask thereon; filling an interlayer dielectric (ILD) layer between and on sides of the gate structures; forming an ILD protection layer on the ILD layer, respectively, the ILD protection layer having an upper portion and a lower portion and including a material that prevents oxide loss at the ILD layer; removing the fin structures, the gate structures, and the ILD protection layer above the lower portion of the ILD protection layer; removing the mask of the fin structures and a top portion of the gate structures such that a top surface of the fin structures and a top surface of the gate structures after the removing are lower than a top surface of the ILD layer; forming a top spacer on the gate structures whose top portions are removed and a top epitaxial layer on the fin structures whose masks are removed; and forming a contact structure connected to the top epitaxial layer.