373 results about "Vertical field" patented technology

A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.

Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

A Head Up Display can be utilized to find light from an energy source. The Head Up Display includes a first waveguide having a first input coupler and a first output coupler. The Head Up Display can also include a second waveguide having a second input coupler and a second output coupler. The first waveguide has a first major surface and the second waveguide has a second major surface, which are disposed approximately parallel to each other. The first waveguide and the second waveguide are positioned as a combiner and allowing viewing an outside feed and information from an image source. The first input coupler diffracts light in the first field of view into the first waveguide and light in a second field of view reaches the second input coupler and is diffracted into the second waveguide.

A panoramic annular lens system (PAL), a unitary video camera and a PC-based software system that unwraps a 360° video image into a seamless, distortion free horizontal image image in real time. The PAL system of the preferred embodiment has a 360° horizontal field of view and a 90° vertical field of view in a 40 mm diameter compact package. The invention is not limited to any particular type of lens system. In fact, there are numerous lens systems for providing a 360° panoramic view. The video camera may be a CCD or CMOS based device having a pixel resolution of either 1280×1024 (high resolution) or 720×480 (NTSC). The unwrapping system is a radiometric ray tracing program carried out using a computer's graphics card capabilities to produce highly efficient regional transformation while minimizing software overhead. The result is real time, high resolution 30 fps conversion from a spherical distorted image to a flat panoramic image in Cartesian coordinates.

A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.

Pixels for a large video display which employs solid-state emitters, such as colored light emitting diodes, as light source are formed by outfitting each colored solid state emitter within the pixel with an individually tailored miniature intensity-enhancing optical system. Each of these miniature optical systems comprises a set of four wide field-of-view Lambertian reflectors 34, a pair of narrow field-of-view Lambertian reflectors 36, and a beam-shaping lens 38. The miniature intensity-enhancing optical system can be specifically designed to restrict emission in the vertical field-of-view, while providing a Lambertian intensity dependence throughout an unrestricted horizontal view. For example, the field-of-view in the vertical direction may be limited to about .+-.30.degree. while the field-of-view is about .+-.90.degree. in the horizontal direction.

A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.

Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

A mobile device-mountable camera apparatus includes a panoramic camera system and a cable-free mounting arrangement. The panoramic camera system includes a panoramic lens assembly and a sensor. The lens assembly provides a vertical field of view in a range of greater than 180° to 360°. The sensor is positioned in image-receiving relation to the lens assembly and is operable to produce image data based on an image received through the lens assembly. The mounting arrangement is configured to removably secure the panoramic camera system to an externally-accessible data port of a mobile computing device to facilitate transfer of the image data to processing circuitry of the mobile device. The mobile device's processing circuitry may produce a video image from the image data and display of the video image may be manipulated based on a change of orientation of the mobile device and/or a touch action of the device user.

A method of manufacturing a non-volatile memory array having vertical field effect transistors is revealed. First, a semiconductor substrate having multiple trenches is provided, and then dopants are implanted into the semiconductor substrate to form first doping regions and second doping regions respectively serving as source and drain bit lines at different heights. Secondly, a gate dielectric including at least one nitride film, e.g., an oxide/nitride/oxide (ONO) layer, is formed onto the surface of the semiconductor substrate, and polysilicon plugs serving as gate electrodes are filled up the multiple trenches afterward. After that, a polysilicon layer and a tungsten silicide (WiSix) layer are sequentially deposited followed by masking and etching processes to form parallel polycide lines serving as word lines, and then an oxide layer is deposited therebetween and planarized for isolation.

A display system is provided to surround a user with an out-the window scene. The system includes a screen structure that is a facetted back-projection dome made up of a polygonal polar top facet surrounded by trapezoidal facets angulated downward from it in an upper facet row. A middle row of facets extends angulated downward therefrom, and a lower row of trapezoidal facets extends down from them. Each facet has video projected thereon by a high definition projector, and to maximize resolution and efficiently use the projector output, the vertical height of each facet makes use of the full vertical field of pixels available from the associated projector. The facets are all tangent to a sphere about a design eyepoint of the dome. The projector resolutions and the size, position and material of the facets are such that the imagery visible on the inside of the dome on the facets is at resolution corresponding to a visual acuity of 20/50 or higher, preferably 20/20, and at or near eye-limiting resolution.

Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

The invention provides a building method of a knowledge map based on a vertical field. The method comprises the following steps of (1) extracting the word realization of classes of an on-line encyclopedia and the hyponymy between classes; (2) merging the field knowledge information, defining the data attribute and the relationship attribute of the field, and further setting the statute on the definition domain and the value domain of the attributes; (3) studying an entity layer, i.e., extracting an entity and filling the attribute value of the entity; performing mass processing on structurized and semi-structurized data by D2R or data collecting tools; and for non-structurized text data, defining the classes and the attributes of the upper layer body and the relationship between the classes and the attributes, and recognizing examples according to the relationship between the classes and the attributes. The method has the advantages that by using the method, the built knowledge classification of the vertical field knowledge map is clear; the self study and the automatic expansion of the knowledge map are realized; and the key effects are achieved on the information retrieval and semantic analysis of the vertical field.

A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

A bipolar junction transistor (BJT) structure and fabrication method are provided in which a doped polysilicon filled trench is utilized to form both the extrinsic base contact region and a vertical field plate. A sacrificial mandrel of dielectric material is formed over regions that will become the BJT active area. This allows the polysilicon filled trench to be extended above the original semiconductor substrate surface. In this way, the base-collector and emitter-base junctions are both self-aligned to the field plate trench. The field plate is utilized to control and shape the electric field in the base-collector depletion region, allowing heavier collector well doping for the same breakdown voltage. This results in improvement in both the breakdown/R_on ratio and the f_T*BV_cbo product.