Vertical nanotube semiconductor device structures and methods of forming the same

Abstract

Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Description

FIELD OF THE INVENTION [0001] The invention relates to semiconductor device fabrication and, more particularly, to vertical semiconductor device structures, such as field effect transistors and capacitors, incorporating nanotubes as a device element and methods of fabricating such vertical semiconductor device structures. BACKGROUND OF THE INVENTION [0002] Traditional field effect transistors (FET's) are familiar conventional devices commonly incorporated as a fundamental building block into the intricate circuitry of integrated circuit (IC) chips. A single IC chip may feature many thousands to millions of FET's, along with other passive components such as resistors and capacitors, interconnected by conductive paths. FET's operate by varying the resistivity of a channel in a channel region separating a source and a drain. Carriers flow from the source to the drain through the channel in proportion to the variation in electrical resistivity. Electrons are responsible for channel cond...

AI Technical Summary

Benefits of technology

[0008] Each semiconducting nanotube defines a channel region of a field effect transistor having a channel regulated by application of a control voltage to the gate electrode. Consistent with the principles of the invention, the length of the channel region between the source and drain is defined by the vertical dimension or thickness of the gate electrode without the limitations imposed by conventional lithographic processes used in semiconductor device fabrication to form channel regions in conventional field effect transistors.

Problems solved by technology

A small change in gate voltage can cause a large variation in the current flowing from the source to the drain.

However, these methods of forming such horizontal FET device structures are incompatible with mass production techniques.

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