Arithmetic processing device

Abstract

The purpose of the present disclosure is to provide an arithmetic processing device. An arithmetic processing device (1) provided with a network having a plurality of nodes and a plurality of processor elements as one node, the arithmetic processing device comprising: a write processing unit (12) that writes data of image information obtained by dividing and transposing inputted image information for each node into a predetermined region in a storage device (20); a change processing unit (13) that changes the correspondence between a predetermined region and a node in the storage device in accordance with the tensor shape of the image information; and a read-out processing unit (14) that reads out the data stored in the storage device to the corresponding node.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority based on Japanese patent application No. 2023-026462, filed on February 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an arithmetic processing device. Background Art

[0004] In a processing device composed of multiple nodes, where multiple processor elements (PEs) (cores) are considered a single node, image information processing, such as neural network processing, may be performed. If the input image information has a low resolution, it is processed directly. However, if the input image information has a high resolution, it may be divided and allocated to multiple nodes for processing. An example of such a method is disclosed in Patent Document 1 listed below.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. WO2011 / 059090 Summary of the Invention

[0008] Patent document 1 discloses a method for optimally scheduling segmented image information according to each node. However, the inventors conducted a detailed study and found that even if the prior art of patent document 1 is used, software developers need to pay attention to how to segment the input image information (tensor) into each node, develop different programs for each node, and load and execute the programs. Therefore, software developers must develop a system that takes into account the segmentation of tensors, and the problem of increased burden was found. In addition, if the verification process of the developed software is also included, the overall working hours will become very long, and the problem of prolonged development period was found.

[0009] An object of the present disclosure is to provide an operation processing device that performs processing without considering tensor division.

[0010] The present disclosure adopts the following technical solutions to solve the above-mentioned problems: The claims and the reference numerals in parentheses therein are examples of the correspondence relationship with the specific elements described in the embodiment described later as one aspect, and do not limit the technical scope.

[0011] According to one aspect of the present disclosure, an operation processing device includes a plurality of processor elements as a node and a network having a plurality of the nodes, wherein the device includes: a write processing unit that writes data of image information obtained by dividing the input image information according to each node and transposing it into a predetermined area in a storage device; a change processing unit that changes the correspondence between the predetermined area of ​​the storage device and the node according to the tensor shape of the image information; and a read processing unit that reads the data stored in the storage device to the corresponding node.

[0012] According to the configuration of the present disclosure, the transposition process can be executed without considering the division of tensors. Therefore, the transposition process can be executed even when the same program is executed on multiple nodes.

[0013] In one embodiment of an arithmetic processing device, for nodes other than nodes corresponding to diagonal components, the write processing unit writes the data of the image information obtained by splitting and transposing the image information assigned to the nodes into a predetermined area of ​​the storage device based on a write request from each node.

[0014] In the arithmetic processing device according to one embodiment, the write processing unit does not write data to the storage device in response to a write request from each node corresponding to a diagonal component.

[0015] The writing process can be performed as disclosed in these disclosures.

[0016] In one aspect of the arithmetic processing device, for nodes other than nodes corresponding to diagonal components, the read processing unit reads data stored in a predetermined area of ​​the storage device to the corresponding node based on a read request from each node.

[0017] In the arithmetic processing device according to one embodiment, the read processing unit does not perform reading from the storage device in response to a read request from each node for a node corresponding to a diagonal component.

[0018] The readout process can be performed as disclosed in these disclosures.

[0019] A method for controlling a processing device according to one embodiment of the present disclosure can be performed as follows. Specifically, a method for controlling a processing device includes a network having a plurality of nodes, wherein a plurality of processor elements are formed as a single node. In the method for controlling a processing device, the processing device includes a storage device and a controller for controlling the storage device, wherein the controller performs the following control operations: writing image information data obtained by dividing input image information into each node and transposing the image information; changing the correspondence between the predetermined storage device regions and the nodes based on the tensor shape of the image information; and reading data stored in the storage device to the corresponding nodes.

[0020] Effects of the Invention

[0021] By using the computational processing device disclosed herein, processing can be performed without considering tensor segmentation. Therefore, software developers can use common software for each node, reducing their development burden. Furthermore, since different software for each node is no longer necessary, the burden of verification can be reduced, and overall man-hours can be reduced, ultimately shortening the development period. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a block diagram schematically showing an example of the configuration of the arithmetic processing device.

[0023] Figure 2 This is a block diagram schematically showing an example of the hardware configuration of the arithmetic processing device.

[0024] Figure 3 This is a flowchart showing an example of the entire processing procedure of the arithmetic processing device.

[0025] Figure 4 This is a flowchart showing an example of a processing procedure of a write process of the arithmetic processing device.

[0026] Figure 5 This is a flowchart showing an example of a processing procedure of a read process of the arithmetic processing device.

[0027] Figure 6 Schematically shows the state of image information after segmentation (state of tensor segmentation).

[0028] Figure 7 This is a diagram schematically showing the correspondence between image information and nodes after tensor segmentation.

[0029] Figure 8 This is a diagram schematically showing a transposed state of image information after tensor segmentation and assigned to each node.

[0030] Figure 9 This is a diagram schematically showing an example of write processing.

[0031] Figure 10 This is a diagram schematically showing a process of changing the correspondence between nodes and banks.

[0032] Figure 11 This is a diagram schematically showing another example of the process of changing the correspondence relationship between nodes and banks.

[0033] Figure 12 This is a diagram schematically showing an example of write processing. DETAILED DESCRIPTION

[0034] exist Figure 1 An example of the configuration of each function of the arithmetic processing device 1 is schematically shown in the block diagram of FIG. Figure 2 The block diagram of FIG schematically shows an example of the hardware configuration of the operation processing device 1. The operation processing device 1 is a so-called multi-core processor in which a plurality of processor elements (processor elements) 22 (PE) (core) are regarded as one node, and each node constitutes a network. Figure 2 In the figure, two processor elements 22 (PEs) are shown at one node, but this is only shown for the sake of illustration. In reality, more processor elements 22 are assigned to one node. For example, as described in the following example, one node may have 3x3 processor elements 22 or more processor elements 22.

[0035] The storage device 20 is preferably an SRAM used as a so-called cache memory, but may also be a device having other storage functions. Furthermore, the controller 21 is a memory controller 21 that controls the storage device 20. When the storage device 20 is an SRAM, it becomes an SRAM controller 21. The memory controller 21 is loaded with a program common to all nodes and executes data writing and reading processes to and from memory banks.

[0036] The arithmetic processing device 1 includes a division processing unit 10, a transposition processing unit 11, a write processing unit 12, a change processing unit 13, and a read processing unit 14. Each process in the arithmetic processing device 1 is executed by a processing program stored in the controller 21, for example.

[0037] That is, the arithmetic processing device 1 has the aforementioned structure, and configures a shared memory controller 21 in a storage device 20 having a general storage body for multiple nodes, and changes the memory access action according to the node based on the shape (tensor shape) of the input image information (input tensor), thereby performing transposition processing even when the same program is executed on multiple nodes.

[0038] The segmentation processing unit 10 segments the image information input to the calculation processing device 1 into nodes using a predetermined method. Figure 6 Indicates the state where the image information is divided. Figure 6 In FIG, one image information is divided into four image information and the divided image information is assigned to each node from node A to node D. However, there are actually a large number of nodes. In addition, for easy understanding, Figure 6 Each number in the image information represents each area.

[0039] The segmentation processing unit 10 stores the nodes to which the segmented image information is assigned as tensor shape information in the controller 21 of the storage device 20. For example, when each region of the segmented image information is represented as a matrix, the image information is segmented into a positional relationship of a 2×2 matrix, and thus the following information is stored: the upper left region is set to (1, 1) and the image information is assigned to node A, the upper right region is set to (1, 2) and the image information is assigned to node B, the lower left region is set to (2, 1) and the image information is assigned to node C, and the lower right region is set to (2, 2) and the image information is assigned to node D. Figure 7 This is schematically shown. Furthermore, if the input image information has a high resolution and the number of image segments is large, similar processing can be achieved by increasing the number of rows and / or columns of the matrix for each region of the segmented image information. Furthermore, in addition to using a matrix to indicate to which node the segmented image information is assigned, other representation methods can be used as tensor shape information.

[0040] The transposition processing unit 11 performs transposition processing on each of the divided image information assigned to each node. Figure 8 An example of a state after transposition processing is performed on the divided image information assigned to each node is shown.

[0041] The write processing unit 12 writes the divided image information data allocated to the nodes other than the nodes corresponding to the diagonal components to the memory banks of the storage device 20 based on the write requests from the nodes. If the write is completed normally, the state of the write process is returned to success.

[0042] Furthermore, the write processing unit 12 does not actually process the write request from each node corresponding to the diagonal component (does not actually execute the write process), and returns a success status of the write process.

[0043] Figure 9 An example of the write processing by the write processing unit 12 is shown. Figure 9 In FIG, a solid arrow indicates that data is written to the storage device 20, and a dotted arrow indicates that data is not written to the storage device 20. In the storage device 20, "B" and "C" indicate that data of nodes B and C are written to the respective banks.

[0044] The change processing unit 13 performs a change process of changing the correspondence between nodes and banks based on the tensor shape of image information.

[0045] The change processing unit 13 changes the correspondence between banks and nodes for nodes other than the nodes corresponding to the diagonal components. For example, the correspondence between banks B storing the data of node B and C storing the data of node C is changed to the same relationship as that between banks B storing the data of node C and C storing the data of node B. Figure 10 This situation is schematically represented.

[0046] exist Figure 10 In the example, the image information is divided into 2 vertical and 2 horizontal areas, but when the image information is divided into 3 vertical and 3 horizontal areas, the correspondence between the nodes and the storage bodies can be changed by swapping the rows and columns of the image information of the divided areas. Figure 11 In the case of , there is a region from node A (1, 1) to node I (3, 3). For nodes other than the nodes corresponding to the diagonal components, namely, node B (region (1, 2)), node C (region (1, 3)), node D (region (2, 1)), node F (region (2, 3)), node G (region (3, 1)), and node H (region (3, 2)), the data of the image information divided into each region is stored in the corresponding memory bank. For nodes other than the nodes corresponding to the diagonal components, the positions of the regions are changed by swapping the rows and columns of the matrix. That is, by swapping node B (region (1, 2)) with node D (region (2, 1)), node C (region (1, 3)) with node G (region (3, 1)), and node F (region (2, 3)) with node H (region (3, 2)), the correspondence between the nodes and the memory banks can be changed.

[0047] For nodes other than the nodes corresponding to the diagonal components, the read processing unit 14 reads the data of the divided image information assigned to each node from the memory bank of the storage device 20 in response to the read request from each node. If the read is completed normally, the state returns to a successful read processing state.

[0048] Furthermore, the read processing unit 14 does not actually process the read request from each node (does not actually perform the read processing) for the node corresponding to the diagonal component, and returns a success status of the read processing.

[0049] Figure 12 An example of the readout processing performed by the readout processing unit 14 is shown. Figure 12 In FIG, the solid arrow indicates that the storage device 20 is being read, and the dotted arrow indicates that the storage device 20 is not being read. Furthermore, the data of the memory bank "C" in the storage device 20 is read to the node B, and the data of the memory bank "B" is read to the node C. Thus, the area of ​​node B (the area (1, 2)) reads the data of the memory bank "C", and the area of ​​node C (the area (2, 1)) reads the data of the memory bank "B".

[0050] By executing the above-described processing, a common program can be used for each node, and high-resolution image information transposition processing can be executed. Therefore, the processing can be executed without considering the division (tensor division) of the image information.

[0051] Next, use Figures 3 to 5 An example of a processing procedure in the arithmetic processing device 1 according to one embodiment of the present disclosure is described with reference to a flowchart of FIG.

[0052] When the image information to be processed is input to the processing device 1, the segmentation processing unit 10 segments the input image information for each node using a predetermined method if the image information has a high resolution (S100). Figure 6 As shown in FIG, the image information is divided into four pieces of 2×2. Then, the division processing unit 10 stores tensor shape information indicating to which node each piece of divided image information is assigned.

[0053] Then, if Figure 8 As shown, the transposition processing unit 11 performs transposition processing on each of the divided image information data assigned to each node ( S110 ).

[0054] After executing the transposition process of the divided image information assigned to each node, the write processing unit 12 executes a write process of writing the data of each divided image information into a memory bank ( S120 ).

[0055] The write processing unit 12 writes nodes other than the nodes corresponding to the diagonal components to Figure 8 The data of each image information of node B and node C in the image processing unit 12 (S200) are written to the memory bank B and the memory bank C (S210), respectively. If the writing is completed normally, the write processing is returned to the successful state (S220). Figure 8 The data of each image information of node A and node D (S200) is not actually processed for the write request from each node (the actual write process is not executed), and the success status of the write process is returned (S230). Figure 9 Indicates these processes.

[0056] After the writing process in the writing processing unit 12 is completed, Figure 10 As shown, the change processing unit 13 changes the correspondence between the nodes and the banks for nodes other than the nodes corresponding to the diagonal components (S130). Through this correspondence change processing (bank swapping processing), the correspondence between bank B storing the data of node C and bank C storing the data of node B is changed.

[0057] Then, the read processing unit 14 executes a read process for reading the data written to the memory bank at each node ( S140 ).

[0058] like Figure 12 As shown, for nodes other than the node corresponding to the diagonal component (S300), the read processing unit 14 reads data from bank C to node B, and reads data from bank B to node C (S310). If the read is successfully completed, the read processing unit 14 returns a read processing success status (S320). Furthermore, for the node corresponding to the diagonal component (S300), the read processing unit 14 does not actually process the read request from each node (does not actually perform the read processing) and returns a read processing success status (S330).

[0059] By executing the above-described processing, even when the input image information is divided, it is possible to execute the transposition processing of the image information using a program common to each node.

[0060] The arithmetic processing device 1 of the present disclosure is not limited to the scope described in this specification, and can be arbitrarily changed within the scope of the technical concept. In addition, the order of each process can also be arbitrarily changed within the scope of the technical concept.

[0061] Industrial Applicability

[0062] By using the arithmetic processing device 1, processing can be performed without considering tensor segmentation. Therefore, software developers can use common software for each node, reducing their development burden. Furthermore, since different software for each node is no longer necessary, the burden of the verification process can be reduced, and the overall man-hours can be reduced, resulting in a shorter development period.

Claims

1. An operation processing device (1), comprising a network in which a plurality of processor elements are used as a node and a plurality of the nodes are provided, wherein the operation processing device is characterized by comprising: A writing processing unit (12) writes data of image information obtained by dividing the input image information into each node and transposing the image information into a predetermined area in a storage device (20); a change processing unit (13) for changing the correspondence between the predetermined area of ​​the storage device and the node according to the tensor shape of the image information; as well as A read processing unit (14) reads the data stored in the storage device to a corresponding node.

2. The arithmetic processing device according to claim 1, wherein: For nodes other than nodes corresponding to diagonal components, the write processing unit writes the data of the divided and transposed image information allocated to the nodes into a predetermined area of ​​the storage device based on a write request from each node.

3. The arithmetic processing device according to claim 2, wherein: The write processing unit does not write data to the storage device in response to a write request from each node corresponding to a diagonal component.

4. The arithmetic processing device according to claim 3, wherein: For nodes other than the nodes corresponding to the diagonal components, the read processing unit reads data stored in a predetermined area of ​​the storage device to the corresponding node based on a read request from each node.

5. The arithmetic processing device according to claim 4, wherein: For nodes corresponding to diagonal components, the read processing unit does not perform reading from the storage device in response to a read request from each node.

6. A control method for an operation processing device (1), wherein the operation processing device includes a network having a plurality of processor elements as one node and a plurality of the nodes, wherein the control method for the operation processing device is characterized in that: The arithmetic processing device includes a storage device and a controller for controlling the storage device. The controller of the arithmetic processing device performs the following control: Writing data of image information obtained by dividing the input image information into each node and transposing the image information into a predetermined area in a storage device (20); changing the correspondence between the predetermined area of ​​the storage device and the node according to the tensor shape of the image information; as well as The data stored in the storage device is read out to the corresponding node.

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