188 results about "Workgroup" patented technology

The invention relates to the field of heterogeneous parallel computing, in particular to an attention operator head dimension block computing method applied to a sea light DCU, which comprises the following steps of: expanding a sequence length block computing range in charge of each thread block in an attention operator and a matrix computing range processed by a single thread working group; a blocking parameter splitqk and a blocking parameter splitv are selected, wherein the blocking parameter splitqk and the blocking parameter splitv are selected; selecting a proper block cutting parameter splitqk for the head dimensions of the query tensor Q and the key tensor K for cutting, accumulating block calculation results, and calculating S block calculation results through a softmax function to obtain P block calculation results; selecting a proper block cutting parameter splitv for the head dimensions of the value tensor V and the output tensor O for cutting, wherein a block calculation result corresponds to a corresponding block of the output tensor O; and finally, segmenting the tensor O according to the splitv, and writing each partitioning result back to the global memory. The method is suitable for a heterogeneous parallel computing system composed of a CPU and a DCU, computing resources of a DCU computing unit can be saved, performance loss caused by resource overflow is reduced, and computing efficiency is improved.

The invention provides a method and device for an intelligent computing center cloud platform to adjust model training parameters according to computing power operation states, and relates to the technical field of intelligent computing centers, intelligent computing centers and computing power infrastructures. The first working component is a component deployed in a node in the intelligent computing center cloud platform, the target link comprises a data preparation link, a model training link, a model evaluation link and / or a model test link in the first working component, and the target link performs data processing or model training based on preset hyper-parameters; s2, calculating target correction parameters corresponding to the operation related parameters in a preset period based on a preset regulation and control model; and S3, adjusting the preset hyper-parameter based on the target correction parameter to obtain a target hyper-parameter. The computing power utilization rate of the intelligent computing center cloud platform can be greatly improved, and then the model training efficiency is greatly improved.

The present application relates to a memory space allocation method, apparatus, computer equipment, computer-readable storage medium and computer program product. The method comprises: obtaining the execution information of the work group and the allocatable space data of the target memory; wherein the execution information at least includes the number of thread bundles of the work group and the space data of the target memory that each thread bundle needs to access; determining the number of target memory slots according to the execution information and the allocatable space data; allocating a target memory slot label to each thread bundle according to the number of target memory slots; executing the target task of the thread bundle accessing the target memory according to the target memory slot label, and releasing the storage space corresponding to the target memory according to the target memory slot label after the execution of the target task is completed. The use of this method can reduce the waste of video memory.

The embodiment of the utility model provides a wafer packaging body, a chip packaging body, a working assembly and computing equipment, the wafer packaging body is arranged on one side of a printed circuit board, the wafer packaging body comprises at least one memory module, the memory module comprises a memory wafer, a logic processing wafer and a circuit element wafer which are stacked, the circuit element wafer is a digital adjustable capacitor wafer, or the circuit element wafer is a resistor-inductor-capacitor wafer. According to the technical scheme of the embodiment of the invention, a wafer-level 3D packaging solution is provided, so that ultra-large computing power and ultra-high storage bandwidth can be realized.

The invention discloses a traffic information sharing method and device for vehicle and road cloud integration, and a medium. The method comprises the following steps: constructing a vehicle social network graph; analyzing a natural language subscription request of a user, and generating a structured decision element; a data and knowledge dual-driven collaborative decision framework is adopted to carry out multi-attribute decision, and optimal working group configuration is generated; the sensing demand parameters are encrypted and issued to all nodes in the optimal working group, sensing fusion of multi-node space-time association is achieved, and multi-source sensing data are obtained; performing standardized packaging and credibility evaluation on the acquired multi-source sensing data, and filtering untrusted data to obtain trusted data; cleaning the credible data, and performing hierarchical desensitization on sensitive information in the credible data to obtain traffic information; and pushing the traffic information to the subscribing user, and constructing an intelligent closed-loop optimization system based on user feedback to optimize the traffic information sharing service. According to the invention, the dynamic cooperative sensing capability in traffic information service can be improved.

The embodiment of the invention discloses a thread coordinate determination method and device, equipment, a storage medium and a program product, and the thread coordinate determination method comprises the steps: determining the three-dimensional size of a thread working group to which a first thread belongs, the sequence number of the first thread in a current round, and the target number of threads which can be processed in each round; determining coordinate conversion values constrained within the target number based on the three-dimensional size and the target number; determining a target conversion result between the arrangement sequence number and the coordinate conversion value from a preset lookup table; the lookup table comprises a conversion result between all values of the arrangement sequence number and all values of the coordinate conversion value; and determining a first three-dimensional coordinate of the first thread based on the target conversion result. Therefore, the determination rate of the thread coordinates is improved to the greatest extent, and the time is saved.

The embodiment of the invention relates to a network access method and device, equipment and a medium, and the method comprises the steps: obtaining a network access request of a target container group, the target container group belongs to a target working group, and the target working group comprises at least one container group with the same function of a target application program; determining a target network access strategy corresponding to the target working group; and if it is determined that a target access object corresponding to the network access request is matched with the target network access strategy, executing an access operation between a target container group corresponding to the network access request and the target access object, the target access object comprises at least one of an external network object, an interactive object of a target container group outside the container arrangement platform and an internal object of the container arrangement platform. According to the technical scheme, network access management with finer granularity and different isolation degrees in the application program is realized, the actual access requirements of different container groups can be met, and the security of network access can be guaranteed.

The invention discloses a control method and device of a heat dissipation device, a computer readable storage medium, an electronic device and a computer program product. The method comprises the steps that a current working scene matched with current running data of a display card to be cooled is determined in a preset scene library; corresponding temperature weights are set for all the working assemblies according to the current working scene, and the higher the load of the working assembly is, the higher the temperature weight of the working assembly is; determining the comprehensive temperature of the display card according to the temperature of each working component and the corresponding temperature weight; and controlling the running state of the heat dissipation device of the display card according to the comprehensive temperature to reduce the temperature of the display card. The comprehensive temperature is obtained by weighting the temperatures of all the working assemblies, so that subsequent control over the operation state of the heat dissipation device of the display card can better meet the heat dissipation requirement of the working assembly with the higher load in the current working scene, and the technical problem that the heat dissipation effect of the display card is poor in the related technology is solved; and the heat dissipation effect of the display card is improved.

Interleaving of variable bitrate streams for GPU implementations is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a super-compression encoder pipeline to provide variable width interleaved coding; and memory for storage of data, wherein the graphics processor is to perform parallel dictionary encoding on a bitstream of symbols one of multiple workgroups, the workgroup to employ a plurality of encoders to generate a plurality of token-streams of variable lengths; create a histogram including at least tokens from the plurality of token-streams for the workgroup to generate an optimized entropy code; entropy code each of the plurality of token-streams for the workgroup into an encoded bitstream; and variably interleave the encoded bitstreams to generate an interleaved bitstream and bookkeep a size of the interleaved bitstream.

A system for privacy-preserving communication and compliance enforcement is disclosed. The invention introduces Virtual Identities (VIs) and Virtual Numbers (VNs) cryptographically bound to Compliance Jurisdiction Tokens (CJTs) generated in secure enclaves. Each CJT carries session identifiers, expiry, consent artifacts, and jurisdictional codes covering GDPR (EU), CCPA (US), HIPAA, PSD2, PCI-DSS, FATF AML, the Digital Personal Data Protection Act (India), and the Personal Information Protection Law (China). Forwarding of calls, payments, or data packets is blocked unless VI–CJT validation and ledger anchoring succeed. Unlike tokenization, the system enforces real-time consent revocation, immutable regulator-verifiable audit, cross-border adequacy validation, and dual cryptographic signatures (RSA / ECC with post-quantum upgrade). Industrial use spans telecom, finance, healthcare, e-commerce, SaaS, and IoT, ensuring privacy-by-design and data protection obligations are enforced at protocol level.

Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

The invention discloses a personnel positioning method in a power enterprise factory, and the method comprises the steps: obtaining the position coordinate data of an employee, and carrying out the preprocessing of the position coordinate data of the employee; integrating the preprocessed coordinate data to obtain working group coordinate data, and obtaining a working group working area according to the working group coordinate data; obtaining timestamps of the position coordinate data of the personnel, obtaining stay time distribution according to the timestamps of the position coordinate data of the personnel, and dividing and optimizing overlapped areas of the working areas of the working groups according to the stay time distribution to obtain mergeable areas; and acquiring the real-time position of the staff position, and judging the real-time position according to the independent area and the mergeable area of the working area of the working group to obtain a real-time position judgment result so as to judge whether the staff is in the working area or not.

Quantum-based dispatch of workgroups is described. An example of an apparatus includes a computer memory to store data for processing, including data for an application; and one or more processors including a graphical processing unit (GPU), the GPU including multiple chiplets, each of the multiple chiplets including compute containers and a cache, each compute container including a plurality of processing resources, and a dispatcher for dispatching workgroups to the processing resources of the GPU, wherein dispatching workgroups includes dispatching workgroups for the application according to a selected workgroup quantum, the selected workgroup quantum having a certain size and shape.

The invention provides a synchronization signal processing method, electronic equipment and a computer readable storage medium, and the method comprises the steps: executing a first synchronization instruction by a meta thread, generating an arrival and request response signal carrying a working group slot position identifier and a barrier object identifier according to first synchronization information, and sending the arrival and request response signal to a synchronization engine; the execution engine executes the meta-thread function instruction and generates an arrival signal according to the second synchronization information; aggregating the arrival signals with the same slot position identifier and barrier object identifier to obtain a final arrival signal; the synchronization engine determines a target barrier object and updates a count value, and constructs a response signal and sends the response signal to the target meta-thread when the count value meets a preset condition. According to the technical scheme, the synchronization signal processing overhead can be reduced, and the parallel execution efficiency is improved.

A processing system (100) includes a scheduling mechanism for generating data for fine-grained reordering of work groups of kernels to generate data blocks, such as for communication across devices, to enable producer computations to overlap with communication that is fully reduced across the network. The scheduling mechanism enables the first parallel processor (702) to schedule and execute a set of work groups of producer operations to generate data for transmission in a desired traffic pattern to the second parallel processor (704). Meanwhile, the second parallel processor schedules and executes a different set of work groups of the producer operations to generate data for transmission to a third parallel processor (706) or back to the first parallel processor in a desired traffic pattern.

The invention discloses a real-time monitor for gas density and gas mixing proportion, which relates to the technical field of gas monitoring and comprises a shell, a data processing module is arranged in the shell, a working group is arranged at the top of the shell and connected with the data processing module, and a data display screen is arranged on the shell and connected with the data processing module. The shell is provided with a combined key group, a conversion key and a switch key, the combined key group is connected with the data display screen and the data processing module, the conversion key is connected with the data display screen and the data processing module, and the switch key is connected with the data display screen and the data processing module. According to the invention, a user can easily adjust the working mode of the working group through the conversion key, and single-head monitoring or double-head simultaneous monitoring is realized. Due to the multifunctionality, the instrument can adapt to different monitoring requirements and environments, and the flexibility and applicability of the instrument are improved. The device is compact in overall design and convenient to carry and transport.

The invention provides a resource allocation method, a resource allocation device, electronic equipment and a medium, and the method comprises the steps: determining whether the number of available memory logic sub-blocks in a shared memory meets the demand of a work group task or not according to the demand number of shared memory resources; under the condition that the number of available memory logic sub-blocks in the shared memory meets the requirements of the working group tasks, the corresponding memory logic sub-blocks are allocated to the working group tasks, and for each thread bundle task in the working group tasks, the corresponding thread bundle task is allocated to the corresponding thread bundle task based on the required number of universal register resources of the corresponding thread bundle task. Determining whether the number of available register logic sub-blocks in one execution unit in the plurality of execution units meets the requirement of a corresponding thread bundle task; and under the condition that the number of the available register logic sub-blocks in one execution unit in the plurality of execution units meets the requirement of the corresponding thread beam task, allocating the corresponding register logic sub-blocks in the execution unit to the corresponding thread beam task. The problem of storage space fragmentation is solved.

The invention provides a hardware switching circuit adaptive to a simulation platform, and relates to the technical field of circuits, the hardware switching circuit comprises a board-to-board connection module used for docking the simulation platform; the hardware expansion connection module is used for inserting an interface card, and the interface card is used for expanding at least one peripheral interface to be verified; the field programmable logic gate array system is used for realizing adaptation between the at least one to-be-verified peripheral interface and the simulation platform, and the simulation platform is used for verifying the at least one to-be-verified peripheral interface; the joint test working group connection module is used for realizing simulation, program burning and debugging of the field programmable gate array system; and the power supply protection module is used for providing power supply and protection for the hardware expansion connection module and the field programmable logic gate array system. According to the invention, the existing hardware resources can be reused on the simulation platform to realize verification requirements of different peripheral interfaces, the flexibility is realized, and meanwhile, the hardware development cost is reduced.

An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

A processor includes a plurality of processing elements. The processor is configured to execute a work graph including a plurality of nodes representing kernels executable by one or more processing elements of the plurality of processing elements. A first processing element of the one or more of the processing elements associated with a first node of the plurality of nodes is configured to assign each logical division of a sparse input matrix to a bin of a plurality of bins. Responsive to a dispatch condition associated with a bin of the plurality of bins, the processor is configured to dispatch a workgroup to at least a second processing element associated with at least a second node of the plurality of nodes corresponding to the bin. The workgroup includes a plurality of work items based on one or more logical divisions of the sparse input matrix assigned to the bin.

The invention provides a station-level production task generation method for a ship manufacturing workshop. The method is applied to the field of general control systems, and comprises the following steps: extracting process characteristic parameters in structured model data; obtaining real-time data of a workshop, and calculating a processing load value corresponding to each process characteristic parameter according to the real-time data of the workshop; setting a capacity adaptive threshold value, and matching a corresponding station type and a working group based on a comparison result of the processing load value and the capacity adaptive threshold value; according to the process adaptation range of the station type and the operation capability of the working group, dividing production batches and distributing station resources, and generating an initial station-level production task; and acquiring execution data of the initial station-level production task in real time, calculating a task execution deviation rate based on the execution data, dynamically adjusting a productivity adaptive threshold value or resource allocation of production batches according to the task execution deviation rate, and outputting the optimized station-level production task. Therefore, the production task generation efficiency is improved.

The utility model discloses a machine room, and relates to the technical field of machine rooms, the machine room comprises an outer shell, an inner shell, a working assembly, a cooling assembly and a movable assembly, the outer shell is provided with a ventilation opening; the inner shell is arranged in the outer shell, and the inner shell is made of a high-thermal-conductivity material; the working assembly is arranged in the inner shell; the cooling assembly is arranged in the inner shell and used for cooling air in the inner shell. The movable assembly is movably connected with the outer shell and can move relative to the outer shell to open or close the ventilation opening. According to the technical scheme, the problems that an existing machine room is high in cost, large in size and difficult to maintain and manage due to the fact that complex or expensive equipment is input for cooling can be solved.

The present disclosure provides an instruction scheduling method and apparatus, an electronic device, and a medium. The method includes: obtaining a target instruction through a first instruction scheduling unit; identifying a target unit for executing the target instruction, where the target unit is one of an execution unit or a first functional unit; in the case where the target unit is the first functional unit, determining a target tensor block corresponding to the target instruction and a target workgroup corresponding to the target tensor block, where the target workgroup is used to indicate the memory address range of the target tensor block; scheduling the target instruction to the target workgroup through the first instruction scheduling unit, and scheduling the target workgroup to the target unit, so that the target unit reads the target tensor block based on the memory address range and executes the target instruction on the target tensor block. Based on the instruction scheduling method of the present disclosure, the adaptability between the hardware layer and block-based GPU programming languages such as Triton can be improved.

The invention provides a computing chip, a reduction operation method, a related device and a medium, and the computing chip comprises a plurality of computing units which are used for executing a computing task containing a thread bundle and a working group, and each computing unit comprises a loading storage unit and a local shared memory; the data caching unit is used for caching the work group level reduction results from the plurality of computing units and executing a reduction operation across work groups; the global memory is used for storing a grid-level reduction result after the reduction operation of the data cache unit; wherein a first-level hardware reduction module is integrated in the loading storage unit, and is used for executing a thread bundle and reduction operation in a working group, and submitting an obtained working group reduction result to a local shared memory; and a second-stage hardware reduction module is integrated in the data cache unit, is coupled with the first-stage hardware reduction module and is used for executing reduction operation across working groups. According to the method, the memory access delay and the calling overhead are reduced, and the execution efficiency of the grid reduction operation is improved.

A method for compressing work item coordinate data for work items in a work group and sending the data across an interface between a computation requesting unit and a computation sequencing unit. A work item valid mask is created in dependence on the number and positions of work items in the work group, the work item valid mask indicating valid work items in the work group. A first swizzle mask indicates which bits of a swizzle index for each work item in the work group correspond to the value of a first coordinate for that work item. A second swizzle mask indicates which bits of the swizzle index for each work item in the work group correspond to the value of a second coordinate for that work item.

The embodiment of the invention provides a scheduling method of a working group, a graphics processor and electronic equipment, the scheduling method of the working group is applied to an arbitration module of the graphics processor, the graphics processor further comprises at least two execution modules, and the scheduling method comprises the following steps: aiming at each execution module, executing the execution modules; determining a first score of the execution module based on the resource request of the working group and the residual resource information of the execution module; under the condition that the first score of each execution module is smaller than a first score threshold value, a target execution module is determined from the at least two execution modules based on the first waiting duration of each execution module, and the first waiting duration of the execution module is the duration needed by the prediction execution module to release the target resource information; the target resource information is determined based on the resource request of the working group and the residual resource information of the execution module; and scheduling the working group to the target execution module.

The application relates to an unmanned aerial vehicle (UAV) intelligent fault detection system and method for inspection, which comprises an UAV fault monitoring server, a communication network, ground fault detection terminals and random fault detection terminals. Each ground fault detection terminal forms a detection work group with at least one random fault detection terminal. The random fault detection terminals are connected with the ground fault detection terminals in the same detection work group through the communication network. The ground fault detection terminals are connected with the UAV fault monitoring server through the communication network. The detection method comprises three steps of system configuration, dynamic detection and ground detection. The application can effectively meet the needs of fault detection and troubleshooting of UAVs with different structures, and can effectively realize the cooperation of synchronous detection in the UAV operation process and ground static detection, so that the flexibility and convenience of UAV detection operation are greatly improved.