1717results about "Machine execution arrangements" patented technology

The invention relates to the technical field of virtualization management, in particular to a virtual machine operation management system based on RISC-V. The system comprises an instruction set mapping module, a resource scheduling optimization module, a virtual machine monitoring integration module, an operation tuning update module and an operation configuration distribution module. According to the method, by analyzing the operation instruction of the virtual machine and combining the RISC-V underlying characteristics, accurate instruction mapping is achieved, the processing efficiency and accuracy are remarkably improved, the performance loss and conversion delay caused by too high abstraction level of a traditional virtual machine on the instruction level are overcome, the optimal allocation scheme is screened, the resource utilization rate and the system response speed are effectively improved, and the system performance is improved. The operation state and performance indexes of the virtual machine are integrated, anomaly detection and resource recovery are embedded, system stability and effective resource reutilization are ensured, basic configuration is continuously and incrementally updated, operation configuration refinement and automatic management and updating are achieved, the overall operation efficiency and management flexibility are improved, and the manual intervention cost is reduced.

The invention discloses a zoom factor processing module, a processor and electronic equipment. The scaling factor processing module comprises: an index extraction unit configured to receive a target tensor and determine an index portion of a target scaling factor corresponding to the target tensor; the multi-scale processing unit is configured to determine a plurality of candidate scaling factors according to the exponential part of the target scaling factor; the first processing unit is configured to execute quantization operation and inverse quantization operation respectively based on the multiple candidate scaling factors and the target tensor, and determine inverse quantization results corresponding to the multiple candidate scaling factors respectively; and the second processing unit is configured to select a target candidate scaling factor as a target scaling factor corresponding to the target tensor according to the inverse quantization results corresponding to the plurality of candidate scaling factors. According to the scaling factor processing module provided by the invention, precise quantization can be efficiently realized on hardware, and the quantization precision is improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes such as financial science and technology and medical health, and discloses an anomaly analysis method, device and equipment based on multi-agent collaboration and a medium. The method comprises the following steps: generating fusion data through processing of a data fusion agent, extracting abnormal feature information through a data analysis agent, generating an abnormal analysis result and a decision instruction through a decision agent, collecting decision feedback through a feedback optimization agent, and analyzing and generating an optimization instruction for optimizing the data analysis agent and the decision agent. According to the method, closed-loop processing of data acquisition, fusion, analysis, decision and feedback optimization is realized through cooperation of multiple agents, so that multi-source heterogeneous data is efficiently integrated and deeply analyzed, the accuracy and adaptability of analysis and decision are continuously improved in combination with feedback optimization, and the timeliness and reliability of anomaly recognition and response are improved.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of data center operation and maintenance, financial science and technology, medical treatment and health and the like, and discloses a task processing method and device based on a domain knowledge base, equipment and a medium. Cleaning and formatting to generate standardized task list data, inputting the standardized task list data and a domain knowledge base into a language model to generate structured task list data, and matching task list types based on the structured task list data to generate a task list execution plan, and determining an execution mode according to the task list execution plan and executing to generate a task list execution state. Through cooperative processing of the domain knowledge base and the language model, standardized and structured processing of task list data is realized, and in combination with task type matching and execution mode control, processing automation and accuracy are improved, manual participation is reduced, and response speed and efficiency are improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of financial science and technology, medical health and the like, and discloses a multi-modal information analysis and scheme reminding method, device, equipment and medium, which comprises the steps of receiving input data and converting the input data into multi-modal data, executing optical character recognition and image classification recognition to generate a recognition result, and sending the recognition result to a server; a natural language processing model is used for analyzing fuzzy description to generate an analysis result, a knowledge base is inquired, a knowledge graph is combined to generate an association result, the analysis result, the association result and user feature data are fused to generate an execution scheme, the execution scheme is compared with an abnormal list, supervision confirmation is triggered, and a compliance instruction is generated. And personalized reminding contents are generated. The information analysis integrity is improved through multi-modal recognition, natural language processing and the knowledge graph, supervision confirmation and personalized reminding are introduced, and intelligent, compliant and reliable reminding management is achieved.

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. Determining a first jump step length required for rearranging the block data based on the block size of the input data in the first dimension; secondly, performing jump reading on the block data according to a first jump step length, rearranging and loading read input elements into a thread private register so as to realize transposition storage of the block data in the thread private register, and mapping a thread direction on a second dimension so as to obtain a data basis of convolution correlation calculation; convolution correlation calculation is executed based on the transposed data in the thread private register and the weight data in the thread private register, repeated data reading in the calculation process is reduced during sliding window calculation, and an operator is converted into calculation performance bottleneck operation from memory access performance bottleneck operation.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared local memory coupled with the plurality of processing elements, a plurality of matrix engines coupled with the distributed shared local memory, and an asynchronous matrix multiply accumulate (MMA) controller configured to perform an asynchronous MMA operation via the plurality of matrix engines.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The embodiment of the invention provides a data processing method and device for large model parameters, equipment and a medium, and belongs to the technical field of artificial intelligence. The method comprises the following steps: obtaining a quantization matrix and a meta-parameter of a target large model from different partitions of a first data storage area of a memory, reading memory access granularity representing the data processing capability of a processor, and determining the size of a filling area between the insertion meta-parameter and the quantization matrix based on the memory access granularity; dividing a second data storage area different from the first data storage area in the memory, and sequentially writing the meta-parameter, preset filling information matched with the filling area in size and the quantization matrix into the second data storage area to obtain an initial data atomic block; and continuously arranging all the initial data atomic blocks in the second data storage area to obtain a target data atomic block. By optimizing the data storage mode, the memory bandwidth utilization rate of the processor in the reasoning process is improved, and then the data calculation efficiency of the processor is improved.

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The embodiment of the invention relates to a data prefetching training method and device, a data prefetching method and device, electronic equipment and a medium. The data prefetching training method comprises the steps of obtaining a plurality of memory access features of an access request, the access request being used for accessing data in a memory access address; searching a historical access record, and determining at least one target access record corresponding to a target feature in the plurality of memory access features, the target feature being a feature existing in the historical access record in the plurality of memory access features; based on the at least one target access record, determining at least one offset of the target feature, each offset indicating an offset address of the data address of the prefetched data relative to the memory access address; and updating the prefetch offset record based on the at least one offset. According to the method, memory access rules under various conditions can be learned, and the accuracy and coverage rate of prefetching are improved.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a processing circuit with multiple compute circuits for executing wavefronts of a parallel data application. Each compute circuit includes a local memory subsystem for accessing data not found in vector register files of the compute circuit. The local memory subsystem includes a first execution pipeline and a second execution pipeline. The second execution pipeline processes vector stack access instructions that access temporary data such as stack data of a function call used by each wavefront that is generated based on the function call. The first execution pipeline processes other types of vector memory access instructions and includes multiple complex pipeline stages not found in the second execution pipeline. Thus, the second execution pipeline has a latency less than the latency of the first execution pipeline.

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

The embodiment disclosed by the application belongs to the technical field of computing, and particularly relates to a method and device for performing stencil calculation and a computing device. The method comprises the following steps: acquiring a plurality of node data included in a calculation region, and grouping the plurality of node data into a data vector. According to at least one calculation condition included in the stencil calculation, the plurality of node data are subjected to judgment processing, and a judgment result corresponding to each calculation condition is obtained for each node data. For each calculation condition, the judgment result corresponding to the calculation condition is grouped into a judgment result vector, and the judgment result vector is obtained. Based on the data vector and the judgment result vector corresponding to each calculation condition, a calculation operation corresponding to each calculation condition in the stencil calculation is performed, and a calculation result of the stencil calculation is obtained. The application can convert the stencil calculation into vector calculation, and can improve the efficiency of the stencil calculation.

The invention relates to the technical field of AI chips, in particular to a calculation method of an AI chip based on RISC-V CPU Core and the chip. The AI chip comprises a scheduling core and a plurality of computing cores based on an RISC-V instruction set architecture, and the method comprises the following steps: the scheduling core analyzes an AI task to determine one or more computing operation types required by the AI task, and selects one or more computing cores capable of executing the computing operation types from the plurality of computing cores according to the computing operation types; the scheduling core allocates the AI task to a calculation core corresponding to the calculation operation type, and activates the calculation core; and the calculation cores obtain respective kernel codes and required calculation data so as to execute respective calculation tasks. It can be understood that according to the technical scheme, the scheduling core and the computing core are both based on the RISC-V instruction set architecture, the ecological barrier problem is solved, flexible iteration of the architecture and optimal configuration of computing resources are achieved, and the method has the beneficial effects of ecological openness, high flexibility, remarkable cost effectiveness and the like.

Techniques for memory tagging based on data transformations in a computing system are described. In certain examples, a computing system includes a memory; an execution circuitry to execute an instruction to generate a memory request, comprising a location and a first tag, to read a data line from the memory; and a memory controller circuit to: retrieve data at the location from the memory request, unmask the data using the first tag from the memory request to generate first unmasked data, unmask the data using a second set of one or more tags to generate a corresponding second set of unmasked data, determine that the first unmasked data is random data, determine that the corresponding second set of unmasked data is random data, and send the first unmasked data for the memory request in response to the first unmasked data being the random data, and the corresponding second set of unmasked data being the random data.

Systems and methods related to vector mask buffers in a vector instruction execution pipeline are disclosed herein. The vector instruction execution pipeline may include several lanes. Each lane may include a vector register file, a vector mask buffer, and a functional processing unit. The vector register file may store operand data and the vector mask buffer may store a vector mask associated with the operand data. In a lane, the operand data may be read from the register file into a functional processing unit, and the vector mask may be read from the vector mask buffer to the functional processing unit. The functional processing unit may process the operand data based on the vector mask. The lane-specific vector mask buffers improve the efficiency of the vector instruction execution pipeline by storing the vector masks proximate to where the vector masks will be used.

The invention relates to the technical field of artificial intelligence, in particular to an operation method and an arithmetic unit based on a Point data format.The method comprises the steps that sign bits, exponential expansion bits, mantissa bits and exponential bits of the Point data format are obtained, all the positions of the Point data format are preprocessed, a bit width distribution priority rule is defined, and a bit width distribution priority rule is obtained; multiplying the two mantissa bits obtained by decoding to obtain a mantissa product and a mask sequence; determining a prepositive zero number of the mantissa product according to the mask sequence, and performing unified logic shift on the mantissa product; the method comprises the following steps: carrying out shift on a mantissa part, carrying out rounding operation on the shifted mantissa part, converting a mantissa product into a fixed-point number format according to a sign bit, an exponential expansion bit and an exponential bit, carrying out additive operation based on the fixed-point number, and outputting an accumulation result. The circuit area and power consumption are reduced, complex time sequence control is not needed, and logic resource consumption is reduced.

The invention relates to a method for calculating matrix multiplication, an artificial intelligence chip, a calculation device, a medium and a program product. The method comprises the following steps of: accumulating a calculation result of a current cycle calculation and a calculation result of a previous cycle calculation of matrix multiplication executed in a thread bundle group granularity by utilizing a buffer which is configured in a calculation core and is used for accumulation operation; determining whether the last cycle calculation of the matrix multiplication performed at the thread bundle group granularity is completed; and in response to determining that the last cycle computation of the matrix multiplication performed at the thread bundle group granularity is completed, writing the computation results accumulated via the buffer to the register file. According to the invention, the write bandwidth of the register and the occupation of the register space can be obviously reduced.

The embodiment of the invention discloses a data processing device, a chip product, computer equipment and a data processing method. The data processing device comprises an instruction decoding module, a data moving module and a plurality of calculation units; wherein the instruction decoding module is used for receiving a calculation instruction based on open source instruction set architecture RISC-V extension; the data moving module is used for responding to the calculation instruction and determining a prediction configuration parameter to be used by a target calculation unit corresponding to the calculation instruction; the calculation unit is used for utilizing a target calculation unit corresponding to the calculation instruction to obtain configuration parameters to be used by the target calculation unit when the calculation instruction is executed; and if the configuration parameter hits the predicted configuration parameter, performing unit configuration by using the predicted configuration parameter so as to perform data operation processing.

The invention provides a processor supporting data multiplexing and instruction multiplexing, which is used for supporting multiplexing of operands and instructions of a previous calculation task in a later-executed calculation task, and realizes operand multiplexing and instruction multiplexing based on configuration information stored by a host control module connected with the processor. The processor comprises a configuration information caching module used for storing a storage offset and a storage offset use mark which are acquired from configuration information and correspond to each instruction in each calculation task; the base address dynamic generation module is used for storing a data cache index address of each calculation task and generating a real base address of each instruction in each calculation task; and the calculation module is used for acquiring an operand to execute each calculation task based on the real base address of each instruction in each calculation task generated by the base address dynamic generation module.

Various embodiments include techniques for performing memory synchronization operations between processors in a multiprocessor computing system. A first processor transfers data by issuing memory operations to store the data to a shared memory. The first processor issues an asynchronous release operation to a load store unit. In response, the load store unit issues a memory synchronization operation to ensure that the data associated with the memory operations is visible in the shared memory. While the asynchronous release operation is pending, the first processor is able to issue further instructions and perform other operations. When the data associated with the memory operations is visible in the shared memory, the memory synchronization operation completes and the load store unit writes a flag to a separate memory location. Upon detecting that the flag has been written, a second thread, and / or other threads, can reliably read the data stored in the shared memory.

There is provided an apparatus, a method, and a computer program. The apparatus is provided with instruction decoding circuitry to decode instructions and processing circuitry to perform a processing operation in response to a decoded instruction. In response to an authentication code generating instruction, the processing circuitry is configured to generate an authentication code associated with an 10 authentication target value. For at least one type of the authentication code generating instruction, the processing circuitry is configured to generate an authentication code, when operating in a first code generation mode, by applying a code generating function to: a key; the authentication target value; a first modifier dependent on a stack pointer, and / or a second modifier dependent on a program counter address; and a further 15 modifier dependent on a further value obtained from an architecturally visible register different from the stack pointer register and the program counter register.

The invention discloses a processing device, an instruction processing method, a chip device and electronic equipment, and belongs to the technical field of electronics. The processing device comprises a physical register file, a physical register cache unit and an execution unit, the physical register file comprises a first read port and a first number of physical registers, the physical register cache unit comprises a second read port and a second number of cache lines used for caching data of the second number of physical registers, and the second number is smaller than the first number; the execution unit is used for responding to all the source data of the first instruction and executing the first instruction based on all the source data of the first instruction, and any source data in all the source data of the first instruction is read from the first number of physical registers through the first read port or read from the second number of cache lines through the second read port. The instruction execution efficiency can be improved on the basis that the occupied area is not greatly increased, and the instruction processing performance of the processing device is improved.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

Some embodiments provide techniques for detecting presence of malicious software in a computing asset. The techniques identify, from among a plurality of memory locations allocated for use by a process managed by an operating system (OS) associated with the computing asset, memory location(s) to monitor in furtherance of detecting presence of malicious software in the computing asset, monitor threads initialized by the process using the identified memory location(s) to determine a number of threads so initialized, identify value(s) for visibility characteristic(s) of the process indicative of whether the process is attempting to evade detection of its execution on the computing asset, and determine whether the process is a malicious software process based on the number of threads and the value(s) for the visibility characteristic(s).

Aspects for forward propagation of a convolutional artificial neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute a convolution kernel with one of the one or more portions of the input data to generate a slave output value. Further still, the aspects may include an interconnection unit configured to combine the one or more slave output values into one or more intermediate result vectors, wherein the master computation module is further configured to merge the one or more intermediate result vectors into a merged intermediate vector.

The invention provides a loading storage circuit and a graphics processor, and relates to the technical field of graphics processing. The loading storage circuit comprises an instruction scheduling module, an address generation module and a data service module, and is provided with a buffer area module which comprises an operand buffer area and an effective data buffer area and is used for caching information required by address calculation and data access; the instruction scheduling module is used for collecting a data access instruction and outputting instruction information; the address generation module calculates a target access address according to the instruction information and the operand; and the data service module executes corresponding data loading or storage operation on the target cache unit. According to the scheme, the operands and the valid data are pre-cached, so that overflow and stagnation caused by inconsistent processing rhythms among modules can be avoided, and the parallel processing capability of an assembly line is improved; through the independent address calculation and data access process, the stability of the access time sequence and the data processing efficiency can be improved.