3504results about "Machine execution arrangements" patented technology

An online system trains a transformer architecture by an initialization method which allows the transformer architecture to be trained without normalization layers of learning rate warmup, resulting in significant improvements in computational efficiency for transformer architectures. Specifically, an attention block included in an encoder or a decoder of the transformer architecture generates the set of attention representations by applying a key matrix to the input key, a query matrix to the input query, a value matrix to the input value to generate an output, and applying an output matrix to the output to generate the set of attention representations. The initialization method may be performed by scaling the parameters of the value matrix and the output matrix with a factor that is inverse to a number of the set of encoders or a number of the set of decoders.

The invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization, which comprises the following steps of: when an executable file is executed in a dynamic instruction conversion mode, acquiring an address memory access mode of a prefetch instruction of x86 architecture, and analyzing an operand and an offset calculation mode of the prefetch instruction; according to an address memory access mode, an operand and an offset calculation mode, an instruction or an instruction sequence of an ARM architecture capable of completing memory address calculation and a prefetching function is constructed, a prefetching instruction of an x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete instruction dynamic conversion, and conversion of the prefetching instruction of a complex address mode under the x86 architecture is achieved. And the execution reliability of the executable file in the dynamic instruction conversion mode is improved.

An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

At least some embodiments of the present disclosure are related to methods and systems for evaluating, generating, and / or prototyping data pipelines. In certain embodiments, a system is configured to perform operations include: receiving an input dataset, the input dataset including a data schema; generating a first prompt based on the input dataset and a first prompt structure having one or more text strings and one or more blanks; providing the first prompt to a language model; receiving a use case generated by the language model for the input dataset, the use case including a description of how to use the input dataset; generating a data pipeline based on the use case; and applying the data pipeline to the input dataset to generate an output dataset.

The invention discloses a data processing system and method, electronic equipment and a storage medium, and relates to the technical field of computers.Original input data are preprocessed into multiple sets of target input data through a data input module, and the multiple sets of target input data are input into multiple iterative calculation units to obtain data to be calculated and code identifiers; when the code identifier represents that the to-be-calculated data needs to be overturned in advance, the to-be-calculated data is overturned in advance to obtain the to-be-calculated inverted data, and a subsequent iterative calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result; that is, the iterative calculation unit can obtain the data processing result only by performing a small amount of data bit flipping on the to-be-calculated inverted data through the target calculation, the number of data bit flipping in the target calculation is reduced, the dynamic flipping power consumption is reduced, and compared with a power consumption reduction mode in the related technology, the efficiency is improved. High-difficulty chip rear end layout wiring is not needed, and the performance and the power consumption reduction effect of the chip can be ensured.

A computer-implemented method includes receiving a neural network model that includes memory load operations and a plurality of computation operations, selecting a memory load operation having an arithmetic intensity factor (AIF) greater than a threshold value from the memory load operations, grouping computation operations associated with data loaded by the selected memory load operation into two or more clusters of computation operations, and incorporating an instance of the selected memory load operation before each cluster of the two or more clusters of computation operations in the neural network model.

The invention relates to the technical field of virtualization management, in particular to a virtual machine operation management system based on RISC-V. The system comprises an instruction set mapping module, a resource scheduling optimization module, a virtual machine monitoring integration module, an operation tuning update module and an operation configuration distribution module. According to the method, by analyzing the operation instruction of the virtual machine and combining the RISC-V underlying characteristics, accurate instruction mapping is achieved, the processing efficiency and accuracy are remarkably improved, the performance loss and conversion delay caused by too high abstraction level of a traditional virtual machine on the instruction level are overcome, the optimal allocation scheme is screened, the resource utilization rate and the system response speed are effectively improved, and the system performance is improved. The operation state and performance indexes of the virtual machine are integrated, anomaly detection and resource recovery are embedded, system stability and effective resource reutilization are ensured, basic configuration is continuously and incrementally updated, operation configuration refinement and automatic management and updating are achieved, the overall operation efficiency and management flexibility are improved, and the manual intervention cost is reduced.

Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

The invention discloses a neural network extension execution computer system based on RISC-V. The neural network extension execution computer system comprises an RISC-V processor based on an out-of-order execution system structure, a neural network hardware accelerator, an instruction memory, a data memory and a dynamic scheduler. The dynamic scheduler is used for switching different working modes for the computer system according to the current calculation load, and distributing a calculation task to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes comprise a standard calculation mode, a neural network acceleration mode and a low power consumption mode; the computing tasks comprise a general computing task and a neural network computing task. According to the technical scheme, the intelligence of the computer system is improved, and the calculation efficiency, the resource consumption and the power consumption are well balanced.

The embodiment of the invention provides a matrix and vector operation device based on an RISC-V extension instruction, the device comprises a coprocessor and a main processor which are connected with each other, an RISC-V instruction set and a coprocessor extension instruction set are configured in the main processor, the RISC-V instruction set comprises a vector extension instruction set related to a vector operation task, and the coprocessor extension instruction set comprises a coprocessor extension instruction set related to the vector operation task. The coprocessor extension instruction set comprises a matrix processing instruction set related to a matrix operation task, and the main processor is configured to send the matrix processing instruction set related to the matrix operation task or a vector extension instruction set related to a vector operation task to the coprocessor when a calculation task is executed, the computing task is executed in parallel with the coprocessor; the coprocessor is configured to execute a matrix operation task unloaded by the main processor according to the matrix extension instruction set to obtain an execution result of the matrix operation task; or executing the vector operation task unloaded by the main processor according to the vector extension instruction set to obtain an execution result of the vector operation task.

Described herein is a generic hardware / software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

Cost-effective storage management including identifying, by a remote storage consumer, one or more of portions of one or more source objects stored at a remote storage resources; issuing, by the remote storage consumer, a command to the remote storage resources configured to cause the remote storage resources to create a new object comprising the one or more of portions of the one or more source objects; and updating, at the remote storage consumer, a mapping data structure to reference the new object.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a thread mode of a client program when an indirect jump instruction in the client program is translated; generating a target search code sequence according to the thread mode; wherein different thread modes correspond to different target search code sequences; the target search code sequence is used for searching a target jump table based on a jump target address of the indirect jump instruction to obtain a cache initial address of a translated basic block corresponding to the jump target address; and if the target search code sequence is successfully searched, skipping to a cache initial address of the translated basic block corresponding to the skipping target address. According to the embodiment of the invention, the translation of the indirect jump instruction can be optimized, and the efficiency of searching the indirect jump table is improved, so that the running efficiency of a translated program is improved.

The invention discloses a zoom factor processing module, a processor and electronic equipment. The scaling factor processing module comprises: an index extraction unit configured to receive a target tensor and determine an index portion of a target scaling factor corresponding to the target tensor; the multi-scale processing unit is configured to determine a plurality of candidate scaling factors according to the exponential part of the target scaling factor; the first processing unit is configured to execute quantization operation and inverse quantization operation respectively based on the multiple candidate scaling factors and the target tensor, and determine inverse quantization results corresponding to the multiple candidate scaling factors respectively; and the second processing unit is configured to select a target candidate scaling factor as a target scaling factor corresponding to the target tensor according to the inverse quantization results corresponding to the plurality of candidate scaling factors. According to the scaling factor processing module provided by the invention, precise quantization can be efficiently realized on hardware, and the quantization precision is improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes such as financial science and technology and medical health, and discloses an anomaly analysis method, device and equipment based on multi-agent collaboration and a medium. The method comprises the following steps: generating fusion data through processing of a data fusion agent, extracting abnormal feature information through a data analysis agent, generating an abnormal analysis result and a decision instruction through a decision agent, collecting decision feedback through a feedback optimization agent, and analyzing and generating an optimization instruction for optimizing the data analysis agent and the decision agent. According to the method, closed-loop processing of data acquisition, fusion, analysis, decision and feedback optimization is realized through cooperation of multiple agents, so that multi-source heterogeneous data is efficiently integrated and deeply analyzed, the accuracy and adaptability of analysis and decision are continuously improved in combination with feedback optimization, and the timeliness and reliability of anomaly recognition and response are improved.

Methods, apparatus, and processor-readable storage media for predicting task execution efforts using artificial intelligence techniques are provided herein. An example computer-implemented method includes determining intent information associated with at least a portion of a task by processing data related to the task using at least a first set of artificial intelligence techniques; determining task execution workflow data based at least in part on the intent information associated with at least a portion of the task; predicting one or more efforts associated with executing the task by processing at least a portion of the task execution workflow data using at least a second set of artificial intelligence techniques; and performing one or more automated actions based at least in part on at least one of the one or more predicted efforts associated with executing the task.

Improved placement of memory and functional modules, ‘tiles’, within a tiled processor architecture are disclosed for linear algebra calculations involving vectors and matrices comprising large amounts of data. The improved placement places the data in close proximity to the functional modules performing calculations using the data. These modules enable these calculations to be performed more quickly while using less energy. These modules, in particular, improve the efficiency of the training and application of deep learning and artificial neural network systems. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention discloses a queue management method of a storage device, an electronic device and a storage medium, and relates to the technical field of data processing. When the storage device is configured, a host only needs to send an instruction containing a batch operation type and a queue parameter storage address; triggering the storage device to obtain queue parameter information of a plurality of input and output queues in batches from a specified address, and completing creation or deletion operation of all the input and output queues at one time; according to the method and the device, a plurality of commands which need to be issued one by one originally are simplified into single interaction, so that the communication times and data transmission redundancy between the host and the storage equipment are greatly reduced, the occupation of link bandwidth is reduced, the time of an initialization or reset process is remarkably shortened, and the data transmission efficiency is greatly improved especially in a scene with a relatively large number of queues. The problems of heavy interaction burden, low link efficiency, long processing delay and reset overtime risk in the prior art are effectively solved, and the technical effects of simplifying the interaction frequency and improving the configuration efficiency are achieved.

The invention is suitable for the technical field of processors, and particularly relates to a vector configuration instruction implementation method and system and a storage medium. The implementation system comprises an instruction fetching unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit. The vector configuration instruction execution unit is used for obtaining the number of the idle register, renaming the received vector configuration instruction according to the number of the idle register to obtain a renamed vector configuration instruction and renaming information, and executing the renamed vector configuration instruction to obtain the renamed vector configuration instruction. And generating vector configuration information according to the execution result and sending the vector configuration information to a vector execution unit. Compared with the prior art, the vector configuration instruction is realized by introducing a register renaming technology, and simple and quick recovery can be carried out when speculative execution errors occur while the speculative execution capability is reserved, so that the design complexity can be reduced and the execution efficiency of the instruction can be improved while the performance is considered.

The invention relates to the technical field of microprocessor structures, and discloses a protocol calculation method, an engine, computer equipment, a storage medium and a program product.The protocol calculation engine comprises an instruction receiving module used for receiving a protocol instruction sent by a core; the instruction splitting module is used for splitting the protocol instruction into a read request and a write request; the read request processing module is used for reading an operand corresponding to the read request from the draft book storage module; and the write request processing module is used for executing protocol calculation on the operand according to the protocol instruction to obtain a calculation result, and writing the calculation result into a draft book for storage. The protocol calculation engine specially used for protocol calculation is designed, and the protocol calculation instruction is executed asynchronously, so that compared with a traditional VPU form, the occupied chip area is small, the calculation efficiency is high, judgment is completed through answer words, and programming is convenient.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of data center operation and maintenance, financial science and technology, medical treatment and health and the like, and discloses a task processing method and device based on a domain knowledge base, equipment and a medium. Cleaning and formatting to generate standardized task list data, inputting the standardized task list data and a domain knowledge base into a language model to generate structured task list data, and matching task list types based on the structured task list data to generate a task list execution plan, and determining an execution mode according to the task list execution plan and executing to generate a task list execution state. Through cooperative processing of the domain knowledge base and the language model, standardized and structured processing of task list data is realized, and in combination with task type matching and execution mode control, processing automation and accuracy are improved, manual participation is reduced, and response speed and efficiency are improved.

The embodiment of the invention provides an instruction processing method and device, a processor, a medium, a program and computer equipment. The method on the processor side comprises the steps that an instruction of an application program is obtained; judging whether the instruction is a support instruction of a processor or not; if the instruction is a non-supporting instruction of the processor, determining the type of the instruction in the non-supporting instruction; if the instruction is an extension instruction in a non-support instruction, decoding the instruction to obtain decoding information of the instruction, and storing the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction which can be decoded and identified by the processor but cannot be executed; and on the basis that the instruction is a non-support instruction of the processor, triggering an illegal instruction exception, so that an exception handling function corresponding to the illegal instruction exception performs software simulation execution on the basis of decoded decoding information of the extended instruction. According to the embodiment of the invention, the non-support instruction can be efficiently processed, and the hardware cost is controlled.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of financial science and technology, medical health and the like, and discloses a multi-modal information analysis and scheme reminding method, device, equipment and medium, which comprises the steps of receiving input data and converting the input data into multi-modal data, executing optical character recognition and image classification recognition to generate a recognition result, and sending the recognition result to a server; a natural language processing model is used for analyzing fuzzy description to generate an analysis result, a knowledge base is inquired, a knowledge graph is combined to generate an association result, the analysis result, the association result and user feature data are fused to generate an execution scheme, the execution scheme is compared with an abnormal list, supervision confirmation is triggered, and a compliance instruction is generated. And personalized reminding contents are generated. The information analysis integrity is improved through multi-modal recognition, natural language processing and the knowledge graph, supervision confirmation and personalized reminding are introduced, and intelligent, compliant and reliable reminding management is achieved.

The invention discloses a multiplication acceleration method and device for double sparse matrixes, equipment, a medium and a product. The method comprises the following steps: positioning a compression matrix set matched with a first sparse matrix and a second sparse matrix in a global memory of a computing chip according to a sparse matrix multiplication demand; carrying the compression matrix set and the second sparse matrix step by step from the global memory to a hardware register of the computing chip in a data block form; and gradually calculating a multiplication result of the first sparse matrix and the second sparse matrix through a sparse calculation unit of the calculation chip according to the data loaded in the hardware register by several times. According to the technical scheme of the embodiment of the invention, the hardware acceleration performance of the sparse computing unit in the computing chip can be brought into full play, so that the overhead of computing, bandwidth and storage resources in the double sparse matrix multiplication process is greatly optimized, and the method is particularly suitable for a model computing scene of a hybrid expert model.

The current disclosure provides methods and systems that can manage the dynamic-uncertainty induced by resources of decentralized data networks, in order to ensure the stability and sustainability of task-oriented automated operations, such as operations conducted through intelligent agents. In contrast to the state-of-the-art object-based processing, the methods and systems enable object-aware processing, to ensure the establishment of stable and sustainable associations with physical and digital web-objects, while enabling those objects to be processed dynamically with full adaptability in response to contextual and structural alterations in real-time. Thus, the disclosure provides—both human and machine—users with the ability to develop and deploy modular systems capable of engaging any conceivable physical or digital interaction with the resources of a data network, such as dynamically linking and manipulating clusters of complex web-objects to execute complex tasks in complex and dynamic web environments—most importantly—stably and sustainably.

Disclosed in the present application are an instruction execution method and apparatus based on a language model, and a storage medium. The method comprises: when requirement information for a target object is received, calling a language model to perform instruction identification on the requirement information according to guide prompt information, so as to obtain a candidate execution instruction; performing an executability check on the candidate execution instruction, wherein when the candidate execution instruction does not pass the executability check, the language model is called to perform another instance of instruction identification on the requirement information according to the candidate execution instruction and the guide prompt information, so as to obtain a new candidate execution instruction, and perform another instance of the executability check on the new candidate execution instruction until the executability check is passed; and taking a candidate execution instruction which passes the executable check as a target execution instruction, and controlling, according to the target execution instruction, a terminal to execute an operation task corresponding to the requirement information. By means of the embodiments of the present application, the interaction efficiency and the usage experience of a user can be improved. The embodiments of the present application can be applied to various application scenarios in which interaction is performed with artificial intelligence.

The invention provides an instruction conflict control method and device, a storage medium and electronic equipment, and the method comprises the steps: detecting a first control instruction of a first control end for target equipment, and detecting a second control instruction of a second control end for the target equipment; judging whether a conflict exists between the first control instruction and the second control instruction or not; if the first control instruction conflicts with the second control instruction, calculating a first priority of the first control instruction, and calculating a second priority of the second control instruction; and selecting to execute the first control instruction or the second control instruction on the target equipment according to the first priority and the second priority. The technical problem of equipment abnormity caused by instruction conflict in related technologies is solved, and the flexibility of equipment control is improved.

A system for accelerating binary convolution operations of a neural network includes a set of destination registers, binary convolution circuitry, a decoder coupled to the binary convolution circuitry, and instruction fetch circuitry coupled to the decoder and configured to fetch a binary convolution instruction from an associated memory. The binary convolution instruction specifies input data, weight data, and the set of destination registers for performing a binary convolution operation. The decoder receives the binary convolution instruction from the instruction fetch circuitry and causes the input data and the weight data to be provided to the binary convolution circuitry. In response, the binary convolution circuitry performs the binary convolution operation on the input data and the weight data to produce output data and stores the output data in the set of destination registers.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.