2359results about "Machine execution arrangements" patented technology

An online system trains a transformer architecture by an initialization method which allows the transformer architecture to be trained without normalization layers of learning rate warmup, resulting in significant improvements in computational efficiency for transformer architectures. Specifically, an attention block included in an encoder or a decoder of the transformer architecture generates the set of attention representations by applying a key matrix to the input key, a query matrix to the input query, a value matrix to the input value to generate an output, and applying an output matrix to the output to generate the set of attention representations. The initialization method may be performed by scaling the parameters of the value matrix and the output matrix with a factor that is inverse to a number of the set of encoders or a number of the set of decoders.

The invention discloses a data processing system and method, electronic equipment and a storage medium, and relates to the technical field of computers.Original input data are preprocessed into multiple sets of target input data through a data input module, and the multiple sets of target input data are input into multiple iterative calculation units to obtain data to be calculated and code identifiers; when the code identifier represents that the to-be-calculated data needs to be overturned in advance, the to-be-calculated data is overturned in advance to obtain the to-be-calculated inverted data, and a subsequent iterative calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result; that is, the iterative calculation unit can obtain the data processing result only by performing a small amount of data bit flipping on the to-be-calculated inverted data through the target calculation, the number of data bit flipping in the target calculation is reduced, the dynamic flipping power consumption is reduced, and compared with a power consumption reduction mode in the related technology, the efficiency is improved. High-difficulty chip rear end layout wiring is not needed, and the performance and the power consumption reduction effect of the chip can be ensured.

A computer-implemented method includes receiving a neural network model that includes memory load operations and a plurality of computation operations, selecting a memory load operation having an arithmetic intensity factor (AIF) greater than a threshold value from the memory load operations, grouping computation operations associated with data loaded by the selected memory load operation into two or more clusters of computation operations, and incorporating an instance of the selected memory load operation before each cluster of the two or more clusters of computation operations in the neural network model.

The invention relates to the technical field of virtualization management, in particular to a virtual machine operation management system based on RISC-V. The system comprises an instruction set mapping module, a resource scheduling optimization module, a virtual machine monitoring integration module, an operation tuning update module and an operation configuration distribution module. According to the method, by analyzing the operation instruction of the virtual machine and combining the RISC-V underlying characteristics, accurate instruction mapping is achieved, the processing efficiency and accuracy are remarkably improved, the performance loss and conversion delay caused by too high abstraction level of a traditional virtual machine on the instruction level are overcome, the optimal allocation scheme is screened, the resource utilization rate and the system response speed are effectively improved, and the system performance is improved. The operation state and performance indexes of the virtual machine are integrated, anomaly detection and resource recovery are embedded, system stability and effective resource reutilization are ensured, basic configuration is continuously and incrementally updated, operation configuration refinement and automatic management and updating are achieved, the overall operation efficiency and management flexibility are improved, and the manual intervention cost is reduced.

Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

The invention discloses a zoom factor processing module, a processor and electronic equipment. The scaling factor processing module comprises: an index extraction unit configured to receive a target tensor and determine an index portion of a target scaling factor corresponding to the target tensor; the multi-scale processing unit is configured to determine a plurality of candidate scaling factors according to the exponential part of the target scaling factor; the first processing unit is configured to execute quantization operation and inverse quantization operation respectively based on the multiple candidate scaling factors and the target tensor, and determine inverse quantization results corresponding to the multiple candidate scaling factors respectively; and the second processing unit is configured to select a target candidate scaling factor as a target scaling factor corresponding to the target tensor according to the inverse quantization results corresponding to the plurality of candidate scaling factors. According to the scaling factor processing module provided by the invention, precise quantization can be efficiently realized on hardware, and the quantization precision is improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes such as financial science and technology and medical health, and discloses an anomaly analysis method, device and equipment based on multi-agent collaboration and a medium. The method comprises the following steps: generating fusion data through processing of a data fusion agent, extracting abnormal feature information through a data analysis agent, generating an abnormal analysis result and a decision instruction through a decision agent, collecting decision feedback through a feedback optimization agent, and analyzing and generating an optimization instruction for optimizing the data analysis agent and the decision agent. According to the method, closed-loop processing of data acquisition, fusion, analysis, decision and feedback optimization is realized through cooperation of multiple agents, so that multi-source heterogeneous data is efficiently integrated and deeply analyzed, the accuracy and adaptability of analysis and decision are continuously improved in combination with feedback optimization, and the timeliness and reliability of anomaly recognition and response are improved.

Improved placement of memory and functional modules, ‘tiles’, within a tiled processor architecture are disclosed for linear algebra calculations involving vectors and matrices comprising large amounts of data. The improved placement places the data in close proximity to the functional modules performing calculations using the data. These modules enable these calculations to be performed more quickly while using less energy. These modules, in particular, improve the efficiency of the training and application of deep learning and artificial neural network systems. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention discloses a queue management method of a storage device, an electronic device and a storage medium, and relates to the technical field of data processing. When the storage device is configured, a host only needs to send an instruction containing a batch operation type and a queue parameter storage address; triggering the storage device to obtain queue parameter information of a plurality of input and output queues in batches from a specified address, and completing creation or deletion operation of all the input and output queues at one time; according to the method and the device, a plurality of commands which need to be issued one by one originally are simplified into single interaction, so that the communication times and data transmission redundancy between the host and the storage equipment are greatly reduced, the occupation of link bandwidth is reduced, the time of an initialization or reset process is remarkably shortened, and the data transmission efficiency is greatly improved especially in a scene with a relatively large number of queues. The problems of heavy interaction burden, low link efficiency, long processing delay and reset overtime risk in the prior art are effectively solved, and the technical effects of simplifying the interaction frequency and improving the configuration efficiency are achieved.

The invention is suitable for the technical field of processors, and particularly relates to a vector configuration instruction implementation method and system and a storage medium. The implementation system comprises an instruction fetching unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit. The vector configuration instruction execution unit is used for obtaining the number of the idle register, renaming the received vector configuration instruction according to the number of the idle register to obtain a renamed vector configuration instruction and renaming information, and executing the renamed vector configuration instruction to obtain the renamed vector configuration instruction. And generating vector configuration information according to the execution result and sending the vector configuration information to a vector execution unit. Compared with the prior art, the vector configuration instruction is realized by introducing a register renaming technology, and simple and quick recovery can be carried out when speculative execution errors occur while the speculative execution capability is reserved, so that the design complexity can be reduced and the execution efficiency of the instruction can be improved while the performance is considered.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of data center operation and maintenance, financial science and technology, medical treatment and health and the like, and discloses a task processing method and device based on a domain knowledge base, equipment and a medium. Cleaning and formatting to generate standardized task list data, inputting the standardized task list data and a domain knowledge base into a language model to generate structured task list data, and matching task list types based on the structured task list data to generate a task list execution plan, and determining an execution mode according to the task list execution plan and executing to generate a task list execution state. Through cooperative processing of the domain knowledge base and the language model, standardized and structured processing of task list data is realized, and in combination with task type matching and execution mode control, processing automation and accuracy are improved, manual participation is reduced, and response speed and efficiency are improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of financial science and technology, medical health and the like, and discloses a multi-modal information analysis and scheme reminding method, device, equipment and medium, which comprises the steps of receiving input data and converting the input data into multi-modal data, executing optical character recognition and image classification recognition to generate a recognition result, and sending the recognition result to a server; a natural language processing model is used for analyzing fuzzy description to generate an analysis result, a knowledge base is inquired, a knowledge graph is combined to generate an association result, the analysis result, the association result and user feature data are fused to generate an execution scheme, the execution scheme is compared with an abnormal list, supervision confirmation is triggered, and a compliance instruction is generated. And personalized reminding contents are generated. The information analysis integrity is improved through multi-modal recognition, natural language processing and the knowledge graph, supervision confirmation and personalized reminding are introduced, and intelligent, compliant and reliable reminding management is achieved.

The current disclosure provides methods and systems that can manage the dynamic-uncertainty induced by resources of decentralized data networks, in order to ensure the stability and sustainability of task-oriented automated operations, such as operations conducted through intelligent agents. In contrast to the state-of-the-art object-based processing, the methods and systems enable object-aware processing, to ensure the establishment of stable and sustainable associations with physical and digital web-objects, while enabling those objects to be processed dynamically with full adaptability in response to contextual and structural alterations in real-time. Thus, the disclosure provides—both human and machine—users with the ability to develop and deploy modular systems capable of engaging any conceivable physical or digital interaction with the resources of a data network, such as dynamically linking and manipulating clusters of complex web-objects to execute complex tasks in complex and dynamic web environments—most importantly—stably and sustainably.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. Determining a first jump step length required for rearranging the block data based on the block size of the input data in the first dimension; secondly, performing jump reading on the block data according to a first jump step length, rearranging and loading read input elements into a thread private register so as to realize transposition storage of the block data in the thread private register, and mapping a thread direction on a second dimension so as to obtain a data basis of convolution correlation calculation; convolution correlation calculation is executed based on the transposed data in the thread private register and the weight data in the thread private register, repeated data reading in the calculation process is reduced during sliding window calculation, and an operator is converted into calculation performance bottleneck operation from memory access performance bottleneck operation.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared local memory coupled with the plurality of processing elements, a plurality of matrix engines coupled with the distributed shared local memory, and an asynchronous matrix multiply accumulate (MMA) controller configured to perform an asynchronous MMA operation via the plurality of matrix engines.

The invention provides a data loading method, a data storage method, a processor, electronic equipment and a medium. The data loading method comprises the steps of determining a plurality of first requests for loading a to-be-processed tensor based on an obtained loading mode of the to-be-processed tensor, a shape and a size of the to-be-processed tensor, a data storage format of the to-be-processed tensor and an initial coordinate of the to-be-processed tensor in a coordinate system determined by an original tensor; sequentially sending a first request in the kth loading request group in the X loading request groups, and sequentially obtaining data from the storage space to obtain first data returned by the kth loading request group; in response to the situation that the size of the first data returned by the kth loading request group is not aligned according to the multiple of Y, the first data is filled to obtain second data, and the size of the second data obtained through filling is aligned according to the multiple of Y; and writing the second data into the cache region. According to the data loading method, the complexity of instructions is reduced, and the overall performance of the processor is improved.

The invention discloses a TFHE-oriented programmable bootstrap hardware implementation system, and the system comprises a vector calculation module which is used for executing an analog-to-digital switching step in a TFHE-oriented programmable bootstrap algorithm on an LWE ciphertext; the rotary register is used for caching and rearranging the LWE ciphertext; the function calculation module is used for executing a blind rotation step in a TFHE-oriented programmable bootstrap algorithm on the rearranged LWE ciphertext and the analog-to-digital switching result to obtain a blind rotation result; the vector calculation module is also used for executing a sample extraction step and a key switching step in a TFHE-oriented programmable bootstrap algorithm on the blind rotation result to obtain a decrypted ciphertext; when the function calculation module executes the blind rotation step, the polynomial in the rearranged LWE ciphertext and the analog-digital switching result is decomposed into a plurality of sub-polynomials through a number theory conversion unit, and the sub-polynomials are subjected to parallel calculation. The method can reduce the use amount of hardware units, and is high in decryption success rate, high in performance and small in area.

The invention discloses an elevator group control method and device and a storage medium, and is applied to a group control system of multiple elevators in a building, and the group control system comprises a sensing layer, a decision-making layer and an execution layer. Calling a sensor in each elevator to sense the state information related to the waiting time of the elevator riders, the energy consumption of the plurality of elevators and the comfort level of the elevator riders in the historical tense, the current tense and the future tense; in the decision-making layer, near-end strategy optimization under reinforcement learning is executed according to the state information, so that one action is selected from the mixed action space to serve as a decision-making strategy; the mixed action space comprises discrete actions and continuous actions related to elevator calling control of each elevator; and in the execution layer, the multiple elevators are controlled to execute decision strategies, so that the elevator waiting time of the elevator passengers and the energy consumption of the multiple elevators are reduced, and the comfort level of the elevator passengers is improved. And through multi-level cooperation, the elevator operation efficiency is optimized, the user experience is improved, and the energy consumption is reduced.

Systems, methods, and computer program products are disclosed for generating a user-customized driving policy for use in navigating at least one host vehicle. The generation of the user-customized driving policy may include accessing a host vehicle driving policy model, wherein the host vehicle driving policy model includes a customizable driving performance component and an invariant navigational constraint component; receiving a driving performance value for assignment to the at least one controllable performance parameter; updating the customizable driving performance component based on the received driving performance value; generating the customized driving policy based on the updated customizable driving performance component and the invariant navigational constraint component; and outputting the customized driving policy for use in navigating the at least one host vehicle.

The present application provides a data check method, device and system, which are applied to the field of communications. The method comprises: obtaining operation environment information, check information and data to be checked; on the basis of the operation environment information and the check information, matching a target check mode, wherein the target check mode is one of a first check mode, a second check mode and a third check mode, the first check mode completes cyclic redundancy check (CRC) calculation on the basis of vectorization calculation, the second check mode completes the CRC calculation on the basis of a hardware CRC, and the third check mode completes the CRC calculation on the basis of a look-up table; and checking said data on the basis of the target check mode. The present application can support various CRC algorithms, and adaptively provide an optimal check mode on the basis of system information, thereby increasing the calculation speed, and optimizing data check.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

An all-to-all coupled, high-fidelity, error-correctable quantum computer can scale to hundreds of qubits within a single cavity of moderate cooperativity with existing neutral atom technology. This quantum processor can enact teleported gates among any pair of qubits using a local Rydberg interaction between each qubit and a separate network of atoms that distribute entanglement via a cavity mode. Small atomic ensembles at network nodes allow for ultrafast, nondestructive readout with high fidelity by substantially shifting the resonance of even a poor-quality cavity. Fast readout enables near-deterministic entanglement distribution among network atoms despite cavity losses as well as syndrome measurements of qubit atoms for error correction.

A sensor is disabled when it receives a signal from a control unit that the control unit has been placed into one or more particular operating modes. In response to receiving the signal, the sensor becomes disabled, thereby preventing detection and / or transmission of certain signals to the security panel. When the control unit is placed into another mode of operation, the control unit sends a signal to the sensor and, in response, the sensor is re-enabled, allowing the sensor to function normally.

The embodiment of the invention discloses a floating point calculation device and method for a processor, electronic equipment and a storage medium, and the device comprises a mantissa alignment module which is used for carrying out the interception processing of a first mantissa of a first floating point number based on an interception digit to obtain a first addend, and carrying out the first addend based on a shift digit to obtain a second addend; the second mantissa of the second floating-point number is shifted to obtain a second addend, and the first addend and the second addend are two mantissas with aligned indexes; the interception bit number and the shift bit number are determined based on an index difference value between a first index of the first floating-point number and a second index of the second floating-point number; the adder is used for adding the first addend and the second addend to obtain a first mantissa sum; and the post-processing module is used for performing normalization processing and rounding processing on the first mantissa sum to obtain a target mantissa. Therefore, the selector processing process before the mantissa is shifted in the floating point addition calculation process can be reduced, the calculation path is shortened, and the calculation speed is improved.