1057results about "Machine execution arrangements" patented technology

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention relates to the technical field of AI chips, in particular to a calculation method of an AI chip based on RISC-V CPU Core and the chip. The AI chip comprises a scheduling core and a plurality of computing cores based on an RISC-V instruction set architecture, and the method comprises the following steps: the scheduling core analyzes an AI task to determine one or more computing operation types required by the AI task, and selects one or more computing cores capable of executing the computing operation types from the plurality of computing cores according to the computing operation types; the scheduling core allocates the AI task to a calculation core corresponding to the calculation operation type, and activates the calculation core; and the calculation cores obtain respective kernel codes and required calculation data so as to execute respective calculation tasks. It can be understood that according to the technical scheme, the scheduling core and the computing core are both based on the RISC-V instruction set architecture, the ecological barrier problem is solved, flexible iteration of the architecture and optimal configuration of computing resources are achieved, and the method has the beneficial effects of ecological openness, high flexibility, remarkable cost effectiveness and the like.

The embodiment of the invention discloses a data processing device, a chip product, computer equipment and a data processing method. The data processing device comprises an instruction decoding module, a data moving module and a plurality of calculation units; wherein the instruction decoding module is used for receiving a calculation instruction based on open source instruction set architecture RISC-V extension; the data moving module is used for responding to the calculation instruction and determining a prediction configuration parameter to be used by a target calculation unit corresponding to the calculation instruction; the calculation unit is used for utilizing a target calculation unit corresponding to the calculation instruction to obtain configuration parameters to be used by the target calculation unit when the calculation instruction is executed; and if the configuration parameter hits the predicted configuration parameter, performing unit configuration by using the predicted configuration parameter so as to perform data operation processing.

The invention discloses a processing device, an instruction processing method, a chip device and electronic equipment, and belongs to the technical field of electronics. The processing device comprises a physical register file, a physical register cache unit and an execution unit, the physical register file comprises a first read port and a first number of physical registers, the physical register cache unit comprises a second read port and a second number of cache lines used for caching data of the second number of physical registers, and the second number is smaller than the first number; the execution unit is used for responding to all the source data of the first instruction and executing the first instruction based on all the source data of the first instruction, and any source data in all the source data of the first instruction is read from the first number of physical registers through the first read port or read from the second number of cache lines through the second read port. The instruction execution efficiency can be improved on the basis that the occupied area is not greatly increased, and the instruction processing performance of the processing device is improved.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

The invention provides a loading storage circuit and a graphics processor, and relates to the technical field of graphics processing. The loading storage circuit comprises an instruction scheduling module, an address generation module and a data service module, and is provided with a buffer area module which comprises an operand buffer area and an effective data buffer area and is used for caching information required by address calculation and data access; the instruction scheduling module is used for collecting a data access instruction and outputting instruction information; the address generation module calculates a target access address according to the instruction information and the operand; and the data service module executes corresponding data loading or storage operation on the target cache unit. According to the scheme, the operands and the valid data are pre-cached, so that overflow and stagnation caused by inconsistent processing rhythms among modules can be avoided, and the parallel processing capability of an assembly line is improved; through the independent address calculation and data access process, the stability of the access time sequence and the data processing efficiency can be improved.

The invention relates to the field of artificial intelligence, and particularly discloses a cooperative office intelligent agent using method and device and a medium, the method comprises the following steps: receiving an input instruction from a user, and analyzing the input instruction to obtain an analysis result; generating a tool calling request based on the analysis result; based on the tool calling request, calling the target MCP Server to generate a tool execution result of the input instruction; and converting the tool execution result into a return result, and sending the return result to the user. And for an enterprise administrator, the intelligent scene access of the service can be completed only by additionally configuring the information of the MCP Server when the light application is originally added. Not only can the scene requirements of enterprise process automation, intelligent work order processing, cross-system data integration and the like be effectively met for enterprises, but also the MCP Server can be automatically expanded for enterprise users, and all the requirements of user office are met.

The invention discloses a method, device and equipment for intelligently controlling a BIM model and a storage medium, and the method comprises the steps: receiving a natural language interaction instruction for a target BIM model, and converting the natural language interaction instruction into a structured instruction comprising a target building object and an interaction intention through a preset building domain knowledge base; if the interaction intention is a query intention, obtaining related model data about the target building object from the target BIM model through a data query tool, and forming query result information meeting the query intention based on the related model data; if the interaction intention is a control intention, firstly determining identity recognition information of the target building object from the target BIM model through a data query tool, and then generating and executing a control code corresponding to the control intention and the identity recognition information through a model control tool so as to implement specified operation on the target building object; according to the invention, the interaction process between the user and the BIM model is simplified.

The invention discloses an equipment manufacturing energy consumption and state visual monitoring method based on an industrial internet of things, solves the problem of passive fixation of an industrial monitoring visualization technology in the prior art, and realizes autonomous and intelligent generation of an optimal visual view matched with a real-time working condition. The method comprises the following steps: collecting industrial field multi-source heterogeneous data in real time, abstracting a monitoring object as an entity node, and constructing a feature vector containing static and dynamic attributes; constructing and updating a dynamic knowledge graph based on nodes and features, wherein relation edges of the dynamic knowledge graph comprise dynamic edges generated by static connection and real-time analysis; inputting the atlas into a pre-trained multi-attention graph neural network to obtain a display priority score and a visual affinity matrix of each node; calculating coordinates of all nodes on an interface through a layout optimization algorithm in combination with the priority and the affinity matrix; and generating a visual drawing instruction according to the coordinates and the node attributes, and driving a display device to render a monitoring interface.

A system receives, by a network interface card (NIC), inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing, and a datatype descriptor defining organization of the message payload. The system identifies a current context and a processing state for the instruction. If the datatype descriptor indicates a first type, the system: obtains the current context associated with the first type from a host memory or a cache of the NIC; and creates direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop. If the datatype descriptor indicates a second type, the system: obtains the current context associated with the second type by fetching vector entries from a buffer of the NIC; and creates the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries.

The invention provides an intelligent caching method and device based on a self-adaptive caching strategy, and the method comprises the steps: collecting an access event flow of each caching key in real time through a sensing probe embedded in a caching client, the event flow comprising Key, operation type, timestamp, request source, hit state and response time; running a streaming processing engine at a client based on an access event stream, and calculating indexes such as instantaneous QPS, continuous miss times and short-term access frequency by adopting a sliding time window; a calculation result is input into a rule engine for online matching, a decision instruction for a single Key is generated, and the decision instruction comprises distributed mutual exclusion lock addition, local TTL dynamic adjustment and read-write mode switching; a decision instruction is directly executed in a client memory through a strategy executor, and nanosecond strategy effectiveness is achieved; and finally, collecting system feedback data after strategy execution, inputting the system feedback data into a machine learning module for online learning, and dynamically optimizing a rule threshold value or recommending a new strategy.

This disclosure provides GPU computational resource scheduling methods and apparatuses. In an implementation, a method includes: in response to a target computing task created in a computing cluster, determining a task type of the target computing task. If the target computing task is a first-type computing task, scheduling, for running, the target computing task to a first GPU hardware that has remaining computational resources satisfying a computational demand of the target computing task in the computing cluster. In response to a first indication indicating that is reported by a first computing node integrated with the first GPU hardware and that indicates that the first-type computing task exclusively occupies computational resources of the first GPU hardware, rescheduling, for running to a second GPU hardware that has remaining computational resources satisfying a computational demand of the second-type computing task in the computing cluster.

An instruction executing within a computing environment is used to perform at least one operation on one or more controls of a queue to be used in communications between a control program executing within the computing environment and an adapter module of the computing environment. Execution of the instruction includes obtaining an indication of the queue for which at least one operation is to be performed on the one or more controls of the queue. At least one operation is performed on the one or more controls of the queue and a result of executing the instruction is provided.

The invention discloses an MAC unit supporting input activation and weight double-end sparsity, and relates to the technical field of neural network accelerator hardware design. Aiming at the technical defects existing in a sparse matrix acceleration scheme, the scheme is adopted, an activation value and non-zero elements of a weight matrix are stored through a special compressed data register, corresponding zero value distribution is recorded through a matched sparse bitmap register, and a joint sparse bitmap marking a double-non-zero effective calculation position is generated through dual-port joint operation; and the control and address generation subunit scans the joint sparse bitmap and outputs an address and an enable signal, the MAC calculation subunit is driven to read non-zero data to complete multiply-accumulate operation, and finally, an operation result is compressed and coded through an output end sparse encoder, so that efficient transmission of interlayer sparse data streams is realized. According to the method, input activation and weight double-end sparsity can be utilized at the same time, end-to-end sparse data flow is supported, zero value calculation can be dynamically skipped, and the energy efficiency ratio and the calculation throughput of neural network reasoning are improved.

The invention discloses a data processing method and device, electronic equipment and a nonvolatile storage medium. The method comprises the following steps: dividing a data matrix to be calculated into a plurality of data blocks with target sizes; data corresponding to the data blocks are allocated to a plurality of stream processors for data reading operation, the data reading operation is used for loading the data from a global memory of the edge computing device to a shared memory, and the data reading and writing efficiency of the shared memory is higher than that of the global memory; and loading the data in the memory block with the preset vector length in the shared memory into a register by taking the preset vector length as a unit, and operating the data loaded into the register by adopting a stream processor to obtain an operation result. The technical problem that the computing efficiency is not high due to the fact that the related technology is limited by the particularity of the memory access and computing rule of the correction operator and the hardware performance of the edge computing equipment cannot be fully exerted is solved.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention provides an operation method of an attention mechanism in a chip, the chip, electronic equipment, a storage medium and a program product. In a forward stage of attention model training, forward calculation is performed on a query matrix, a key matrix and a value matrix in each thread of a calculation engine based on a first instruction pipeline to obtain a forward output matrix, in algorithm implementation, matrix multiplication is executed by calling a matrix multiplication unit through a first thread and a third thread, and a forward output matrix is obtained. The vector calculation is processed by a second thread calling vector calculation unit; in a reverse phase, performing reverse calculation on the query matrix, the key matrix, the value matrix and the output gradient matrix in each thread based on a second instruction pipeline to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or the third thread to obtain all matrixes. According to the invention, the operation performance of the chip can be improved.

Example apparatus disclosed herein include an array of processor elements, the array including rows each having a first number of processor elements and columns each having a second number of processor elements. Disclosed example apparatus also include configuration registers to store descriptors to configure the array to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of multiple tensor processing templates, ones of the processor elements to be configured based on the descriptors to implement the one of the tensor processing templates to operate on input activation data and filter data associated with the layer of the convolutional neural network to produce output activation data associated with the layer of the convolutional neural network. Disclosed example apparatus further include memory to store the input activation data, the filter data and the output activation data associated with the layer of the convolutional neural network.

The invention provides an RISC-V vector data loading instruction processing method and a processor, and relates to the technical field of processors. When a vector loading instruction is transmitted, memory access address calculation and memory access can be started in advance only by making a source operand ready, and waiting for an old value of a target vector register is not needed, so that transmission blocking caused by dependence of the old value is avoided; by temporarily storing loaded data in a vector data buffer area, memory access operation and subsequent merging write back are decoupled, and memory access delay and old value ready waiting time are overlapped; and when the instruction becomes the oldest to-be-written-back instruction and an old value is ready, the merging unit merges new and old data element by element according to the mask and vector configuration to ensure correct implementation of RISC-V vector extension complex semantics. On the premise of not influencing the function correctness, the memory access delay is effectively hidden, the instruction level parallelism is improved, and the processing efficiency of the vector loading instruction is remarkably improved.

Apparatuses, systems, and techniques to enable efficient use of mixed precision hardware architecture. In at least one embodiment, one or more first precision circuits and one or more second precision circuits are used on portions of data sets.

The invention relates to the technical field of unified management, in particular to a localized key component adaptation and unified management platform construction method, which comprises the following steps: extracting and merging path information, comparing an affiliation relationship to execute binding, extracting a migration content annotation jump structure, and summarizing and registering combined path data in sequence. And generating a key component adaptation and unified management platform construction scheme. According to the method, merging processing is carried out through the triggering relation of the action field and the scheduling instruction, unified extraction and non-repeated integration of path behavior information are achieved, the attribution path relation is compared according to the action frequency and the field span, the structure recognition accuracy is improved, channel binding actions without name conflicts are screened, and clear path matching is ensured; the method comprises the following steps of: marking a jump source and a pointing position in a path migration process, realizing the traceability of structure change, integrating an affiliation label and an action field according to an original sequence, registering and archiving, and enhancing the orderliness and calling consistency of a data structure.

The invention discloses a multi-modal conference summary generation method and system based on a large language model, and relates to the technical field of artificial intelligence, and the method comprises the steps: receiving conference basic information uploaded by a user and a conference file containing a picture and an audio; the audio file is transferred into a structured text with a timestamp through an ASR voice transfer technology, and the picture file is recognized as an editable text through an OCR technology; conference basic information, a structured text and an editable text are integrated and converted into a structured conference summary first draft, then text cleaning and content error correction are performed on the first draft in combination with a large language model and predefined logic, participant information is extracted, and finally a customized instruction is input into the large language model through a prompt project to obtain a complete conference summary. And performing accurate filling according to a structured field of the predefined Word template to generate an editable conference summary Word document. The conference summary can be automatically output, and the writing efficiency of the conference summary is improved.

Embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and related devices and methods. The present solution is applicable to various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set), or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc. The instruction retirement unit includes a receiving subunit configured to receive a completion request signal; an arbitration subunit configured to, after determining that a to-be-completed instruction can be completed, send a completion permission signal to an instruction execution unit, and store instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer; and a retirement subunit configured to, according to the instruction completion information stored in each instruction buffer table item, perform retirement processing on a to-be-retired instruction which has been completed but not retired, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The present solution can reduce the hardware resource consumption of the processing unit for the instruction reordering part.

The embodiment of the invention discloses a processor, a chip product, computer equipment and a data processing method. The processor comprises a block matrix calculation unit, a storage unit and a target register, wherein the storage unit is used for storing an input matrix to be processed and inverse quantization data corresponding to the input matrix; the block matrix calculation unit is used for reading the block matrix from the storage unit and reading the last target operation result from the target register; performing accumulation operation on the last target operation result and the block matrix to obtain a candidate operation result; and according to the inverse quantization parameter corresponding to the block matrix read from the storage unit, performing data precision adjustment on each element in the candidate operation result to obtain a current target operation result, and updating and storing the current target operation result in a target register.

The invention discloses a drawing instruction execution method and device and a medium, and relates to the technical field of computers.The drawing instruction execution method comprises the steps that an initial drawing instruction set is preprocessed, and a target instruction set is obtained; determining a target processing unit of the target instruction set according to the state information of the hardware processing unit; the target processing unit comprises a hardware processing unit and a software processing unit; and scheduling the target processing unit to execute the target instruction set. Visibly, whether the target processing unit of the target instruction set is the hardware processing unit or the software processing unit is determined according to the state information of the hardware processing unit, so that drawing instruction accumulation and low execution efficiency caused by overhigh load of the hardware processing unit, task congestion or resource shortage are avoided; and therefore, the problems of picture lagging, abnormal display and the like in a high-concurrency scene can be solved.

The invention provides an immediate operand instruction fusion method, an immediate operand instruction fusion device, electronic equipment and a computer program product. In a renaming stage, aiming at a RAW instruction having data read-after-write RAW correlation with a first loading immediate operand instruction, according to a source logic register number index register mapping table of the RAW instruction, the first loading immediate operand instruction is subjected to data read-after-write RAW correlation; obtaining a first status bit and a first table item of a source operand of the RAW instruction; and obtaining a fusion instruction by combining the RAW instruction with a first immediate value of a first loading immediate number instruction stored in the first table item under the condition that the table item storage content corresponding to the source logic register number is determined to be the immediate value according to the first status bit. Therefore, the immediate operand is directly fused to the RAW instruction in the renaming stage by utilizing the extended register mapping table, so that the dependence of instruction fusion on the adjacent program sequence is broken, a consumer instruction can obtain the operand without waiting for the execution of the immediate operand loading instruction, and the instruction execution delay is remarkably reduced.

System and methods for automatically generating control / status registers (CSR) based on configurations of components in a Network on Chip (NoC) include generating at least one repeatable field group from a plurality of defined fields, each of the plurality of defined fields defining portions of a register and NoC connectivity, generating at least one repeatable multi-register from the at least one repeatable field group, and generating at least one CSR group from the at least one repeatable multi-register, the at least one CSR group generated to be incorporated into a CSR bank. Such systems and methods of generating CSRs provides flexibility for designers / users to optimize the NoC for area consumption, reducing cost and complexity, parameterize configurations of the CSRs, and the like.

The invention discloses a cross-ISA mapping method for a unified atomic electricity calculation semantic layer, and relates to the field of electricity calculation fusion index measurement, and the method comprises the steps: 1, obtaining an instruction sequence of a to-be-evaluated or to-be-analyzed application on a target ISA; 2, according to a predefined UACES abstract instruction set, translating each instruction of the target ISA into one or more UACES atomic instructions according to an instruction set conversion translation rule; 3, performing bit width normalization metering on the obtained UACES atomic instruction according to a bit width scaling rule to obtain arithmetic, logic, memory access and control flow indexes based on 64 bits; and step 4, aggregating and analyzing normalized UACES instruction statistical results for scenes between different ISA, and providing a unified representation and measurement basis for semantic alignment and statistics in cross-ISA performance evaluation and reference comparison and instruction coding optimization.

The invention discloses a data processing method, a multi-core heterogeneous system and a computer readable storage medium, and belongs to the technical field of data processing.The method comprises the steps that in the initialization stage of a hardware system, a physical storage space is allocated based on a predefined physical address boundary, and the physical storage space comprises a shared space; writing predefined configuration data corresponding to the shared space into a configuration register of the storage management module and latching the configuration register, wherein the configuration data comprises an access control strategy and a storage attribute; in the starting stage of the operating system, an address mapping relation is obtained, the address mapping relation comprises a target mapping relation, and under the condition that the operating system runs, a storage management module is triggered based on an instruction of a target operation to execute the target operation based on the address mapping relation, configuration data and a virtual address corresponding to the instruction, the target operation is read operation or write operation. The calculation amount of the processor is greatly reduced, and the time consumption for reading and writing data is reduced on the whole.

An apparatus and method are described for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality cores and power management circuitry to associate a plurality of performance values and a plurality of efficiency values with the plurality of cores. In some implementations, each core is associated with at least one performance value and at least one efficiency value. The performance values and efficiency values are used by a scheduler for scheduling threads on the plurality of cores. Some implementations include dynamic core configuration hardware logic coupled to or integral to the power management circuitry to resolve a plurality of configuration hints into a consolidated hint for updating one or more performance values of the plurality of performance values and / or one or more efficiency values of the plurality of efficiency values.