33 results about "Multiprocessor network" patented technology

The virtual supercomputer is an apparatus, system and method for generating information processing solutions to complex and / or high-demand / high-performance computing problems, without the need for costly, dedicated hardware supercomputers, and in a manner far more efficient than simple grid or multiprocessor network approaches. The virtual supercomputer consists of a reconfigurable virtual hardware processor, an associated operating system, and a set of operations and procedures that allow the architecture of the system to be easily tailored and adapted to specific problems or classes of problems in a way that such tailored solutions will perform on a variety of hardware architectures, while retaining the benefits of a tailored solution that is designed to exploit the specific and often changing information processing features and demands of the problem at hand.

An event synchronization protocol called time-based synchronization (TBS) is employed to control operation of a network simulation. In TBS, processors in the simulated network execute events based on comparisons between timestamps for each event and a value generated by a time tracking device in the processor. In this manner, event execution is not dependent on other processes in the network and the simulation can actually be carried out at speeds faster than real time. A multiprocessor network is specially designed to execute TBS-based simulations.

The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular / normal address tenures and these modified address tenures and respond to a receipt of a modified address tenure by removing the synchronization data stored therein and updating the corresponding register location of the PCR.

The invention discloses a parallel data transmission method on an extended cube structure multi-processor network. When a processor is designated as a source processor in the invention, a group of edge-independent spanning trees can be constructed in parallel with the processor as the center, so that There are 2n-1 edge-disjoint paths from this processor to any other processor. Data can be decomposed into these 2n‑1 paths for parallel transmission without interfering with each other. According to any given vertex, the present invention can construct 2n-1 edge-independent spanning trees in parallel; there are 2n-1 edge-disjoint paths between the root vertex and any other vertex; each tree can be constructed independently. The invention has better topology properties, can greatly reduce hardware cost and communication overhead, and improve the balance of communication cost, and has broad market prospects in the popularization of interconnection network structure.

A method and system for increasing reliability and availability of a multi-processor network. A system includes a network with at least two nodes, with each node comprising a multi-processor unit (mpu) and memory. The mpu includes one or more processors and a wiretap unit. The wiretap unit and the memory included in the node are coupled to the processors in the node. The wiretap unit is configured to monitor memory accesses of the processors and convey data indicative of such accesses to a second node. The second node maintains a replica of memory in the first node, and is configured to undo modifications to the memory if needed. In the event of a hardware or software fault, the nodes are configured to restart the application on another node.