Multi-processor load distribution-regulation method

Abstract

The invention is a multiprocessor load allocation regulating method, relating to the data communication field, especially relating to a technique for regulating load allocation of each processor in multiprocessor network equipment. And it comprises the steps of: a. CPU obtains bandwidth condition of system interface socket; b. according to processing ability of each processor, CPU allocates interface to each processor in proportion. And it makes the data flow processed by each processor in operation basically equivalent, relatively uniformly and appropriately allocating processor resources and avoiding load allocation ununiformity in a multiprocessor system.

Description

technical field [0001] The invention relates to the field of data communication, in particular to an adjustment technology for load distribution of each processor in a multi-processor network device. Background technique [0002] In existing data communication systems, network node devices with high performance and complexity requirements usually adopt a distributed system architecture to process data forwarding tasks of various interfaces at high speed. The main task of this network device is to forward data packets at a very high speed, so most of the multiple processors of the network device handle forwarding tasks. [0003] In today's multi-processor network equipment, the load distribution of the processors that handle forwarding tasks is usually static, that is, it has been fixed at design time, that is to say, a certain processor handles one or more interfaces receiving and receiving tasks fixedly. sent data. For example, processor 1 processes data in slots 1 and 2,...

AI Technical Summary

Problems solved by technology

A very serious shortcoming of this processing method is that the load of the processor cannot be dynamically adjusted in the actual environment. It may happen that a certain processor must handle multiple high-speed interfaces, while another processor only handles one The situation of the low-speed interface leads to serious uneven load on the processor, which makes the actual use efficiency low and the processor performance is seriously wasted.

The main problem brought by this method is that since the same interface may be processed by multiple processors, a mutual exclusion mechanism must be introduced, which affects the parallelism of multiple processors, thereby reducing the forwarding performance of the interface.

There is also a structure in which each processor is designed on each line card, and each interface line card has its own processor. Although this design bypasses the problem of multi-processor load distribution, it is followed by The sharp increase in the number of processors has led to an increase in costs; since each processor is not on the same printed circuit board, it is also difficult to connect processors at a high speed, or the cost of high-speed connections has also risen sharply; at the same time, the design difficulty of the system software has also increased sharply. increase

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