184 results about "Processor assignment" patented technology

Techniques to more accurately measure the arrival times of transmissions received at a remote terminal from a number of base stations. In one aspect, unassigned finger processors are used to process and measure the arrival times of transmissions from base stations not in the active set. In another aspect, if no finger processors are available for assignment, the arrival times can be measured in the time period between updates of a reference oscillator used for the measurements. In accordance with a method for determining a position of a remote terminal, a first set of one or more base stations in active communication with the remote terminal is identified and each base station in the first set is assigned at least one finger processor. A second set of one or more base stations not in active communication with the remote terminal is also identified and an available finger processor is assigned to each of at least one base station in the second set. A (signal arrival) time measurement is then performed for each base station, and outputs indicative of the measurements are provided for further processing. To improve accuracy, the measurements can be performed within a narrow time window.

A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

A processor allocation mechanism for a logically partitionable computer system allows an administrator to specify processing capability allocable to each partition as an equivalent number of processors, where the processing capability may be specified as a non-integer value. This processing capability value is unaffected by changes to the processing capability values of other partitions. The administrator may designate multiple sets of processors, assigning each physical processor of the system to a respective processor set. Each logical partition is constrained to execute in an assigned processor set, which may be shared by more than one partition. Preferably, the administrator may designate a logical partition as either capped, meaning that a partition can not use excess idle capacity of the processors, or uncapped, meaning that it can.

A heterogeneous multiprocessor system including a plurality of processor elements having mutually different instruction sets and structures avoids a specific processor element from being short of resources to improve throughput. An executable task is extracted based on a preset depending relationship between a plurality of tasks, and the plurality of first processors are allocated to a general-purpose processor group based on a depending relationship among the extracted tasks. A second processor is allocated to an accelerator group, a task to be allocated is determined from the extracted tasks based on a priority value for each of tasks, and an execution cost of executing the determined task by the first processor is compared with an execution cost of executing the task by the second processor. The task is allocated to one of the general-purpose processor group and the accelerator group that is judged to be lower as a result of the cost comparison.

A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments for ready-to-run processes/threads. Processors are chosen to minimize access latency. Further, the Page Fault Handler is modified such that free memory pages are assigned to a process based partially on the proximity of the memory with respect to the processor requesting memory allocation.

In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment.

An Interbank Deposit Placement System (IDPS) that allows banks participating in the service to offer their customers multiple deposits so that potential deposit (fund) amounts exceeding an applicable Federal deposit insurance limit (e.g., $100,000) are fully insured. The IDPS partitions each of the potential deposit amounts into a plurality of deposit portions that do not exceed the Federal deposit insurance limit. In one embodiment, a proposed list of banks to which the deposit portions are allocated is presented to a recipient (e.g., bank representative, depositor) who is offered the option of modifying the proposed list during an established time window. After the time window expires, a deposit is established on behalf of each bank on the list to which the specific deposit portion was allocated by the processor.

In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. The system and method can reschedule processes to run on the processor on which the assignment is made.

A system for facilitating virtualization of a heterogeneous processor pool includes a processor allocation component and a hypervisor, each executing on a host computer. The processor allocation component identifies a plurality of physical processors available for computing and determines a set of flags, each of the set of flags identifying a type of functionality provided by each of a subset of the plurality of physical processors. The hypervisor, in communication with the processor allocation component, allocates, to at least one virtual machine, access to one of the subset of the plurality of physical processors.

Methods, signals, devices, and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the multi-faceted task space is assigned to a task. The task is then associated with the processing unit if the region allocated to the processing unit is close to the point assigned to the task. The region allocated to a processing unit may be changed. If no assigned point for a task is sufficiently close to any allocated processing unit region, the task is suspended. Overlapping regions may be assigned to different processing units. In some implementations, the union of the allocated regions covers the task space, while in others it does not. Regions may also be allocated to wait conditions and one or more dimensions of a region may be allocated to conventional processor allocators.

A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.

A method for determining if a user of a computer system is a human. A processor receives an indication that a computer security program is needed and acquires at least one image depicting a first string of characters including at least a first and second set of one or more characters. A processor assigns a substitute character to be used as input for each of the second set of one or more characters. A processor presents the at least one image and an indication of the substitute character and when to use the substitute character to the user. A processor receives a second string of characters from the user. A processor determines whether the second string of characters substantially matches the first string of characters based on the substitute character assigned to each of the second set of one or more characters and determines whether the user is a human.

An information processing apparatus includes a control operating system executing a process for allocating a plurality of logical processors to a physical processor in a time division manner, and a guest operating system for which a logical partition as an application entity of the logical processor is set. The control operating system sets and updates, as address conversion tables for determining an allocation relationship between the logical processor and the physical processor, two address conversion tables of a first conversion table that sets an allocation relationship between a logical partition address space and a physical address space and a second conversion table that sets an allocation relationship between a virtual address space in the guest operating system and the physical address space.

A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.

A scheduling processor allocates a time slot of a communication protocol to a user equipment for data transmission based on received control data of the same or another user equipment in a current time slot and received user data of the same or another user equipment in a preceding time slot, while ignoring user data of the same or any other user equipment received in the current time slot. The scheduling processor also allocates a frequency resource to the user equipment. A control channel managing processor allocates signaling resources on a control channel for the submission of control information to the user equipment, which informs of the time slot allocated by the time domain scheduling processor as well as of the frequency resource allocated by the frequency domain scheduling processor.

To efficiently manage performance resources while preventing a failure of a control processing from affecting another control processing in a disk array apparatus.

A disk array apparatus 1 has a disk array controller 11, the disk array controller 11 has a CPU incorporating a plurality of processor cores 1110 that cannot be physically separated from each other, each processor core serves as an unit processor, one unit processor manages the unit processors separately, allocates a self-contained control program to each unit processor in such a manner that the operation of the unit processor can be terminated appropriately or in such a manner that the unit processor can operate until the operation of the whole CPU is terminated, and manages the processing load or processing status of the allocated control program on a unit-processor basis.

Task management in a Non-Uniform Memory Access (NUMA) architecture having multiple processor cores is aware of the NUMA topology in task management. As a result memory access penalties are reduced. Each processor is assigned to a zone allocated to a memory controller. The zone assignment is based on a cost function. In a default mode a thread of execution attempts to perform work in a queue of the same zone as the processor to minimize memory access penalties. Additional work stealing rules may be invoked if there is no work for a thread to perform from its default zone queue.

According to an aspect of the present invention, the processor temperatures can be leveled among processors, thereby suppressing the occurrence of stop of processing due to overheating. For example, on the basis of the temperatures of the processors sensed by temperature sensors, the control IC assigns the processor whose temperature is the lowest to the task whose heat emission is the highest. This makes it possible to level the processor temperatures among processors and suppress occurrence of stop of processing due to overheating.

In one exemplary embodiment, a computer-implemented method of generating an implicit social graph includes receiving an eye-tracking data associated with a word. The eye-tracking data is received from a user device. The word is a portion of a digital document. The eye-tracking data comprises at least one fixation period of substantially seven-hundred and fifty milliseconds and at least one regression from another portion of the digital document to the word. A comprehension difficulty of the word is determined based on the eye-tracking data. One or more attributes to a user of the user device is assigned, by one or more processors based on the comprehension difficulty, wherein the one or more attributes are determined based on a meaning of the word. An implicit social graph is generated based on the one or more attributes.

An information exchanging apparatus capable of exchanging information with a plurality of outside apparatuses has: a first wireless communicator including a telephone transmitter and telephone receiver for wireless telephone communication with one of the outside apparatuses; a second wireless communicator other than the first wireless communicator; a transmitter arranged to transmit original information to the plurality of outside apparatuses through the second wireless communicator; a processor arranged to process response information from the plurality of outside apparatuses to be received through the second wireless communicator in response to the original information; and a distributor arranged to distribute result information from the processor to the plurality of outside apparatuses through the second wireless communicator.