22 results about "Processor assignment" patented technology

The invention provides a computer system starting method and device, electronic equipment and a storage medium, and can be applied to the technical field of computers. The method comprises the steps of executing a first initialization task under the condition that power-on of a computer system is completed; the first initialization task comprises executing an initialization configuration operation on first equipment of the computer system; under the condition that the execution of the first initialization task is completed, based on the global resource information of the equipment resources, allocating the equipment resources to the plurality of processors, and determining local resource information of each of the plurality of processors; executing the plurality of second initialization tasks in parallel by utilizing the plurality of processors, and determining respective initial resource allocation results of the plurality of processors; under the condition that execution of the multiple second initialization tasks is completed, resource unification adjustment is executed according to the multiple initial resource allocation results, and a target resource allocation result is obtained; and in response to resource adjustment completion, loading an operating system of the computer system to start the computer system.

The invention provides a decoder, a decoding method, a memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, wherein the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check formula, the check matrix and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to select a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the checkout weight in the initial iteration; distributing one flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit is configured to output the to-be-decoded code word in the next iteration based on the comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value allocated by the processor.

The invention provides a task allocation method, device and equipment, and relates to the technical field of video processing. The method comprises the steps of performing task division on a to-be-allocated task according to a first division mode under the condition of obtaining the to-be-allocated task to obtain a first sub-task; generating a second division mode according to the task characteristics and the resource state of the processor; performing task division on the to-be-allocated task according to a second division mode to obtain a second sub-task; and according to the first sub-task and the second sub-task, obtaining a target second division mode with the lowest coincidence degree with the first division mode from the second division modes, performing task division on the to-be-allocated task, and allocating the divided task to at least one processor for processing. According to the scheme provided by the invention, the difference between the processor allocation results of the newly generated second sub-task of the second division mode and the used first sub-task of the first division mode is maximum, so that more unique computing areas of the processor can be covered, and the resource utilization is more balanced.

An RTOS includes an event processor construct. The event processor has a task priority and an event processor handler. A stack for the event processor is allocated by the RTOS. The event processor handler is called by the RTOS each time an event is posted by an interrupt request handler or another task. Once processing of the event completes, the event processor handler returns (as opposed to remaining in an infinite loop) thereby allowing the stack allocated to the event processor to not be retained on entry into a sleep state and the memory bank containing the stack to be powered down during a sleep state.

The present application belongs to the technical field of embedded real-time system, and particularly relates to a non-hungry distribution method of multi-core processor based on EDZL algorithm. The method comprises the following steps: firstly, obtaining a real-time task set by calling system parameters, and calculating the priority of each task in the task set; secondly, calculating the slackness of each task, setting the priority of the task with zero slackness as 0, and arranging the tasks into a stack according to the priority from high to low; and finally, distributing the task set to the processor cluster by using the non-hungry processor distribution method. The method has good applicability, can improve the system resource utilization rate of the processor, balance the system performance and task power consumption, and effectively guarantee the real-time performance of the system.

Disclosed in the present application are a task allocation method and apparatus, and a device, a storage medium and a program product in the technical field of computer applications. The method comprises: acquiring state information of a processor in a server cluster, and writing into a target record idle-processor identifiers determined by using the state information; sequentially reading the idle-processor identifiers from the target record, and sequentially reading dataset paths from an input file; determining one read idle-processor identifier and one read dataset path as an allocation information pair, on the basis of each allocation information pair, performing splicing to obtain a task command and writing same into an output file, and deleting from the input file dataset paths that have been read and used; and on the basis of the output file, allocating an inference task to an idle processor in the server cluster. The technical effects are as follows: the present application can automatically allocate an inference task of a model to a server cluster in a distributed manner, thereby reducing the learning cost for developers on a distributed framework and the time cost of task allocation and deployment.

Apparatuses, methods, and systems are disclosed for setting up multiple user plane (“UP”) security contexts. One apparatus includes a transceiver and a processor that derives distinct UP integrity and ciphering keys for a selected central unit user plane (“CU-UP”) node in the RAN, said derivation using a key derivation function. The processor assigns a UP Security Indicator to uniquely identify the derived distinct UP integrity and ciphering keys and the transceiver sends a setup request to the selected CU-UP node, said setup request containing the UP Security Indicator and the distinct UP integrity and ciphering keys. The transceiver receives a setup response from the selected CU-UP node and the processor activates distinct UP security at a UE.

The invention relates to a multi-ROM (Read Only Memory) quick starting method based on a heterogeneous multi-core chip, the heterogeneous multi-core chip comprises a security core and at least one other processor, initialization codes of each processor are respectively stored in respective corresponding independent ROM, a user program and an operating system program are stored in FLASH, and after a system is powered on, the security core and at least one other processor can be started. The security core is started by default and executes a first starting process: reading a user program in the FLASH to the storage space allocated by each processor; when the security core executes the first startup process, the at least one other processor is started according to the configuration signal of the power management module and executes the second startup process. According to the method, the security core is used for overall starting, the starting time of the heterogeneous multi-core system can be shortened, the starting complexity of the heterogeneous multi-core processor is reduced, the safety of the system is enhanced, other processors in the chip can replace the security core to complete starting operation, the reliability of the system is enhanced, the requirements for rich application scenes are met, and the application field is widened.

The utility model provides an interface circuit and a charging cabinet, which not only can meet the requirement of people for charging when the electric quantity of an electric appliance is insufficient when people go out, but also can supply power to more electric appliances at the same time. The interface circuit comprises a processor, a bus conversion chip, an identification interface and n slave modules, n is larger than or equal to 1, and when n is larger than 1, the first slave module to the nth slave module are sequentially connected. The slave module comprises a slave interface and a slave controller, the slave controller is provided with an expansion interface used for being connected with an external electric appliance, and the slave interface of the first slave module is used for establishing communication between the first slave module and the processor; the identification interface serves as a transfer end and receives and sends signals and communication data between the slave controller and the processor; the bus conversion chip is used for converting the type of communication data between the slave controller and the processor. The processor is used for communicating with the slave module, and when the slave module does not have the communication address, the processor allocates the communication address to the slave module.

Management of access to data stored in a storage system is provided, including allocation of a first storage processor as a master storage processor and allocation of a second storage processor as a slave storage processor. The master storage processor is configured to manage data storage operations on predefined memory portions of the storage system, and the slave storage processor is configured to manage data storage operations in response to a failure of the master storage processor. The management further includes detecting a failure of the first storage processor that interrupts management of the data storage operation, thereby, in response to the detection of the failure, allocating the second storage processor as a new primary storage processor configured to resume management of the operation, and allocating the third storage processor as a new slave processor configured to manage data storage operations on the predefined memory portion.

A method comprising: sending a first signal, comprising data about a task related to the operation of the first machine, by a first machine located in a workshop, to a storage medium to write a first event to an event log stored on the storage medium, wherein the event log is recognizable to each of a plurality of actors operating in the workshop, the first event corresponding to the task; reading the event log by each of the plurality of actors; sending one or more second signals to the storage medium by any one of the plurality of actors capable of performing the task to write one or more corresponding second events to the event log, wherein the one or more second signals comprise data indicating that the respective actor or actors are capable of performing the task;Determine, by a processor coupled to the storage medium, which of the plurality of actors is to be assigned the task, based on the one or more second events; and a) if only one first actor of the plurality of actors has sent the second signal to the storage medium: send a third signal, comprising data to write a third event to the event log, indicating that the task has been assigned to the first actor, by the processor to the storage medium; and read the event log by each of the plurality of actors, informing the first actor, based on the first actor's reading of the event log, that the task has been assigned to the first actor;and b) if at least two of the plurality of actors have sent at least two respective second signals to the storage medium: sending a fourth signal, comprising data to write a fourth event to the event log, indicating that the task has been assigned to one of the at least two actors, by the processor to the storage medium; and reading the event log by each of the plurality of actors, whereby, based on the reading of the event log by the at least two actors, one of the at least two actors is informed that the task has been assigned to said actor.

Systems for capturing and organizing team-generated content produced during a meeting defined / facilitated by a third-party meeting tool or service. In particular, a server system includes a memory allocation and a processor allocation configured to cooperate to instantiate an instance of a bridge service configured to communicably couple to API endpoints of the third-party meeting tool and to one or more collaboration tools. The bridge service can use meeting data obtained from a third-party meeting tool to obtain task information from a task management system for task associated with a current meeting being hosted by the third-party meeting tool. The bridge service can analyze the task information to determine a status of the tasks, and generate graphical summaries of the task associated with the event. The graphical summaries can be displayed to participants of the current meeting.

A method includes determining, by a processing device, an intended level of power consumption associated with a network function; allocating, in view of the intended level of power consumption, a network device to the network function; allocating, in view of the intended level of power consumption, a processor to the network function; and designating the processor to handle interrupts from the network function via the network device.

The invention discloses a server-free platform-oriented random workflow performance optimization method, which comprises a task random workflow sorting stage: according to a basic principle of a queuing theory model, performing arrival sorting on tasks of random workflows on the basis of an arrival sequence and a topological structure of the random workflows; in the instance parameter calculation stage, the blocking probability is calculated through an Erland B formula, the cold start probability is deduced, modeling is conducted through the semi-Markov process in the queuing theory, and performance indexes under the steady state condition are calculated through the parameters so as to evaluate the performance of the platform; and a system performance analysis stage: according to different task parameters, comprehensively analyzing the influence of the different task parameters on the performance of the function task, and based on the influence, giving out estimated resource overhead so as to realize cost minimization. According to the method, a processor distribution mode and constraint conditions are studied, and a demand processor combination prediction model is constructed by using a queuing theory model M / N / m / infinity for the problem of inaccurate prediction caused by strong uncertainty of a cloud center.

The embodiment of the present application provides a resource access method, a computing network and related equipment, which can realize flexible access between a processor and a computing card according to the demand of a computing service, and improves the utilization rate of computing resources. The method comprises the following steps: a management and control device sends a first resource allocation instruction to the computing card, the first resource allocation instruction carries first allocation information, and the first allocation information is used for instructing the computing card to allocate a first shared resource. The management and control device sends a second resource allocation instruction to the processor, the second resource allocation instruction carries second allocation information, and the second allocation information is used for instructing the processor to allocate a second shared resource. The management and control device receives a first shared message from the computing card, the first shared message carries first access information used for accessing the first shared resource. The management and control device sends a first access message to the processor, and the first access message is used for the second shared resource to access the first shared resource.

The application provides a computer system starting method and device, electronic equipment and storage medium, which can be applied to the technical field of computers. The method comprises the following steps: in the case that the computer system is powered on, performing a first initialization task; the first initialization task comprises performing an initialization configuration operation on a first device of the computer system; in the case that the first initialization task is completed, allocating device resources to a plurality of processors based on global resource information of the device resources, and determining local resource information of each of the plurality of processors; performing a plurality of second initialization tasks in parallel by using the plurality of processors, and determining initial resource allocation results of each of the plurality of processors; in the case that the plurality of second initialization tasks are all completed, performing resource uniformization adjustment according to the plurality of initial resource allocation results to obtain target resource allocation results; and in response to the completion of the resource adjustment, loading an operating system of the computer system to start the computer system.

Methods and apparatus of enhanced candidate allocation schemes for enhanced PDCCH are disclosed. The method includes: receiving, by a receiver, configurations of a plurality of search space sets that are linked for a Physical Downlink Control Channel (PDCCH) transmission with a plurality of repetitions; wherein the plurality of repetitions of the PDCCH are transmitted on a plurality of candidates; determining, by a processor, according to a priority rule with a predefined granularity, by counting the candidates from the linked search space sets, whether there is sufficient candidate resource available for allocation; and allocating, by the processor, the candidates, upon determining that there is sufficient candidate resource available for allocation.

A technique for allocating registers to a processor is provided. The technique includes identifying a first instruction in an instruction dispatch set that satisfies all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction in the instruction dispatch set that does not satisfy all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating registers for the second instruction.

An operating system running data collection method and an electric device. The operating system running data collection method comprises: allocating a ring buffer for a processor in a memory, and at least one event is recorded in the ring buffer; stopping recording and saving at least one event generated later than a reference time; wherein the reference time is the latest time of a first event. The scheme no longer needs periodic resource occupation, reduces the influence on service performance; at the same time, the latest time of the first event recorded in the ring buffer is taken as the reference, and events earlier than the time point are removed, so that the analysis exception caused by the loss of buffer data is avoided, and the data time window consistency is ensured; the scheme does not need to allocate a central buffer storage area, and the occupation of too much system memory is avoided.

Method for managing resource utilization for a system board (100) which has: multiple processors (102), memory allocated to each of the processors (102), several voltage regulators (106) designed to regulate voltages applied to the processors (102) and memory, and a board manager (108) trained to manage resources of the system board (100), the method comprising: Transmitting an operating status information from the board manager (108) to controllers (107) of the voltage regulators (106) independently of the processors (102), which also communicate with the controllers (107), wherein the operating status information received by each controller (107) specifies a computational load for the processor (102) which is controlled by the voltage regulator (106) controlled by the controller (107), and Controlling the voltage regulators (106) based on the operating state information to set the power limit of the voltage regulators (106) according to the processing load specified by the operating state information transmitted by the board manager (108) to the controllers (107) for each processor (102), and the procedure also features: Receiving telemetry information from the voltage regulators (106) by the board manager (108), wherein the telemetry information indicates an efficiency of the voltage regulators (106) for different power modes of the respective processors (102), and Generating an efficiency profile by the board manager (108) based on the telemetry information.

Systems and methods for using a logical block addressing (LBA) scatter list to calculate an address corresponding to an entry in the LBA scatter list are disclosed. A system may include a non-transitory memory including machine-readable instructions that, when executed by a processor, cause the processor to allocate an LBA scatter list array and send an initializing command to a target storage device to provide to the target storage device an address to the LBA scatter list array. The instructions cause the processor to gather a plurality of read requests and select an available LBA scatter list index. The instructions cause the processor to populate a LBA list indicated by the selected LBA scatter list index and send a subsequent command to the target storage device to cause the target storage device to calculate an address corresponding to a given entry in the selected LBA scatter list index.

This application relates to the field of artificial intelligence technology, and in particular to an inference control method, device configuration method, apparatus, device, medium, and product. The method involves using the communication interface type configured by the baseboard management controller as the target type, determining a pre-configured accelerator processor based on the target type, and constructing a detection driver adapted to the baseboard management controller and the pre-configured accelerator processor. The detection driver for the pre-configured accelerator processor is obtained, and the accelerator processor connected to the target communication port is detected using the detection driver. The detected accelerator processor is then designated as the target processor. The control unit of the target communication port assigns a device address to the target processor, thereby obtaining the port information combination of the target processor, and scheduling the target processor to execute inference tasks. This method solves the technical problem that the baseboard management controller cannot schedule the computing power of accelerator processors due to the lack of dedicated drivers, improves the efficiency of task scheduling for heterogeneous computing resources, and reduces inference latency.