Multi-ROM (Read Only Memory) quick starting method based on heterogeneous multi-core chip

Abstract

The invention relates to a multi-ROM (Read Only Memory) quick starting method based on a heterogeneous multi-core chip, the heterogeneous multi-core chip comprises a security core and at least one other processor, initialization codes of each processor are respectively stored in respective corresponding independent ROM, a user program and an operating system program are stored in FLASH, and after a system is powered on, the security core and at least one other processor can be started. The security core is started by default and executes a first starting process: reading a user program in the FLASH to the storage space allocated by each processor; when the security core executes the first startup process, the at least one other processor is started according to the configuration signal of the power management module and executes the second startup process. According to the method, the security core is used for overall starting, the starting time of the heterogeneous multi-core system can be shortened, the starting complexity of the heterogeneous multi-core processor is reduced, the safety of the system is enhanced, other processors in the chip can replace the security core to complete starting operation, the reliability of the system is enhanced, the requirements for rich application scenes are met, and the application field is widened.

Description

Technical Field

[0001] This invention belongs to the field of embedded system technology and relates to a fast boot method for multiple ROMs based on heterogeneous multi-core chips. Background Technology

[0002] As the demands of various application fields continue to increase, the requirements for embedded systems are also becoming more and more stringent. For example, in the field of aerospace applications, there are strict requirements for startup time. The usual method of starting one processor first and then having the first-started processor guide the other processors to start is slow and cannot meet the needs of some applications with high startup time requirements.

[0003] Traditional technology uses the method of booting the first processor to guide the boot of other processors. The main drawback of this method is that the boot time is slow, and if the first processor fails to boot due to design or manufacturing issues, the entire system will freeze, resulting in low reliability and security. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a multi-ROM fast boot method based on a heterogeneous multi-core chip. The heterogeneous multi-core chip includes a security core and at least one other processor. The initialization code of each processor is stored in its respective independent ROM, while the user program and operating system program are stored in FLASH memory. After the system is powered on, the security core starts by default and executes the first boot process: initializes the QSPI interface and configures the DMA controller, then reads the user program in the FLASH in parallel through the two channels of the QSPI interface to the storage space allocated to each processor in the chip, configures the boot address of each processor after the transfer is completed, and sets the flag of each processor in the boot control register to the first state. During the execution of the first boot process by the security core, at least one other processor starts up according to the configuration signal of the power management module and executes the second boot process: it starts executing initialization code from its respective independent ROM; after completing its own initialization, each other processor queries the power-on status of other processors in the system and makes a judgment based on the preset processor priority. If it is determined that there is a processor that is powered on and has a higher priority than itself, then the flag bit corresponding to itself in the boot control register is cyclically queried to see if it is in the first state. If it is found to be in the first state, the user program is executed by jumping to the boot address configured by the security core. If it determines that it is the highest priority processor among the currently powered-on processors, it will take over the security core and execute the first boot process.

[0005] Furthermore, after the chip's reset signal is released, the security core is configured by hardware to be the first device to start among all the master devices within the chip.

[0006] Furthermore, the operation of the security core to move the user program from FLASH in the first boot process overlaps at least partially in time with the operation of the other processors to execute the initialization code from their respective ROMs in the second boot process.

[0007] Furthermore, when the secure core malfunctions, other processors boot from their own ROM and replace the secure core to complete the boot process.

[0008] Furthermore, if the safety core malfunctions, it is bypassed and powered on again.

[0009] Furthermore, the other processors determine whether to be powered on based on the power management module. Specifically, the user instructs the power management module via an external pin of the chip to determine which processors need to be powered on.

[0010] Furthermore, the alternative security core completes the boot operation, including completing basic initialization, configuring DMA, moving the user program from FLASH to the boot address of each processor through two QSPI interfaces, and writing 1 to the corresponding bit of the boot control register.

[0011] Furthermore, after the security core is powered on and reset, it starts execution from the security core ROM and completes basic initialization.

[0012] Furthermore, after completing initialization, the other processors read the power-on status of the other processors.

[0013] Furthermore, the higher-priority processor includes the security core.

[0014] This invention is based on a heterogeneous multi-core system architecture, consisting of a secure core and other processors. It employs multi-ROM booting, with the secure core coordinating the boot process. This accelerates the boot time of the heterogeneous multi-core system. At the same time, the secure core's overall management reduces the complexity of booting heterogeneous multi-core processors and enhances system security. Other processors within the chip can replace the secure core to complete the boot operation, enhancing system reliability and meeting a wide range of application scenarios, thus broadening the application areas. Attached Figure Description

[0015] Figure 1 This is a diagram illustrating the chip startup process of the present invention. Detailed Implementation

[0016] To better understand the purpose, technical solution, and function of this invention, the invention will be described in further detail below with reference to the accompanying drawings. However, this invention can be implemented in many different ways as defined and covered by the claims. The accompanying drawings, which constitute a part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0017] To enable fast booting from multiple ROMs in a heterogeneous multi-core chip, each type of processor within the chip has its own ROM, and user programs are stored in FLASH memory. Except for the security core, the power-on signals of other processors are controlled by the power management module; they are not powered on by default. Users can instruct the power management module via external pins on the chip to specify which processors need to be powered on. The heterogeneous multi-core chip includes multiple master and slave modules interconnected via a system bus, where the security core and other processors are all master devices capable of actively initiating bus transactions.

[0018] like Figure 1 As shown, the multi-ROM boot process of the present invention is described as follows: 1. When the system is powered on, the security core starts by default. After the security core is powered on and reset, it starts executing from the security core ROM and completes basic initialization.

[0019] 2. After the system powers on, the power management module determines whether the processor is powered on. If the processor is powered on, execution begins from the processor's dedicated ROM after a reset. After initialization, the processor checks its power-on status. If a security core or other higher-priority processor is powered on, the system continuously checks the boot control register for a value of 0. If no higher-priority processor is powered on, the current processor will act as the security core to complete the boot process.

[0020] 3. If the secure core boots successfully, it configures DMA and uses two QSPI interfaces to move the user program from FLASH to the boot address of each processor. The two QSPI interfaces can move the program in parallel, improving boot efficiency. After the program is moved to each core, the secure core writes a 1 to the corresponding bit in the boot control register. If the secure core fails to boot, it is bypassed and powered on again.

[0021] 4. When other processors in the chip find that the corresponding bit in the boot control register is not 0, they will jump to the user program entry address and start executing the user program.

[0022] 5. Once all processors have started up, the chip startup is complete.

[0023] In this invention, on the one hand, heterogeneous multi-core processors can start execution and complete basic initialization from their own dedicated ROMs, allowing multiple cores to boot independently. Compared to the method of booting a single core and then guiding other cores to boot, this shortens the boot time. On the other hand, by reading the user program from the FLASH in parallel through two QSPI channels, the boot time is further shortened.

[0024] In this invention, the security core moves the user program to the boot address of each processor, and the security core manages the chip boot process in a unified manner, which simplifies the chip boot process and reduces the complexity of the system.

[0025] In this invention, the security core and other processors can be bypassed. When a processor fails to start normally due to process or design problems, the remaining processors in the system can also bootstrap and replace the security core to complete the chip boot process, thereby enhancing the reliability of the system.

[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art can make various changes or modifications within the scope of the claims, all of which should be included within the protection scope of the present invention.

Claims

1. A method for fast booting of multiple ROMs based on heterogeneous multi-core chips, characterized in that, The heterogeneous multi-core chip includes a security core and at least one other processor. The initialization code for each processor is stored in its respective independent ROM, while the user program and operating system program are stored in FLASH. After the system is powered on, the security core starts by default and executes the first boot process: initializes the QSPI interface and configures the DMA controller, then reads the user program in the FLASH in parallel through the two channels of the QSPI interface to the storage space allocated to each processor in the chip, configures the boot address of each processor after the transfer is completed, and sets the flag of each processor in the boot control register to the first state. During the execution of the first boot process by the security core, at least one other processor starts up according to the configuration signal of the power management module and executes the second boot process: it starts executing initialization code from its respective independent ROM; after completing its own initialization, each other processor queries the power-on status of other processors in the system and makes a judgment based on the preset processor priority. If it is determined that there is a processor that is powered on and has a higher priority than itself, then the flag bit corresponding to itself in the boot control register is cyclically queried to see if it is in the first state. If it is found to be in the first state, the user program is executed by jumping to the boot address configured by the security core. If it determines that it is the highest priority processor among the currently powered-on processors, it will take over the security core and execute the first boot process.

2. The method according to claim 1, characterized in that, After the chip's reset signal is released, the security core is configured by hardware to be the first device to start among all the master devices within the chip.

3. The method according to claim 1, characterized in that, The operation of the security core to move the user program from FLASH in the first boot process overlaps at least partially in time with the operation of the other processors to execute the initialization code from their respective ROMs in the second boot process.

4. The method according to claim 1, characterized in that, When the secure core malfunctions, other processors boot from their own ROM and take over the boot process from the secure core.

5. The method according to claim 4, characterized in that, When the safety core malfunctions, it is bypassed and then powered on again.

6. The method according to claim 1, characterized in that, The other processors determine whether to be powered on based on the power management module. Specifically, the user instructs the power management module via an external pin on the chip to determine which processors need to be powered on.

7. The method according to claim 1, characterized in that, The alternative security core completes the boot operation, including basic initialization, DMA configuration, moving the user program from FLASH to the boot address of each processor through two QSPI interfaces, and writing 1 to the corresponding bit of the boot control register.

8. The method according to claim 1, characterized in that, After the security core is powered on and reset, it starts execution from the security core ROM and completes basic initialization.

9. The method according to claim 1, characterized in that, After completing initialization, the other processors read the power-on status of the other processors.

10. The method according to claim 1, characterized in that, The higher-priority processor includes the security core.

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