Instruction cache management method, instruction cache, computing device and system

By downsampling the original age value of cache lines in the instruction cache, a baseline age value is obtained, which solves the failure problem of the LRU replacement strategy in the parallel access environment of high-performance computing devices and achieves more efficient cache management.

CN122018985BActive Publication Date: 2026-07-24SHANGHAI BIREN TECH CO LTD
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Patent Information

Application Number
CN202610478146.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-04-13
Publication Date
2026-07-24
Estimated Expiration
2046-04-13

AI Technical Summary

Technical Problem

In high-performance computing devices, LRU-based instruction cache replacement strategies are prone to failure in parallel access environments, leading to unfairness and reduced efficiency in the replacement strategy.

Method used

By downsampling the original age value of the cache line in the instruction cache, a baseline age value is obtained, and this baseline age value is used to replace the original age value to represent the replacement priority of the cache line, thereby reducing the risk of replacement strategy failure.

Benefits of technology

This effectively alleviates the problem of the cache line baseline age value growing too quickly to the upper limit due to hot access, ensuring the effectiveness and fairness of the replacement strategy in a concurrent access environment.

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Abstract

The present disclosure relates to an instruction cache management method, an instruction cache, a computing device and a system, for reducing the risk of long time invalidation of LRU replacement policy. The method comprises: receiving a memory access request for the instruction cache; determining a target cache group mapped by the memory access request, and detecting whether a target instruction indicated by the memory access request exists in the target cache group; in the case that the target instruction is absent in the target cache group and the target cache group is full, selecting a target cache line to be replaced from the target cache group based on reference age values of each cache line in the target cache group; wherein the reference age value of the cache line is obtained by down-sampling an original age value of the corresponding cache line by a set sampling step, the original age value representing the number of consecutive misses of the corresponding cache line, and the reference age value representing the replacement priority of the corresponding cache line in the target cache group; and reading the target instruction from a lower-level memory of the instruction cache and writing the target instruction into the target cache line.
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