Non-volatile memory device, storage device including the same, and operating method thereof

Abstract

A method of operating a non-volatile memory device includes receiving a suspend command at the non-volatile memory device, suspending a programming operation being performed at the non-volatile memory device in response to the suspend command, receiving a resume command at the non-volatile memory device, and resuming the suspended programming operation at the non-volatile memory device in response to the resume command. The programming operation includes programming cycles, each of the programming cycles including a bit line set interval, a program interval, and a verify interval. A level of a program voltage to be applied to selected memory cells of the non-volatile memory device is increased by a first voltage in the program interval of each of the programming cycles. A difference between a level of a program voltage last applied before the suspension and a level of a program voltage first applied after the resume is different from the first voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0053180, filed on May 4, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of the present invention relate to an electronic device, and more specifically, to a non-volatile memory device that supports programming operations with improved reliability and flexibility, a storage device including the non-volatile memory device, and a method of operating the non-volatile memory device. Background Technology

[0004] Non-volatile memories include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0005] Typically, programming non-volatile memory devices takes longer than reading them. During programming operations, emergency access events may occur. For example, an emergency write or read of data from a non-volatile memory device may happen.

[0006] If emergency access is delayed until the programming operation is completed, the non-volatile memory device may be considered to not support emergency access. If the programming operation is paused and emergency access is supported, data associated with the programming operation may be lost. Therefore, the non-volatile memory device may be considered to have low reliability. Summary of the Invention

[0007] An exemplary embodiment of the present invention provides a non-volatile memory device with flexibility to support emergency access and improved reliability, a storage device including the non-volatile memory device, and a method of operating the non-volatile memory device.

[0008] According to an example embodiment, an operation method for a non-volatile memory device includes: receiving a pause command at the non-volatile memory device; pausing a programming operation being performed at the non-volatile memory device in response to the pause command; receiving a resume command at the non-volatile memory device; and resuming the paused programming operation at the non-volatile memory device in response to the resume command. The programming operation includes a programming loop, each of which includes a bit line setup interval, a programming interval, and a verification interval. During the programming interval of each programming loop, the level of the programming voltage to be applied to a selected memory cell of the non-volatile memory device is increased by a first voltage. The difference between the level of the programming voltage finally applied to the selected memory cell before pausing the programming operation and the level of the programming voltage initially applied to the selected memory cell after resuming the paused programming operation corresponds to a second voltage different from the first voltage.

[0009] According to an example embodiment, a non-volatile memory device includes: a memory cell array including memory cells; a row decoder connected to the memory cells via word lines, which applies a programming voltage to a word line selected from the word lines during a programming interval in each programming cycle of a programming operation, and applies a verification voltage to the selected word line during a verification interval in each programming cycle; a page buffer connected to the memory cells via bit lines, which applies a voltage to the bit lines during a bit line setting interval in each programming cycle of a programming operation; and control logic that controls the row decoder and page buffer in response to a programming command, causing a programming operation to be initiated. During the programming interval of each programming cycle, the row decoder increases the level of the programming voltage applied to the selected word line by a first voltage. The control logic controls the row decoder and page buffer to pause the programming operation in response to a pause command and resume the paused programming operation in response to a resume command. The difference between the level of the programming voltage finally applied to the selected word line before the programming operation is paused and the level of the programming voltage initially applied to the selected word line after the paused programming operation is resumed corresponds to a second voltage different from the first voltage.

[0010] According to an example embodiment, a storage device includes: a non-volatile memory device including memory cells; and a controller that sends a write command associated with a memory cell selected from the memory cells to the non-volatile memory device, sends a pause command to the non-volatile memory device to pause the write command before completing a programming operation, and sends a resume command to the non-volatile memory device to resume the write command. In response to the write command, the non-volatile memory device repeatedly applies a programming voltage to the selected memory cell while increasing the programming voltage by a first increment. The controller sends information about a second increment of the programming voltage to be applied to the selected memory cell along with the resume command to the non-volatile memory device. The non-volatile memory device increases the programming voltage by the second increment in response to the resume command. Attached Figure Description

[0011] The above and other objects and features of the present invention will become apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating an example embodiment of a non-volatile memory device according to a concept of the present invention.

[0013] Figure 2 An example of performing a programming operation is shown.

[0014] Figure 3 An example of pausing and resuming programming operations is shown.

[0015] Figure 4 A first example of an operation method for a non-volatile memory device according to an exemplary embodiment of the present invention is shown.

[0016] Figure 5 The first example shown is applying a programming voltage to a selected word line during a programming operation.

[0017] Figure 6 A second example is shown where a programming voltage is applied to a selected word line during a programming operation.

[0018] Figure 7 A second example of an operation method for a non-volatile memory device according to an exemplary embodiment of the present invention is shown.

[0019] Figure 8 A third example is shown where a programming voltage is applied to a selected word line during a programming operation.

[0020] Figure 9 Another example of pausing and resuming programming operations is shown.

[0021] Figure 10This is a block diagram of a non-volatile memory device according to an exemplary embodiment of the present invention.

[0022] Figure 11 It shows Figure 10 Examples of operating methods for non-volatile memory devices.

[0023] Figure 12 It shows that it can be used as Figure 10 Examples of machine learning logic in neural networks.

[0024] Figure 13 It is shown Figure 1 or Figure 10 A circuit diagram of an example memory block within a memory block.

[0025] Figure 14 A storage device according to an example embodiment of the present invention is shown.

[0026] Figure 15 It shows Figure 14 An example of how to operate a storage device.

[0027] Figure 16 This is a diagram illustrating an example non-volatile memory device. Detailed Implementation

[0028] Below, exemplary embodiments of the present invention will be described in detail and clearly to the extent that those skilled in the art can readily implement the present invention.

[0029] Figure 1 This is a block diagram illustrating an example embodiment of a non-volatile memory device 100 according to a concept of the present invention. (See reference) Figure 1 The non-volatile memory device 100 includes a memory cell array 110, a line decoder block 120, a page buffer block 130, a pass / fail check (PFC) block 140, a data input and output block 150, a buffer block 160, and / or a control logic block 170.

[0030] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each of memory blocks BLK1 to BLKz includes multiple memory cells. Each of memory blocks BLK1 to BLKz can be connected to line decoder block 120 via one or more ground select lines GSL, word lines WL, and one or more serial select lines SSL. Some of the word lines WL can be used as virtual word lines. Each of memory blocks BLK1 to BLKz can be connected to page buffer block 130 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be connected together with multiple bit lines BL.

[0031] In the example embodiment, each of the plurality of memory blocks BLK1 to BLKz can be a unit of erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz can be erased simultaneously. Alternatively, each of the plurality of memory blocks BLK1 to BLKz can be divided into multiple sub-blocks. Each of the multiple sub-blocks can correspond to a unit of erase operation.

[0032] The row decoder block 120 is connected to the memory cell array 110 via the ground select line GSL, the word line WL, and the serial select line SSL. The row decoder block 120 operates under the control of the control logic block 170.

[0033] The line decoder block 120 can decode the line address RA received from the buffer block 160, and can control the voltage to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded line address.

[0034] Page buffer block 130 is connected to memory cell array 110 via multiple bit lines BL. Page buffer block 130 is connected to data input and output block 150 via multiple data lines DL. Page buffer block 130 operates under the control of control logic block 170.

[0035] During programming operations, page buffer block 130 can store data to be written to memory cells. Page buffer block 130 can apply voltages to multiple bit lines BL based on the stored data. During read operations or verification read operations performed during programming or erasing operations, page buffer block 130 can sense the voltage of bit lines BL and store the sensing results.

[0036] In a verification read operation associated with a programming or erasing operation, pass / fail check block 140 can verify the sensing results of page buffer block 130. For example, in a verification read operation associated with a programming operation, pass / fail check block 140 can count the number of values ​​(e.g., 0) corresponding to on-cells that are not programmed to a target threshold voltage or higher.

[0037] In the verification read operation associated with the erase operation, the pass / fail check block 140 can count the number of values ​​(e.g., 1) corresponding to off-cells that were not erased to a target threshold voltage or lower. When the count result is the threshold or higher, the pass / fail check block 140 can output a failure signal to the control logic block 170. When the count result is less than the threshold, the pass / fail check block 140 can output a pass signal to the control logic block 170. A programming loop for programming operations or an erase loop for erasing operations can be further executed based on the verification result of the pass / fail check block 140.

[0038] Data input / output block 150 is connected to page buffer block 130 via multiple data lines DL. Data input / output block 150 can receive column address CA from buffer block 160. Data input / output block 150 can output data read from page buffer block 130 to buffer block 160 based on column address CA. Data input / output block 150 can also provide data received from buffer block 160 to page buffer block 130 based on column address CA.

[0039] Buffer block 160 can receive commands CMD and addresses ADDR from external devices via the first channel CH1, and can exchange data "DATA" with external devices. Buffer block 160 can operate under the control of control logic block 170. Buffer block 160 can provide commands CMD to control logic block 170. Buffer block 160 can provide the row address RA of address ADDR to row decoder block 120, and can provide the column address CA of address ADDR to data input and output block 150. Buffer block 160 can exchange data "DATA" with data input and output block 150.

[0040] Control logic block 170 can exchange control signals CTRL from external devices via the second channel CH2. Control logic block 170 can allow buffer block 160 to route commands CMD, addresses ADDR, and data "DATA". Control logic block 170 can decode commands CMD received from buffer block 160 and can control non-volatile memory device 100 based on the decoded commands.

[0041] Control logic block 170 may include counter 171 and / or table 172. Under the control of control logic block 170, counter 171 can count the time elapsed from a specific point in time. Table 172 can store parameters according to the elapsed time. Control logic block 170 can improve the reliability of programming operations that support pause and resume functions (or schemes or operations) by using counter 171 and table 172.

[0042] In an example embodiment, the non-volatile memory device 100 can be fabricated in a bonding manner. The memory cell array 110 can be fabricated on a first wafer, and the line decoder block 120, page buffer block 130, data input and output block 150, buffer block 160, and control logic block 170 can be fabricated on a second wafer. The non-volatile memory device 100 can be implemented by coupling the first and second wafers such that the upper surfaces of the first and second wafers face each other.

[0043] For example, the non-volatile memory device 100 can be fabricated in a Cell Over Peri (COP) configuration. Peripheral circuitry, including a line decoder block 120, a page buffer block 130, a data input and output block 150, a buffer block 160, and a control logic block 170, can be implemented on the substrate. The memory cell array 110 can be implemented on the peripheral circuitry. The peripheral circuitry and the memory cell array 110 can be connected using vias.

[0044] Figure 2 An example of performing a programming operation is shown. Figure 2 In the diagram, the horizontal axis represents time "T", and the vertical axis represents voltage "V". Figure 2 The image shows an example of the voltage to be applied to a word line selected from word line WL during a programming operation.

[0045] refer to Figure 1 and Figure 2 Programming operations can include multiple programming loops. In an example embodiment, in Figure 2 The diagram shows the first programming loop LOOP1 to the third programming loop LOOP3. However, the number of programming loops is not limited to "3".

[0046] Each of the programming loops LOOP1 through LOOP3 may include a bit line setup interval I_BLS, a programming interval I_PGM, and a verification interval I_VFY. In the bit line setup interval I_BLS, the voltage of the bit line BL can be set. For example, the bit line BL may be connected to a selected memory cell (e.g., a memory cell for a programming operation) connected to a selected word line.

[0047] Programming voltage (e.g., power supply voltage) can be applied to the bit line connected to the memory cell in the selected memory cell whose threshold voltage is to be increased (or programmed). Programming disable voltage (e.g., ground voltage or a voltage similar to ground voltage) can be applied to the bit line connected to the memory cell in the selected memory cell whose threshold voltage is to be maintained (or programmed disable).

[0048] During the programming interval I_PGM, a voltage VPASS can be applied to the word line WL. The VPASS voltage turns on the memory cell connected to the word line WL. Afterwards, a programming voltage VPGM can be applied to the selected word line. The programming voltage VPGM allows the threshold voltage of the memory cell to be programmed to increase.

[0049] Within the verification interval I_VFY, the verification voltage VFY can be applied to the selected word line. For example, when programming two bits in a memory cell, the threshold voltage of the memory cell can be adjusted to one of the three programming states through the programming operation, or it can be kept in the erase state. That is, the threshold voltage of the memory cell can belong to either the erase state or one of the three programming states. The verification voltage VFY can include three voltages corresponding to the three programming states respectively.

[0050] For example, when programming "n" bits (n is a positive integer) into a memory cell, the threshold voltage of the memory cell can be adjusted to the erase state and (2) through the programming operation. n -1) one of the programming states, or it can be held. The verification voltage VFY can include those corresponding to (2) n -1) programming states (2 n -1) voltage.

[0051] Programming operations can be performed by repeating a programming loop. When the programming loop is in progress (repeated), the level of the programming voltage VPGM can be increased by a first voltage ΔV1.

[0052] During programming operations, an emergency access event to the non-volatile memory device 100 may occur. The non-volatile memory device 100 according to an exemplary embodiment of the present invention can support pausing and resuming programming operations to enable emergency access functionality while programming operations are being performed.

[0053] exist Figure 2 An example is shown where the verification voltage VFY is applied in descending order from highest to lowest value. However, the order in which the verification voltage VFY is applied may not be related to the level of the verification voltage VFY. Alternatively, the verification voltage VFY can be applied in ascending order from lowest to highest value.

[0054] Figure 3 An example of pausing and resuming programming operations is shown. Figure 3 The diagram shows the signals received / transmitted by the non-volatile memory device 100 as a control signal CTRL through the first channel CH1, the internal operation IOP of the non-volatile memory device 100, and the ready / busy signal RnB output by the non-volatile memory device 100 through the second channel CH2.

[0055] When the internal operation IOP of the non-volatile memory device 100 is not executed, the non-volatile memory device 100 can set the ready / busy signal RnB to a high level indicating a ready state. When the ready / busy signal RnB is high, an external device (e.g., a controller) of the non-volatile memory device 100 can send a request to the non-volatile memory device 100.

[0056] For example, the non-volatile memory device 100 can receive a first request R1 from an external device. The first request R1 may include a first command CMD1, a first address ADDR1, and first data DATA1. The first command CMD1 may be a write command. In response to receiving the first request R1, the non-volatile memory device 100 can set the ready / busy signal RnB to a busy state, i.e., a low level.

[0057] In response to the first request R1, the non-volatile memory device 100 can begin the first operation, namely the programming operation. Because the non-volatile memory device 100 supports the function of pausing and resuming the programming operation, the non-volatile memory device 100 can begin the first operation and can set the ready / busy signal RnB to the ready state.

[0058] Before completing the first operation, the non-volatile memory device 100 may receive a second request R2 from an external device. The second request R2 may include a second command CMD2. The second command CMD2 may be a pause command. The non-volatile memory device 100 may perform a pause operation SUS in response to the second request R2. When performing the pause operation SUS based on the second request R2, the non-volatile memory device 100 may set the ready / busy signal RnB to a busy state.

[0059] The pause operation SUS may include storing (or backing up) the progress information of the first operation. The progress information of the first operation may include data (e.g., programming progress data) that is updated (or obtained) by applying the verification result of the programming operation of the selected memory cell to the first data DATA1 loaded into the page buffer block 130.

[0060] The progress information for the first operation may also include the number of programming cycles executed, the level of the final applied programming voltage VPGM, and information about the fully programmed state in the programming state. The progress information for the first operation may also include information about the interval during which the pause operation SUS was executed in the bit line setup interval I_BLS, programming interval I_PGM, and verification interval I_VFY of the programming cycle.

[0061] The progress information of the first operation can be stored (or updated) in the internal storage of the non-volatile memory device 100. The pause operation SUS may also include resetting (or initializing) the page buffer block 130 after storing (or backing up) the progress information.

[0062] When the pause operation SUS is completed, the non-volatile memory device 100 can set the ready / busy signal RnB to the ready state. After the ready / busy signal RnB is set to the ready state, the non-volatile memory device 100 can receive a third request R3 from an external device.

[0063] The third request R3 may include a third command CMD3, a third address ADDR3, and second data DATA2. In an example embodiment, the third command CMD3 may be a write command. Alternatively, the third request R3 may include the third command CMD3 and the third address ADDR3. In an example embodiment, the third command CMD3 may be a read command.

[0064] The non-volatile memory device 100 can perform a second operation in response to a third request R3. In an example embodiment, when performing the second operation, the non-volatile memory device 100 can keep the ready / busy signal RnB in a busy state. Alternatively, the non-volatile memory device 100 can support multiple pause-resume functions. In an example embodiment, when performing the second operation, the non-volatile memory device 100 can set the ready / busy signal RnB to a ready state. When performing the second operation, the non-volatile memory device 100 can receive additional pause commands.

[0065] When the second operation is completed, the non-volatile memory device 100 can set the ready / busy signal RnB to the ready state. Alternatively, if the non-volatile memory device 100 supports multiple pause-resume functions, the non-volatile memory device 100 can notify an external device that the second operation has been completed by allowing the ready / busy signal RnB to sequentially transition from ready to busy and from busy to ready.

[0066] Before completing the second operation, the non-volatile memory device 100 may receive a fourth request R4 from an external device. The fourth request R4 may include a fourth command CMD4. The fourth command CMD4 may be a recovery command. The non-volatile memory device 100 may perform a recovery operation RES in response to the fourth request R4. When performing the recovery operation RES, the non-volatile memory device 100 may set the ready / busy signal RnB to a busy state.

[0067] The recovery operation RES may include loading progress information of the first operation. The recovery operation RES may include loading programming progress data into page buffer block 130. Furthermore, the recovery operation RES may include setting parameters for the programming loop based on the progress information of the first operation. Setting the parameters for the programming loop may include setting the level of the programming voltage VPGM or setting the interval to be recovered within the programming loop interval.

[0068] In the example embodiment, the interval of the programming cycle executing the pause operation SUS can be resumed in the resume operation RES. Alternatively, regardless of the interval of the programming cycle executing the pause operation SUS, the first programming cycle can begin in the resume operation RES.

[0069] When the recovery operation RES is completed, the non-volatile memory device 100 can resume the first operation. The first operation can be resumed, and the non-volatile memory device 100 can set the ready / busy signal RnB to a ready state. In an example embodiment, when the first operation is completed, the non-volatile memory device 100 can notify an external device that the first operation has been completed by allowing the ready / busy signal RnB to sequentially have ready-to-busy transitions and busy-to-ready transitions.

[0070] An external device can determine whether the non-volatile memory device 100 supports pause and resume functionality. When it is determined that the non-volatile memory device 100 supports pause and resume functionality, the external device can determine whether the non-volatile memory device 100 is in a ready state where no command is currently being executed or in a ready state that supports pause and resume functionality. When it is determined that the non-volatile memory device 100 is in a ready state that supports pause and resume functionality, the external device can sequentially input pause commands, access commands, and resume commands to the non-volatile memory device 100.

[0071] The example is described as a non-volatile memory device 100 receiving a second command CMD2 as a pause command. However, the non-volatile memory device 100 can be configured to perform a pause operation SUS in response to receiving a read command while performing a programming operation, and to perform a read operation.

[0072] Furthermore, the example is described as a non-volatile memory device 100 receiving a fourth command CMD4 as a recovery command. However, the non-volatile memory device 100 can be configured to perform a recovery operation RES in response to the completion of a read operation, and to resume the programming operation.

[0073] exist Figure 3In this context, the time from the start of the pause operation SUS to the completion of the recovery operation RES can be called the recovery time tRES. After a portion of the programming operation is performed, the selected memory cell can be left alone during the recovery time tRES. While the selected memory cell is left alone, its threshold voltage can be changed (or stabilized).

[0074] When resuming programming operations, such as Figure 2 As shown, when the programming voltage VPGM is increased by a first voltage ΔV1, the distribution of threshold voltages of the selected memory cells can increase due to the change in threshold voltages during the recovery time tRES. This may lead to an increase in read errors, i.e., a decrease in the reliability of the non-volatile memory device 100.

[0075] The non-volatile memory device 100 of the exemplary embodiment of the present invention can adjust (or set) the parameters of the programming cycle based on the change of the threshold voltage during the recovery time tRES. Therefore, the reliability of the non-volatile memory device 100 may be reduced or prevented from being reduced due to the individual delay during the recovery time tRES.

[0076] Figure 4 A first example of an operation method for a non-volatile memory device 100 according to an exemplary embodiment of the present invention is shown. (Reference) Figure 1 and Figure 4 In operation S110, the non-volatile memory device 100 can receive a pause command. For example, the non-volatile memory device 100 can receive a pause command when a programming operation is performed in response to a write command.

[0077] In operation S120, the non-volatile memory device 100 can pause the programming operation. In operation S130, the non-volatile memory device 100 can begin counting the recovery time tRES using counter 171. Operations S120 and S130 can be executed simultaneously, in parallel, sequentially, or in reverse.

[0078] In operation S140, the non-volatile memory device 100 can determine whether a recovery command has been received. The non-volatile memory device 100 can wait until a recovery command is received. When a recovery command is received, the non-volatile memory device 100 can execute operation S150.

[0079] In operation S150, the non-volatile memory device 100 can adjust the programming operation voltage based on the recovery time tRES. For example, the non-volatile memory device 100 can adjust the programming voltage VPGM based on the recovery time tRES. Table 172 can store information about a second voltage ΔV2 corresponding to the recovery time tRES. The non-volatile memory device 100 can adjust the second voltage ΔV2 by referring to Table 172.

[0080] Until a resume command is received after the programming operation has been paused, the non-volatile memory device 100 can perform one or more operations in response to a request from an external device. Figure 4 The main focus is on the operation of the non-volatile memory device 100 associated with the pause and resume functions; therefore, descriptions of the operations(s) performed in response to requests from external devices while pausing programming operations are omitted.

[0081] Figure 5 This illustrates a first example of applying the programming voltage VPGM to a selected word line during a programming operation. Figure 5 An example embodiment of applying the programming voltage VPGM during the above pause and resume operations is shown. Figure 5 In the diagram, the horizontal axis represents time "T" and the vertical axis represents voltage "V".

[0082] refer to Figure 1 and Figure 5 When a programming cycle is executed during a programming operation, the programming voltage VPGM can be increased by a first voltage ΔV1. In the case of pause and resume operations, the programming voltage VPGM may not be applied to the selected word line during the resume time tRES.

[0083] After the recovery time tRES has elapsed, the programming cycle can be executed again. The difference between the programming voltage VPGM initially applied after the programming operation resumes and the programming voltage VPGM finally applied before the programming operation is paused can be a second voltage ΔV2. The second voltage ΔV2 can be equal to or less than the first voltage ΔV1. In the example embodiment, the second voltage ΔV2 can be adjusted based on the recovery time tRES.

[0084] As the recovery time tRES increases, the second voltage ΔV2 can decrease. As the recovery time tRES decreases, the second voltage ΔV2 can increase. Figure 5 The second voltage ΔV2, marked by the dashed box, can be determined within the range from "0" to the first voltage ΔV1. By decreasing the increment of the programming voltage VPGM as the recovery time tRES increases, the spread of the threshold voltage distribution of memory cells left alone during the recovery time tRES can be suppressed.

[0085] After resuming the programming operation, when the programming voltage VPGM is applied for the second time, the increment of the programming voltage VPGM can return to the first voltage ΔV1. That is, when executing the programming cycle, the programming voltage VPGM can be increased from the previous level by the first voltage ΔV1.

[0086] In an example embodiment, the second voltage ΔV2 can be further adjusted based on the progress information of the programming operation. For example, the second voltage ΔV2 can be further adjusted based on at least one of the number of programming loops that have been executed, the level of the final applied programming voltage VPGM, and information about the fully programmed state in the programming state.

[0087] Furthermore, the second voltage ΔV2 can be further adjusted based on information about the interval during which the pause operation SUS is executed within the bitline setting interval I_BLS, programming interval I_PGM, and verification interval I_VFY of the programming cycle. The second voltage ΔV2 can also be further adjusted based on the physical location of the selected memory cell.

[0088] In an example embodiment, the second voltage ΔV2 can be further adjusted based on external information provided from an external device, such as the number of programming and erasing cycles associated with the selected memory cell and the temperature. For example, external information can be received from an external device along with a pause or resume command.

[0089] Figure 6 A second example is shown where the programming voltage VPGM is applied to a selected word line during programming operations. Figure 6 An example embodiment of applying the programming voltage VPGM during the above pause and resume operations is shown. Figure 6 In the diagram, the horizontal axis represents time "T" and the vertical axis represents voltage "V".

[0090] and Figure 5 In contrast, after resuming the programming operation, the increment of the programming voltage VPGM can gradually return to the first voltage ΔV1. For example, the increment of the programming voltage VPGM initially applied after resuming the programming operation can be determined as the second voltage ΔV2 based on the recovery time tRES.

[0091] After resuming the programming operation, the increment of the second applied programming voltage VPGM can be returned to the third voltage ΔV3. The third voltage ΔV3 can be greater than the second voltage ΔV2 and less than the first voltage ΔV1. After resuming the programming operation, the increment of the third applied programming voltage VPGM can be the first voltage ΔV1.

[0092] exist Figure 6An example is shown where the increment of the programming voltage VPGM returns from the second voltage ΔV2 to the first voltage ΔV1 in two steps. However, the number of steps required to return the increment of the programming voltage VPGM and the level to which the programming voltage VPGM returns are not limited to the example above.

[0093] For example, the increment of the programming voltage VPGM can increase a given voltage level. In an example embodiment, the increment of the programming voltage VPGM can be returned to a first voltage ΔV1 by steps, where the number of steps corresponds to the value obtained by subtracting the second voltage ΔV2 from the first voltage ΔV1 and dividing by the given voltage level.

[0094] For example, the increment of the programming voltage VPGM can be returned to the first voltage ΔV1 by a given number of steps. In an example embodiment, the programming voltage VPGM can be increased to a voltage level corresponding to a value obtained by dividing the value of the first voltage ΔV1 minus the value of the second voltage ΔV2 by a determined number.

[0095] For example, the increment of the programming voltage VPGM and the number of steps can be determined based on the recovery time tRES, progress information, and at least a portion of the second voltage ΔV2.

[0096] Figure 7 A second example of an operation method for a non-volatile memory device 100 according to an exemplary embodiment of the present invention is shown. (Refer to...) Figure 1 and Figure 7 Operations S210 to S240 and Figure 4 Operations S110 through S140 are the same. Therefore, additional descriptions will be omitted to avoid redundancy.

[0097] When the programming operation resumes, in operation S250, the non-volatile memory device 100 can perform verification on the selected memory cell. Verification can be performed using the verification voltage that was finally applied to the selected memory cell before the programming operation was paused.

[0098] In operation S260, the non-volatile memory device 100 can adjust the voltage of the programming operation based on the recovery time tRES and the verification result. For example, the non-volatile memory device 100 can compare programming progress data and verification results, and can detect changes in the threshold voltage of the selected memory cell. In addition to the recovery time tRES, the non-volatile memory device 100 can also adjust the voltage of the programming operation based on the detected changes.

[0099] Figure 8 A third example is shown where the programming voltage VPGM is applied to a selected word line during programming operations. Figure 8An example embodiment of applying the programming voltage VPGM during the above pause and resume operations is shown. Figure 8 In the diagram, the horizontal axis represents time "T" and the vertical axis represents voltage "V".

[0100] and Figure 5 Compared to the example, when resuming the programming operation, a verification voltage VFY can be applied to the selected word line. The second voltage ΔV2 can be adjusted based on the recovery time tRES and the verification result. In the example embodiment, the second voltage ΔV2 can be determined within the range of negative voltage -ΔV1 to positive voltage ΔV1.

[0101] The example of a negative second voltage ΔV2 can be applied to... Figure 5 and Figure 6 Example. See reference. Figure 6 The increment of the programming voltage VPGM after the programming operation is restored can be returned from the second voltage ΔV2 to the first voltage ΔV1 through multiple steps.

[0102] Figure 9 Another example of performing pause and resume operations in programming loops LOOP1 through LOOP3 is shown. (Reference) Figure 1 and Figure 9 In each of the programming cycles LOOP1 to LOOP3, the programming voltage VPGM can have two or more different levels.

[0103] Different levels of the programming voltage VPGM can be applied to memory cells to be programmed into different programming states. For example, a high level of the programming voltage VPGM can be applied to memory cells to be programmed into the first and second programming states. A low level of the programming voltage VPGM can be applied to memory cells to be programmed into the third programming state.

[0104] In an example embodiment, different levels of the programming voltage VPGM can be applied together to a memory cell to be programmed into at least one programming state. For example, a high level of the programming voltage VPGM can be applied to memory cells to be programmed into first and second programming states. A low level of the programming voltage VPGM can be applied to memory cells to be programmed into second and third programming states.

[0105] When the programming cycle is executed, a low level of the programming voltage VPGM can increase the voltage by a first increment ΔV1. When the programming cycle is executed, a high level of the programming voltage VPGM can increase the voltage by a second increment ΔV2. In the example embodiment, the first increment ΔV1 can be equal to or greater than the second increment ΔV2.

[0106] like Figure 9As shown, programming can be paused after executing the first programming loop (LOOP1) and the second programming loop (LOOP2). Then, the third programming loop (LOOP3) can be resumed. In the third programming loop (LOOP3), the low level of the programming voltage VPGM can be increased by a third increment ΔV3 from the level of the second programming loop (LOOP2). The high level of the programming voltage VPGM can be increased by a fourth increment ΔV4 from the level of the second programming loop (LOOP2). The third increment ΔV3 can be equal to or greater than the fourth increment ΔV4.

[0107] For reference Figure 5 , Figure 6 and Figure 8 The third increment ΔV3 can be equal to or less than the first increment ΔV1. The third voltage ΔV3 can have a negative value. The increment of the low level of the programming voltage VPGM can be gradually returned. For example, the increment of the low level of the programming voltage VPGM can start from the third increment ΔV3, then increase to at least one of the increments between the third increment ΔV3 and the first increment ΔV1, and then return to the first increment ΔV1.

[0108] For reference Figure 5 , Figure 6 and Figure 8 The fourth increment ΔV4 can be equal to or less than the second increment ΔV2. The fourth increment ΔV4 can be negative. The increment of the high level of the programming voltage VPGM can be gradually reduced. For example, the increment of the high level of the programming voltage VPGM can start from the fourth increment ΔV4, then increase to at least one of the increments between the fourth increment ΔV4 and the second increment ΔV2, and then return to the second increment ΔV2.

[0109] exist Figure 9 An example is shown where the programming voltage VPGM includes two different levels, but the programming voltage VPGM can include three or more different levels.

[0110] exist Figure 9 An example is shown where the programming voltage VPGM is applied in descending order from the highest level to the lowest level. However, as shown in the reference... Figure 2 As stated in the verification voltage VFY, the order in which the programming voltage VPGM is applied can be changed. Furthermore, the verification voltage VFY can be applied in various orders.

[0111] In the example embodiment, a description is given of the programming voltage VPGM including different levels. However, the technical concept of the present invention can be understood as applying programming voltages of different levels within the programming interval I_PGM.

[0112] Figure 10This is a block diagram illustrating an example embodiment of a non-volatile memory device 200 according to a concept of the present invention. (See reference) Figure 10 The non-volatile memory device 200 includes a memory cell array 210, a row decoder block 220, a page buffer block 230, a pass / fail check block (PFC) 240, a data input and output block 250, a buffer block 260, and / or a control logic block 270.

[0113] and Figure 1 Compared to the non-volatile memory device 100, the control logic block 270 of the non-volatile memory device 200 may include a counter 271 and / or machine learning (ML) logic 272. The counter 271 may be used to count the recovery time tRES. The machine learning logic 272 may be used to determine the second voltage ΔV2.

[0114] Figure 11 It shows Figure 10 An example of the operation method of the non-volatile memory device 200. (See reference) Figure 10 and Figure 11 Operations S310 to S340 and Figure 4 Operations S110 to S140 are the same. Therefore, additional descriptions will be omitted to avoid redundancy. In operation S350, the non-volatile memory device 200 can adjust the voltage of the programming operation based on machine learning.

[0115] Figure 12 It shows that it can be used as Figure 10 Examples of machine learning logic include neural networks (NNs). For instance, neural networks (NNs) can include various derivative implementations such as artificial neural networks (ANNs), convolutional neural networks (CNNs), and recursive neural networks (RNNs).

[0116] refer to Figure 12 The neural network NN includes first input nodes IN1 to fourth input nodes IN4, first hidden nodes HN1 to tenth hidden nodes HN10, and output node ON. When constructing the neural network, the number of input nodes, the number of hidden nodes, and the number of output nodes can be determined in advance.

[0117] The first input nodes IN1 to the fourth input node IN4 form the input layer. The first hidden nodes HN1 to the fifth hidden nodes HN5 form the first hidden layer. The sixth hidden nodes HN6 to the tenth hidden nodes HN10 form the second hidden layer. The output node ON forms the output layer. When constructing a neural network, the number of hidden layers can be determined in advance.

[0118] Data used for learning or inference can be input to first input nodes IN1 through fourth input nodes IN4. The value of each input node is transmitted via branches (or synapses) to first hidden nodes HN1 through fifth hidden nodes HN5 in the first hidden layer. Each branch (or synapse) can be assigned a corresponding synaptic value or a corresponding weight. The value of each input node can be computed (e.g., multiplied) using the synaptic value or weight of the corresponding branch (or synapse) and can be transmitted to the first hidden layer.

[0119] The values ​​input to the first hidden nodes HN1 through the fifth hidden nodes HN5 are calculated using weights (or synaptic values) and can be transmitted to the sixth hidden nodes HN6 through the tenth hidden nodes HN10 in the second hidden layer. The inputs to the sixth hidden nodes HN6 through the tenth hidden nodes HN10 are calculated using weights (or synaptic values) and transmitted to the output node ON. The value of the output node ON can indicate the result of learning or inference.

[0120] The recovery time tRES, the number of programming loops executed, the level of the final applied programming voltage VPGM, and information about the fully programmed state in the programming state can be used as inputs to the neural network NN. Furthermore, information about the intervals during which the pause operation SUS is executed in the bit line setup interval I_BLS, programming interval I_PGM, and verification interval I_VFY of the programming loop can also be used as inputs to the neural network NN.

[0121] The address ADDR, i.e., the physical location of the selected memory cell, can be used as input to a neural network NN. In the example embodiment, external information provided from an external device, such as the number of programming and erasing cycles associated with the selected memory cell and the temperature, can further be used as input to the neural network NN. External information can be received from the external device along with pause or resume commands.

[0122] For reference Figure 7 and Figure 8 Where the non-volatile memory device 200 is configured to perform verification during a programming operation recovery, the verification result can be further used as input to the neural network NN. For example, comparing the verification result with programming progress data can be used as input to the neural network NN. An input node of the neural network NN can receive one input or two or more inputs.

[0123] The neural network NN can output the level of the second voltage ΔV2. (See reference...) Figure 6 As the incremental value of the programming voltage VPGM is gradually returned, the neural network NN can output the number of steps and the increment of each step.

[0124] Machine learning logic can utilize various other artificial neural networks to organize and process models, such as deconvolutional neural networks, recurrent neural networks (RNNs) including Long Short-Term Memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0125] Alternatively or additionally, such network structures may include other forms of machine learning models, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models can also be used to provide a variety of services and / or applications, such as image classification services, user authentication services based on bioinformatics or biostatistics, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which can be executed, run, or processed by electronic devices.

[0126] Figure 13 It is shown Figure 1 or Figure 10 A circuit diagram of an example memory block BLKa from memory blocks BLK1 to BLKz. (Refer to...) Figure 13 Multiple cell strings (CS) can be arranged in rows and columns on the substrate SUB. These multiple cell strings (CS) can be connected together with a common source line (CSL) formed on (or within) the substrate SUB. Figure 13The location of the substrate SUB is illustrated to help understand the structure of the memory block BLKa.

[0127] Each row's cell string CS can be connected to the ground select line GSL and the corresponding select lines of the first select line SSL1 to the fourth select line SSL4. Each column's cell string can be connected to one of the first select line BL1 to the fourth select line BL4. To reduce or prevent the diagram from becoming complicated, the cell string CS connected to the second select line SSL2 and the third select line SSL3 is depicted as blurred.

[0128] Each of the cell strings CS may include at least one ground selection transistor GST connected to the ground selection line GSL, a plurality of memory cells MC1 to MC8 connected to a plurality of word lines WL1 to WL8 respectively, and a string selection transistor SST connected to a string selection line SSL1, SSL2, SSL3 or SSL4 respectively.

[0129] In each of the cell strings CS, the ground selection transistor GST, memory cells MC1 to MC8, and string selection transistor SST can be connected in series along a direction perpendicular to the substrate SUB, and can be stacked sequentially along the same direction. In each of the cell strings CS, at least one of the memory cells MC1 to MC8 can be used as a virtual memory cell. The virtual memory cell may not be programmed (e.g., it may be programmed to be disabled) or may be programmed differently from the remaining memory cells in MC1 to MC8 other than the virtual memory cell.

[0130] In the example embodiment, memory cells located at the same height and associated with a string select line SSL1, SSL2, SSL3, or SSL4 can form a physical page. The memory cells of a physical page can be connected to a sub-word line. Sub-word lines of physical pages located at the same height can be collectively connected to a word line.

[0131] When the memory block BLKa is implemented in a three-dimensional structure, the characteristics of the memory cell MC can be implemented differently depending on the height of the memory cell MC. For example, the size of the memory cell MC can be changed according to its height. Therefore, the second voltage ΔV2 can be adjusted based on the physical location of the memory cell MC.

[0132] Figure 14 A storage device 300 according to an example embodiment of the present invention is shown. (Reference) Figure 14The storage device 300 may include a non-volatile memory device 310, a memory controller 320, and / or a buffer memory 330. The non-volatile memory device 310 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

[0133] For example, the non-volatile memory device 310 may include at least one of various non-volatile memory devices such as flash memory devices, phase-change memory devices, ferroelectric memory devices, magnetic memory devices, and resistive memory devices.

[0134] The memory controller 320 can receive various requests from an external host device to write data to or read data from the non-volatile memory device 310. The memory controller 320 can store (or buffer) user data exchanged with the external host device in the buffer memory 330, and can also store metadata for managing the storage device 300 in the buffer memory 330.

[0135] The memory controller 320 can access the non-volatile memory device 310 through the first channel CH1 and the second channel CH2. For example, the memory controller 320 can send commands and addresses to the non-volatile memory device 310 through the first channel CH1. The memory controller 320 can exchange data with the non-volatile memory device 310 through the first channel CH1.

[0136] The memory controller 320 can send a first control signal to the non-volatile memory device 310 via the second channel CH2. The memory controller 320 can also receive a second control signal from the non-volatile memory device 310 via the second channel CH2.

[0137] In an example embodiment, the memory controller 320 may be configured to control two or more non-volatile memory devices. The memory controller 320 may provide a first different channel and a second different channel for each of the two or more non-volatile memory devices.

[0138] For example, memory controller 320 may share a first channel for two or more non-volatile memory devices. Memory controller 320 may share a portion of a second channel CH2 for two or more non-volatile memory devices, and may provide the remaining portion separately.

[0139] The buffer memory 330 may include random access memory. For example, the buffer memory 330 may include at least one of dynamic random access memory, phase change random access memory, ferroelectric random access memory, magnetic random access memory, or resistive random access memory.

[0140] The memory controller 320 may include a bus 321, a host interface 322, an internal buffer 323, a processor 324, a buffer controller 326, a memory manager 327, and / or an error correction code (ECC) block 328.

[0141] Bus 321 provides a communication channel between components in memory controller 320. Host interface 322 can receive various requests from external host devices and can parse the received requests. Host interface 322 can store the parsed requests in internal buffer 323.

[0142] The host interface 322 can send various responses to external host devices. The host interface 322 can exchange signals with external host devices according to a given communication protocol. The internal buffer 323 may include random access memory. For example, the internal buffer 323 may include static random access memory or dynamic random access memory.

[0143] Processor 324 can drive the operating system or firmware used to drive memory controller 320. Processor 324 can read parsed requests stored in internal buffer 323 and can generate commands and addresses for controlling non-volatile memory device 310. Processor 324 can transmit the generated commands and addresses to memory manager 327.

[0144] Processor 324 can store various metadata used to manage storage device 300 into internal buffer 323. Processor 324 can access buffer memory 330 through buffer controller 326. Processor 324 can control buffer controller 326 and memory manager 327 so that user data stored in buffer memory 330 is sent to non-volatile memory device 310.

[0145] Processor 324 can control host interface 322 and buffer controller 326 to send data stored in buffer memory 330 to external host devices. Processor 324 can control buffer controller 326 and memory manager 327 to store data received from non-volatile memory device 310 into buffer memory 330. Processor 324 can control host interface 322 and buffer controller 326 to store data received from external host devices into buffer memory 330.

[0146] Under the control of the processor 324, the buffer controller 326 can write data to or read data from the buffer memory 330. The memory manager 327 can communicate with the non-volatile memory device 310 through the first channel CH1 and the second channel CH2 under the control of the processor 324.

[0147] Error correction code block 328 can perform error correction encoding on data to be sent to non-volatile memory device 310 using error correction code ECC. Error correction code block 328 can perform error correction decoding on data received from non-volatile memory device 310 using error correction code ECC.

[0148] Processor 324 may include machine learning logic 325. Machine learning logic 325 may be implemented according to reference... Figure 11 The neural network NN is described. Machine learning logic 325 can infer information about the increments and steps of the programming voltage VPGM of the recovered programming operation.

[0149] In this embodiment, the machine learning logic 325 can be implemented using a separate dedicated processor independent of the processor 324. The separate dedicated processor may include a neural processor or a neuromorphic processor.

[0150] In an example embodiment, storage device 300 may not include buffer memory 330 and buffer controller 326. When buffer memory 330 and buffer controller 326 are not included in storage device 300, the above functions of buffer memory 330 and buffer controller 326 can be performed by internal buffer 323.

[0151] Figure 15 It shows Figure 14 An example of how to operate the storage device 300. (See reference) Figure 14 and Figure 15 In operation S410, the memory controller 320 can send a first command CMD1 as a write command to the non-volatile memory device 310. In operation S420, the non-volatile memory device 310 can start programming operations in response to the first command CMD1 and can notify the memory controller 320 of its ready status.

[0152] In operation S430, the memory controller 320 may send a second command CMD2 as a pause command to the non-volatile memory device 310. In operation S440, the non-volatile memory device 310 may perform a pause operation and may notify the memory controller 320 of its ready status.

[0153] In operation S450, the memory controller 320 can send a third command CMD3 as a read or write command to the non-volatile memory device 310. Furthermore, in operation S460, the memory controller 320 can begin counting the recovery time tRES.

[0154] In operation S470, the non-volatile memory device 310 can complete a read or program operation and can notify the memory controller 320 of its ready status. In operation S480, the memory controller 320 can use machine learning logic 325 to infer the voltage(s) and steps(s) of the programming voltage VPGM of the recovered programming operation.

[0155] In operation S490, the memory controller 320 may send information about the inferred voltages and steps along with a fourth command CMD4 as a recovery command to the non-volatile memory device 310. In an example embodiment, when progress information for the programming operation being inferred needs to be paused, the memory controller 320 may read the progress information from the non-volatile memory device 310.

[0156] Furthermore, the non-volatile memory device 310 can send progress information to the memory controller 320 according to a schedule determined by an algorithm for pausing and resuming. For example, the non-volatile memory device 310 can send progress information to the memory controller 320 in response to a pause command.

[0157] Figure 16 This is a diagram illustrating an example non-volatile memory device. (Reference) Figure 16 The memory device 1400 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. For example, the bonding method may include a method of electrically connecting bonding metals formed on the uppermost metal layer of the upper chip and bonding metals formed on the uppermost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten.

[0158] Each of the peripheral circuit region PERI and cell region CELL of the memory device 1400 may include an external pad bonding region PA, a word line bonding region WLBA, and / or a bit line bonding region BLBA.

[0159] The Peripheral Circuit Region (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and / or second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In an example embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten with relatively high resistance, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper with relatively low resistance.

[0160] exist Figure 16 In the example embodiments shown, although first metal layers 1230a, 1230b, and 1230c and second metal layers 1240a, 1240b, and 1240c are shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 1240a, 1240b, and 1240c. At least a portion of the one or more metal layers formed on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum or the like, having a lower resistance than the copper used to form the second metal layers 1240a, 1240b, and 1240c.

[0161] An interlayer insulating layer 1215 may be placed on a first substrate 1210 and cover multiple circuit elements 1220a, 1220b, and 1220c, first metal layers 1230a, 1230b, and 1230c, and second metal layers 1240a, 1240b, and 1240c. The interlayer insulating layer 1215 may include an insulating material, such as silicon oxide or silicon nitride.

[0162] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b in the cell region CELL by bonding, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum, copper, tungsten, etc.

[0163] Furthermore, the upper bonding metals 1371b and 1372b in the cell region CELL can be referred to as the first metal pads, and the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be referred to as the second metal pads.

[0164] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 1310, an interlayer insulating layer 1315, and a common source line 1320. On the second substrate 1310, a plurality of word lines 1331 to 1338 (e.g., 1330) may be stacked in a direction perpendicular to the upper surface of the second substrate 1310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the plurality of word lines 1330, respectively, and the plurality of word lines 1330 may be positioned between the at least one string select line and the at least one ground select line.

[0165] The widths of the multiple word lines 1330 along the X direction can be different from each other. As the distance from the first substrate 1210 of the peripheral circuit region PERI to the corresponding one of the multiple word lines 1330 increases, the width of the corresponding one of the multiple word lines 1330 decreases. Similarly, as the distance from the second substrate 1310 of the cell region CELL to the corresponding one of the multiple word lines 1330 increases, the width of the corresponding one of the multiple word lines 1330 increases.

[0166] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 1310 and pass through multiple word lines 1330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c may be a bit line contact, and the second metal layer 1360c may be a bit line. In an example embodiment, the bit line 1360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 1310.

[0167] An interlayer insulating layer 1315 may be placed on a second substrate 1310 and cover a common source line 1320, multiple word lines 1330, multiple cell contact plugs 1340, first metal layers 1350a, 1350b, and 1350c, and second metal layers 1360a, 1360b, and 1360c. The interlayer insulating layer 1315 may include an insulating material, such as silicon oxide or silicon nitride.

[0168] exist Figure 16In the example embodiment shown, the area where the channel structure CH, bit line 1360c, etc., are placed can be defined as a bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 1360c can be electrically connected to circuit element 1220c that provides page buffer 1393 in peripheral circuit area PERI. For example, bit line 1360c can be connected to upper bonding metals 1371c and 1372c in cell area CELL, and upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c, wherein the lower bonding metals 1271c and 1272c are connected to circuit element 1220c of page buffer 1393.

[0169] In the word line bonding area (WLBA), a plurality of word lines 1330 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 1310 and may be connected to a plurality of cell contact plugs 1341 to 1347 (e.g., 1340). The plurality of word lines 1330 and the plurality of cell contact plugs 1340 may be connected to each other in pads provided by at least a portion of the plurality of word lines 1330 extending at different lengths in the second direction. A first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portions of the plurality of cell contact plugs 1340, wherein the plurality of cell contact plugs 1340 are connected to the plurality of word lines 1330. The plurality of cell contact plugs 1340 may be connected to the peripheral circuit region PERI via upper bonding metals 1371b and 1372b of the cell region CELL and lower bonding metals 1271b and 1272b of the peripheral circuit region PERI in the word line bonding area (WLBA).

[0170] Multiple unit contact plugs 1340 may be electrically connected to circuit element 1220b providing line decoder 1394 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 1220b providing line decoder 1394 may differ from the operating voltage of circuit element 1220c providing page buffer 1393. For example, the operating voltage of circuit element 1220c providing page buffer 1393 may be greater than the operating voltage of circuit element 1220b providing line decoder 1394.

[0171] A common source contact plug 1380 can be placed in the external pad bonding area PA. The common source contact plug 1380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a can be sequentially stacked on the upper portion of the common source contact plug 1380. For example, the area where the common source contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are placed can be defined as the external pad bonding area PA.

[0172] Input-output pads 1205 and 1305 can be placed within the external pad bonding area PA. (See reference) Figure 16 A lower insulating film 1201 covering the lower surface of the first substrate 1210 can be formed below the first substrate 1210, and a first input-output pad 1205 can be formed on the lower insulating film 1201. The first input-output pad 1205 can be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c placed in the peripheral circuit region PERI via a first input-output contact plug 1203, and can be separated from the first substrate 1210 via the lower insulating film 1201. Furthermore, a side insulating film can be placed between the first input-output contact plug 1203 and the first substrate 1210 to electrically isolate the first input-output contact plug 1203 and the first substrate 1210.

[0173] refer to Figure 16 An upper insulating film 1301 covering the upper surface of the second substrate 1310 can be formed on the second substrate 1310, and a second input-output pad 1305 can be placed on the upper insulating layer 1301. The second input-output pad 1305 can be connected to at least one of a plurality of circuit elements 1220a, 1220b and 1220c placed in the peripheral circuit region PERI via a second input-output contact plug 1303.

[0174] According to the example embodiment, the second substrate 1310 and the common source line 1320 may not be placed in the area where the second input-output contact plug 1303 is placed. Furthermore, the second input-output pad 1305 may not overlap with the word line 1330 in the third direction (Z-axis direction). Reference Figure 16 The second input-output contact plug 1303 can be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and can pass through the interlayer insulation layer 1315 of the cell region CELL to connect to the second input-output pad 1305 and the lower bonding metals 1271a and 1272a of the peripheral circuit region PERI.

[0175] According to an example embodiment, the first input-output pad 1205 and the second input-output pad 1305 may be selectively formed. For example, the memory device 1400 may include only the first input-output pad 1205 disposed on the first substrate 1210 or the second input-output pad 1305 disposed on the second substrate 1310. Alternatively, the memory device 1400 may include both the first input-output pad 1205 and the second input-output pad 1305.

[0176] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern in the uppermost metal layer can be provided as a virtual pattern, or the uppermost metal layer may not exist.

[0177] In the external pad bonding region PA, the memory device 1400 may include a lower metal pattern 1273a in the uppermost metal layer of the peripheral circuit region PERI, wherein the lower metal pattern 1273a corresponds to the upper metal pattern 1372a formed in the uppermost metal layer of the cell region CELL and has the same shape as the upper metal pattern 1372a of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern may be formed in the uppermost metal layer of the cell region CELL, wherein the upper metal pattern corresponds to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern of the peripheral circuit region PERI.

[0178] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL via Cu-Cu bonding.

[0179] Furthermore, in the bit line bonding region BLBA, the upper metal pattern 1392 can be formed in the uppermost metal layer of the cell region CELL, wherein the upper metal pattern 1392 corresponds to the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 1252 of the peripheral circuit region PERI. The contacts may not be formed on the upper metal pattern 1392 formed in the uppermost metal layer of the cell region CELL.

[0180] In the example embodiment, a reinforced metal pattern having the same shape as the metal pattern formed in the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI can be formed in the uppermost metal layer of the other cell region CELL and the peripheral circuit region PERI, and the contacts may not be formed on the reinforced metal pattern.

[0181] As described above, according to exemplary embodiments of the present invention, a non-volatile memory device, a storage device including the non-volatile memory device, and a method of operating the non-volatile memory device are provided, wherein the non-volatile memory device has improved flexibility by supporting pause and resume functions (or operations) and improved reliability by adjusting the increment of the programming voltage when resuming programming operations.

[0182] In the above example embodiments, components according to the inventive concept are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish components from each other and do not limit the inventive concept. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0183] In the above exemplary embodiments, components of exemplary embodiments based on the present invention are described using blocks. A block can be implemented as a processing circuit having various hardware devices, such as integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in the hardware device, software such as applications, or a combination of hardware devices and software. Furthermore, the block may include circuits implemented using semiconductor elements in an integrated circuit or circuits registered as intellectual property (IP).

[0184] According to the present invention, a non-volatile memory device can pause programming operations in response to a pause command and can perform any other operations. The non-volatile memory device can resume programming operations in response to a resume command. Specifically, the reliability of the non-volatile memory device can be improved by adjusting the parameters of the programming operation. Therefore, a non-volatile memory device with the flexibility to support emergency access and improved reliability, a storage device including the non-volatile memory device, and a method of operating the non-volatile memory device are provided.

[0185] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method of operating a non-volatile memory device, comprising: A pause command is received at the non-volatile memory device; In response to the pause command, the programming operation being performed is paused at the non-volatile memory device; A recovery command is received at the non-volatile memory device; In response to the recovery command, the suspended programming operation is resumed at the non-volatile memory device; as well as The time count from pausing the programming operation to resuming the paused programming operation. The programming operation includes a programming loop, each of which includes a bit line setting interval, a programming interval, and a verification interval. In each programming interval of the programming cycle, the programming voltage level to be applied to the selected memory cell of the non-volatile memory device is increased by a first voltage. The difference between the programming voltage level finally applied to the selected memory cell before the programming operation is paused and the programming voltage level initially applied to the selected memory cell after the paused programming operation is resumed corresponds to a second voltage different from the first voltage. The second voltage is adjusted based on the counted time.

2. The operating method according to claim 1, wherein, The second voltage is less than the first voltage.

3. The operating method according to claim 1, wherein, As the counting time increases, the second voltage decreases.

4. The operating method according to claim 1, wherein, The difference between the level of the programming voltage applied to the selected memory cell a second time after the paused programming operation is resumed and the level of the programming voltage applied for the first time corresponds to the first voltage.

5. The operating method according to claim 1, wherein, The difference between the level of the programming voltage applied a second time to the selected memory cell after the paused programming operation is resumed and the level of the programming voltage applied the first time corresponds to a third voltage, and The third voltage is greater than the second voltage and less than the first voltage.

6. The operating method according to claim 1 further includes: In response to the recovery command, the threshold voltage of the selected memory cell is verified at the non-volatile memory device. The second voltage is further adjusted based on the results of the verification.

7. The operating method according to claim 6, wherein, The verification is not included in the programming loop.

8. The operating method according to claim 1, wherein, The second voltage is determined based on machine learning.

9. The operating method according to claim 8, wherein, The second voltage is determined by the machine learning based on the count, the result of verifying the selected memory cell after resuming the paused programming operation, the number of programming / erase cycles associated with the selected memory cell, the temperature, the interval of the programming cycle when the programming operation is paused, the number of programming cycles executed up to the time the programming operation is paused, the number of states where programming is completed up to the time the programming operation is paused, the physical location of the selected memory cell, and the address of the selected memory cell.

10. A non-volatile memory device, comprising: The memory cell region includes memory cells and a first metal pad; as well as The outer area includes: Second metal pad; A line decoder, connected to the memory cell via word lines, is configured to apply a programming voltage to a word line selected from the word lines during the programming interval of each programming cycle of the programming operation, and to apply a verification voltage to the selected word line during the verification interval of each programming cycle. A page buffer, connected to the memory cell via bit lines, is configured to apply voltage to the bit lines during the bit line setting interval of each programming cycle of the programming operation; and The control logic is configured to control the line decoder and the page buffer in response to a programming command, causing the programming operation to be initiated. In each programming interval of the programming cycle, the line decoder increases the level of the programming voltage applied to the selected word line by a first voltage from the previous level of the programming voltage in the previous programming cycle. The control logic controls the line decoder and the page buffer to pause the programming operation in response to a pause command and resume the paused programming operation in response to a resume command. The control logic is further configured to count the time from pausing the programming operation to resuming the paused programming operation. The difference between the programming voltage level finally applied to the selected word line before pausing the programming operation and the programming voltage level initially applied to the selected word line after resuming the paused programming operation corresponds to a second voltage different from the first voltage. The control logic is further configured to adjust the second voltage based on a counted time, and The peripheral area is vertically connected to the memory cell area via the first metal pad and the second metal pad.

11. The non-volatile memory device according to claim 10, wherein, The control logic is also configured as follows: After resuming the paused programming operation, the line decoder and the page buffer are controlled to verify the selected memory cell connected to the selected word line; and The second voltage is further adjusted based on the results of the verification.

12. The non-volatile memory device according to claim 10, wherein, The control logic is also configured as follows: When the programming operation is paused, the operation specified by the other command is performed in response to another command.

13. The non-volatile memory device according to claim 10, wherein, The pause command includes a read command, and The control logic is further configured as follows: After pausing the programming operation, the line decoder and the page buffer are controlled to perform a read operation in response to the read command.

14. The non-volatile memory device according to claim 10, wherein, During the programming interval of each of the programming cycles, the line decoder further applies a second programming voltage to the selected word line, and In each programming interval of the programming loop, the line decoder increases the level of the second programming voltage by a third voltage.

15. The non-volatile memory device according to claim 14, wherein, The difference between the level of the second programming voltage that was finally applied to the selected word line before the programming operation was paused and the level of the second programming voltage that was first applied to the selected word line after the paused programming operation was resumed corresponds to a fourth voltage that is different from the third voltage.

16. A storage device, comprising: Non-volatile memory devices, including memory cells; as well as The controller is configured to send a write command associated with a memory cell selected from the memory cells to the non-volatile memory device, send a pause command to the non-volatile memory device to pause the write command before completing the programming operation, and send a resume command to the non-volatile memory device to resume the write command. In response to the write command, the non-volatile memory device is configured to repeatedly apply a programming voltage to the selected memory cell while increasing the programming voltage from a previous level by a first increment. The controller sends information about a second increment of the programming voltage to be applied to the selected memory cell, along with the recovery command, to the non-volatile memory device. The non-volatile memory device, in response to the recovery command, increases the programming voltage by the second increment, and The controller is further configured to count the time between the pause command and the resume command, and to determine the second increment based on the counted time.

17. The storage device according to claim 16, wherein, The controller is also configured to: The second increment is determined based on machine learning.

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