Low power and fast memory reset

Abstract

Various embodiments of this disclosure relate to low-power and fast memory reset. One memory reset method includes: pre-charging bit lines of a memory array; asserting a signal at a reset node to remove the pre-charge voltage; and selecting write drivers associated with bit lines, the bit lines being associated with columns of the memory array including memory cells to be reset; wherein the assertion signal at the reset node further causes a desired logic state to be applied to the input of the selected write drivers, causing those selected write drivers to change the logic state of the bit lines associated with those write drivers. The method continues to assert each word line associated with a row of memory containing the memory cells to be reset, to write the desired logic state to all memory cells to be reset in the column and row of memory during a single clock cycle, and then deasserting those word lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 221,090, filed July 13, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to the field of static random access memory (SRAM), and more particularly to techniques for performing fast resets of SRAM while reducing power consumption for those processes. Background Technology

[0004] Static random access memory (SRAM) is used in many electronic devices in the modern world. Some applications utilizing SRAM, such as time-of-flight (ToF) ranging and light detection and ranging (LiDAR) applications, involve frequent "resets" of the SRAM, i.e., writing the same logical value (such as a default logical 0, or an alternative logical 1, or a predefined pattern of logical 1 and logical 0, such as a checkerboard) to all memory cells of at least a portion of the SRAM.

[0005] Now for reference Figure 1 This diagram illustrates a block diagram of memory circuitry 10 used in HistoRam (a memory used in constructing histograms for ranging applications). Circuitry 10 includes an array 12 of memory cells C arranged in rows and columns. The size of array 12 is m×n, where m is the number of columns and n is the number of rows. Memory cells in each row are controlled by word lines from word lines 14[0],...,14[n-1]. Memory cells in each column are connected to bit line / complementary bit line pairs from pairs 16[0],...,16[m-1]. Row decoder circuitry 18b receives a row address pre-decoded from the address and decodes the bits of the row address to select and activate one word line from word lines 14[0],...,14[n-1]. Column decoder circuitry 18a receives a column address pre-decoded from the address and decodes the bits of the column address to select multiple bit lines 16[0],...,16[m-1]. In read mode, data stored in a memory cell is read onto data input / output line 20. The memory cell is located at the intersection of one word line 14[0],...,14[n-1] selected by the address and multiple bit lines 16[0],...,16[m-1]. In write mode, data on data input / output line 20 is written to a memory cell. The memory cell is located at the intersection of one word line 14[0],...,14[n-1] selected by the address and multiple bit lines 16[0],...,16[m-1].

[0006] The write operation will be discussed in more detail, as this invention focuses on the write operation. In particular, note that at the end of each operation, the precharge circuit 24 precharges the bit line pairs 16[0],...,16[m-1] to a voltage between the voltage representing logic 0 and the voltage representing logic 1. Therefore, at the start of the write operation, the selected bit line pairs 16[0],...,16[m-1] have already been precharged. Consequently, the precharge voltage applied to the selected bit line pairs 16[0],...,16[m-1] by the precharge circuit 24 is released, allowing the selected bit line pairs 16[0],...,16[m-1] to float. The selected word line 14[0],...,14[n-1] is then selected by asserting the associated word line 14[0],...,14[n-1] via the line decoder circuit 18b, and the write driver 22 forces the selected memory cell to reach the desired logic value. In order to complete the write operation, the precharge of the selected bit line pair 16[0],...,16[m-1] is restored, thereby preparing the associated memory cell for the next operation, whether it is a write operation or a read operation.

[0007] Typically, memory cells in array 12 are selected one word at a time for a write operation. Typically, to reset a portion or all of the memory cells in array 12, a write operation is performed for each selected word to write logic zeros into the memory cell of the word. Typically, one clock cycle is used for each write operation to be performed. Therefore, the number of clock cycles required to reset a given number of words is equal to the given number of words (e.g., if ten words are to be reset, then ten clock cycles are used to write logic zeros into the memory cell of each word). While write cycle times for modern SRAM memories are relatively short, for some applications such as ToF and LiDAR, it is desirable to reset large blocks of SRAM as quickly as possible, and even modern SRAM memories cannot perform this as quickly as desired due to the potentially large number of clock cycles involved.

[0008] Furthermore, it should be noted that each write operation performed (and one write operation per word to be reset) involves discharging the bit line pairs in the bit line pair, followed by pre-charging the bit line pairs, thereby consuming power for each memory cell of each word to be reset. Additionally, as in Figure 1 As can be observed, it is common in HistoRam (or conventional SRAM with existing D inputs) to have a separate reset data input pin “D”, which allows the selected reset value (logic 0 or logic 1) to be directly provided for writing the word to be reset, resulting in area consumption for the pin and associated routing.

[0009] Therefore, there is a need to further develop circuit devices and technologies for operating the aforementioned circuit devices to provide fast, low-power memory reset. Summary of the Invention

[0010] This document discloses a method for resetting a memory, comprising: a) precharging the bit lines by applying a precharge voltage to the bit lines of a memory array; b) asserting a signal at a reset node to thereby remove the precharge voltage from the bit lines; c) selecting write drivers associated with the bit lines, the bit lines being associated with columns of the memory array containing memory cells to be reset; wherein the assertion of the signal at the reset node also causes an assertion of the inputs of the selected write drivers, thereby causing those selected write drivers to change the logic state of the bit lines associated with those write drivers; d) asserting word lines associated with rows of the memory containing memory cells to be reset, thereby writing the desired logic state to all memory cells to be reset in the columns and rows of the memory during a first clock cycle, and then deasserting the word lines; and e) asserting word lines associated with memory cells to be reset in other rows of the memory without first reapplying the precharge voltage to the bit lines and complementary bit lines, thereby writing the desired logic state to all memory cells to be reset in the columns and other rows of the memory during a second clock cycle, and then deasserting the word lines.

[0011] The method may also include: f) repeating step e) until each row containing the memory cell to be reset has reset the memory cell.

[0012] The method may also include: g) releasing the assertion signal at the reset node; and h) reapplying the precharge voltage to the bit line.

[0013] All columns can contain memory cells to be reset, and at c), all write drivers associated with the bit lines can be selected.

[0014] Not all columns can contain memory cells to be reset, and at c), not all write drivers associated with the bit lines can be selected.

[0015] An assertion of the signal at the reset node can cause an assertion of the input of the selected write driver, thereby causing those selected write drivers to pull the bit lines associated with those write drivers low. The desired logic state for all memory cells to be reset, written to columns and other rows of memory, can be logic 0.

[0016] Assertions at the reset node signal can cause the desired logic signals to be applied to the inputs of the selected write drivers, thereby driving the bit lines associated with those drivers to the desired logic state. The desired logic state of all memory cells to be reset, written to columns and rows of memory, can represent a predefined pattern.

[0017] The predefined pattern can be a checkerboard pattern.

[0018] An assertion of the signal at the reset node can cause an assertion of the input of the selected write driver, thereby causing those selected write drivers to pull the bit lines associated with those write drivers high. The desired logic state for all memory cells to be reset, written to columns and rows of memory, can be logic 1. The desired logic state for all memory cells to be reset, written to columns and other rows of memory, can be logic 1.

[0019] An assertion on a word line associated with a row of memory containing a memory cell to be reset can cause the same logic state to be written to all memory cells to be reset in both columns and rows of memory during the first clock cycle, and then the assertion on the word line is released.

[0020] This document also discloses a method for resetting a memory, comprising: a) precharging a bit line by applying a precharge voltage to a bit line of a memory array; b) asserting a signal at a reset node to thereby remove the precharge voltage from the bit line; c) selecting a write driver associated with a bit line, the bit line being associated with a column of a memory array containing a memory cell to be reset; wherein the assertion of the signal at the reset node also causes a desired logic state to be applied to the input of the selected write driver, thereby causing those selected write drivers to change the logic state of the bit lines associated with those write drivers; and d) asserting each word line associated with a row of the memory containing the memory cell to be reset, thereby writing the desired logic state to all memory cells to be reset in the column and row of the memory during a single clock cycle, and then deasserting those word lines.

[0021] The method may further include: g) releasing the assertion signal at the reset node; and h) reapplying the precharge voltage to the bit line.

[0022] All columns can contain memory cells to be reset, and at c), all write drivers associated with the bit lines can be selected.

[0023] Fewer than all columns may contain memory cells to be reset, and at c), not all write drivers associated with the bit lines can be selected.

[0024] Assertions to the signals at the reset node can lead to assertions to the inputs of the selected write drivers, thereby causing those selected write drivers to pull the bit lines associated with those write drivers low. The desired logic state for all memory cells to be reset, written to columns and rows of memory, can be logic 0.

[0025] Assertions at the reset node signal can cause the application of desired logic signals to the inputs of the selected write drivers, thereby causing those selected write drivers to drive the bit lines associated with those drivers to the desired logic state. The desired logic state of all memory cells to be reset, written to columns and rows of memory, can represent a predefined pattern.

[0026] The predefined pattern can be a checkerboard pattern.

[0027] Assertions to the signals at the reset node can lead to assertions to the inputs of the selected write drivers, thereby causing those selected write drivers to drive the bit lines associated with those write drivers to logic high. The desired logic state for all memory cells to be reset, written to columns and rows of memory, can be logic 1.

[0028] This document also discloses a static random access memory (SRAM) device, comprising: a memory array formed of memory cells and organized into rows and columns, wherein each row has an associated word line and each column has an associated bit line and a complementary bit line; a row decoder configured to selectively assert the word line of a desired row; a column decoder configured to select a desired column; precharge circuitry associated with the bit line and the complementary bit line; and column drive circuitry configured to selectively drive the bit line and the complementary bit line of the desired column to opposite logic states. In response to an assertion of a reset signal: the precharge circuitry is configured to release the precharge voltage applied to the bit line and the complementary bit line; the row decoder is configured to assert the word line of each desired row within a given time period sufficient to allow a reset of the memory cell in the desired row, wherein the precharge circuitry maintains the precharge voltage between word line assertions; and the precharge circuitry is configured to restore the precharge voltage after the given time period for the last desired row has expired.

[0029] The line decoder can be configured to selectively assert word lines of the desired line simultaneously.

[0030] The line decoder can be configured to sequentially assert the word lines of the desired lines.

[0031] The line decoder can be configured to assert word lines of the desired line sequentially under the control of a counter, wherein the counter increments between assertions of different word lines.

[0032] Driving the bit lines and complementary bit lines to opposite logic states by the column driver circuit can drive the bit lines to logic 1 and the complementary bit lines to logic 0.

[0033] Driving the bit line and the complementary bit line to opposite logic states by the column driver circuit can drive the bit line to logic 0 and the complementary bit line to logic 1.

[0034] The column driver circuit may include: an inverter associated with each different bit line, the output of which is coupled to the bit line; and a multiplexing circuit. The multiplexing circuit may include: different first multiplexers associated with each different bit line; and different second multiplexers associated with each different complementary bit line; wherein each first multiplexer has: a first data input coupled to a reset signal, a second data input coupled to the column decoder, and a selection input coupled to the reset signal; wherein each second multiplexer has: a first data input coupled to the two's complement of the reset signal, a second data input coupled to the column decoder, and a selection input coupled to the reset signal; and wherein, in response to an assertion of the reset signal, each first multiplexer and each second multiplexer for each selected column passes its first data input as an output, thereby driving the bit line and complementary bit line of the desired column to opposite logic states.

[0035] The column driver circuit may include: an inverter associated with each different bit line, the output of which is coupled to the bit line; and a multiplexing circuit. The multiplexing circuit may include: different first multiplexers and first supplementary multiplexers associated with each different bit line; and different second multiplexers and second supplementary multiplexers associated with each different complementary bit line; wherein each first supplementary multiplexer has: a first data input coupled to a logic high voltage, a second data input coupled to a logic low voltage, a selection input coupled to a logic state selection signal, and an output; wherein each first multiplexer has: a first data input coupled to the output of the first supplementary multiplexer, a second data input coupled to the column decoder, a selection input coupled to a reset signal, and an output coupled to an inverter for its respective bit line. Each of the second additional multiplexers has: a first data input coupled to a logic high voltage, a second data input coupled to a logic low voltage, a selection input coupled to a logic state selection signal, and an output; each of the second multiplexers has a first data input coupled to the output of the first additional multiplexer, a second data input coupled to the column decoder, a selection input coupled to a reset signal, and an output coupled to its corresponding complementary bit line; and wherein, in response to an assertion of the reset signal, each of the first multiplexers and each of the second multiplexers for each selected column passes its first data input as an output, thereby driving the bit line and complementary bit line of the desired column to the opposite logic state. Attached Figure Description

[0036] Figure 1 This is a block diagram of a conventional SRAM device.

[0037] Figure 2 This is a schematic block diagram of the SRAM device disclosed herein, which is capable of quickly and with low power resetting the memory array to the default value of logic 0 one row at a time.

[0038] Figure 3A This occurs when a single row of memory cells is reset to its default value of logic 0. Figure 2 Timing diagram of SRAM device.

[0039] Figure 3B This occurs when multiple rows of memory cells are sequentially reset to their default value of logic 0. Figure 2 Timing diagram of SRAM device.

[0040] Figure 4 This is a schematic block diagram of the SRAM device disclosed herein, which can quickly and with low power reset the memory array to the default value of logic 0 at a time, multiple rows at a time.

[0041] Figure 5 When multiple rows of memory cells are simultaneously reset to their default value of logic 0. Figure 4 Timing diagram of SRAM device.

[0042] Figure 6 This is a schematic block diagram of the SRAM device disclosed herein, which can quickly and with low power reset the memory array to the default value of logic 0 one row at a time using a counter that controls the row decoder.

[0043] Figure 7 This occurs when multiple rows of memory cells are sequentially reset to their default value of logic 0. Figure 6 Timing diagram of SRAM device.

[0044] Figure 8 This is a schematic block diagram of the SRAM device disclosed herein, which can quickly and with low power reset the memory array to the default value 1 or the default value 0, row by row.

[0045] Figure 9A This is when a single-row memory cell is reset to its default value of logic 0. Figure 8 Timing diagram of SRAM device.

[0046] Figure 9B When a single-row memory cell is reset to its default value of logic 1. Figure 8 Timing diagram of SRAM device.

[0047] Figure 10A This occurs when multiple rows of memory cells are sequentially reset to their default value of logic 0. Figure 8 Timing diagram of SRAM device.

[0048] Figure 10B This occurs when multiple rows of memory cells are sequentially reset to their default logic value of 1. Figure 8 Timing diagram of SRAM device.

[0049] Figure 11 This is a schematic block diagram of the SRAM device disclosed herein, which can quickly and with low power reset the memory array to the default value of logic 0 or logic 1 at a time, multiple rows at a time.

[0050] Figure 12A When multiple rows of memory cells are simultaneously reset to their default value of logic 0. Figure 11 Timing diagram of SRAM device.

[0051] Figure 12B When multiple rows of memory cells are simultaneously reset to their default value of logic 1. Figure 11 Timing diagram of SRAM device.

[0052] Figure 13This is a schematic block diagram of the SRAM device disclosed herein, which can quickly and with low power reset the memory array to the default value of logic 0 or logic 1 one row at a time using a counter that controls the row decoder.

[0053] Figure 14A This occurs when multiple rows of memory cells are sequentially reset to their default value of logic 0. Figure 13 Timing diagram of SRAM device.

[0054] Figure 14B This occurs when multiple rows of memory cells are sequentially reset to their default logic value of 1. Figure 13 Timing diagram of SRAM device. Detailed Implementation

[0055] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is consistent with the widest scope of the principles and features disclosed or suggested herein.

[0056] Now, let's refer to... Figure 2 The description includes an SRAM device 30 on which fast, low-power memory resets can be performed.

[0057] SRAM device 30 includes memory array 12. Memory array 12 is m×n in size, where m is the number of columns and n is the number of rows. At each intersection of a column and a row, there is a memory cell.

[0058] For example, memory cell C[0,0] located at the intersection of the 0th pair of bit lines and the 0th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP1 and NMOS MN1, and the second inverter is a CMOS inverter formed by PMOS MP2 and NMOS MN2), wherein the transmission gate NMOS MN3 is coupled between the node BLTI[0,0] at the drain of MP1 and MN1 and the bit line BL[0], and the transmission gate NMOS MN4 is coupled between the node BLFI[0,0] at the drain of MP2 and MN2 and the complementary bit line BLN[0]. Memory cell C[0,0] is powered between the power supply voltage VDD and ground GND.

[0059] Similarly, the memory cell C[m-1, 0] located at the intersection of the (m-1)th pair of bit lines and the 0th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP3 and NMOS MN5, and the second inverter is a CMOS inverter formed by PMOS MP4 and NMOS MN6), wherein the transmission gate NMOS MN7 is coupled between the node BLTI[m-1, 0] at the drain of MP3 and MN5 and the bit line BL[m-1], and the transmission gate NMOS MN8 is coupled between the node BLFI[m-1, 0] at the drain of MP2 and MN2 and the complementary bit line BLN[m-1]. The memory cell C[m-1, 0] is powered between the power supply voltage VDD and ground GND.

[0060] The memory cell C[0, n-1] located at the intersection of the 0th pair of bit lines and the (n-1)th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP5 and NMOS MN9, and the second inverter is a CMOS inverter formed by PMOS MP6 and NMOS MN10). The transmission gate NMOS MN11 is coupled between the node BLTI[0, n-1] at the drain of MP5 and MN9 and the bit line BL[0], and the transmission gate NMOS MN12 is coupled between the node BLFI[0, n-1] at the drain of MP6 and MN10 and the complementary bit line BLN[0]. The memory cell C[0, n-1] is powered between the power supply voltage VDD and ground GND.

[0061] The memory cell C[m-1, n-1] located at the intersection of the (m-1)th pair of bit lines and the (n-1)th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP7 and NMOS MN13, and the second inverter is a CMOS inverter formed by PMOS MP8 and NMOS MN14). The transmission gate NMOS MN15 is coupled between node BLTI[m-1, n-1] at the drain of MP7 and MN13 and the bit line BL[m-1], and the transmission gate NMOS MN16 is coupled between node BLFI[m-1, n-1] at the drain of MP8 and MN14 and the complementary bit line BLN[m-1]. The memory cell C[m-1, n-1] is powered between the power supply voltage VDD and ground GND.

[0062] The memory cells in each row are controlled by word lines from word lines WL[0],...,WL[n-1]. The selection of one or more rows is achieved by the row decoder 18b asserting one or more associated word lines from word lines WL[0],...,WL[n-1]. The selection of one or more columns is performed by the column decoder 18a, which performs the selection.

[0063] The precharge circuit device 24 is coupled to each bit line and complementary bit line pair BL[0],BLN[0],...,BL[m-1],BLN[m-1], and is controlled by the precharge control signal PCH.

[0064] The write driver circuit 22 is coupled to the multiplexing circuit 21 and associated with the precharge circuit device 24. For each bit line BL[0],...,BL[m-1], the write driver circuit device 22 includes an inverter having an input coupled to the multiplexing circuit device 21 and an output coupled to the bit line BL[0],...,BL[m-1].

[0065] For each bit line BL[0],...,BL[m-1] and complementary bit line BLN[0],...,BLN[m-1], the multiplexing circuit device 21 includes a multiplexer MUX having: a first data input coupled to column decoder 18a, a second data input coupled to a reset signal MRST applied to a pin or pad, a selection input coupled to MRST (which determines which data input is the output), and an output coupled to the bit line or complementary bit line. Note that MRST is provided as an input to column decoder 18b to allow selection of desired columns (e.g., column decoder 18b may have internal circuitry that selects certain columns based on an asserted MRST), and MRST is coupled to precharge circuit device 24 such that an assertion of MRST can deactivate precharge circuit device 24.

[0066] A standard write operation is described. Since this is a standard write operation, it is assumed that MRST is at logic low, causing the multiplexing circuitry 23 to be transparent and connecting the column decoder 18a to the write driver circuitry 22.

[0067] Remember that at this point, bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are precharged by precharge circuit device 24, just as they were at the end of the previous operation. In this example, assume that memory cell C[0,0] is set to hold logic 0. Here, the pre-decoded row address is received by row decoder 18b, and the pre-decoded column address is received by column decoder 18a. Column decoder 18a selects column 0, meaning that BL[0] and BLN[0] are selected, while the other bit lines and complementary bit lines are deselected. The precharge is released, and column decoder 18a outputs a data bit of 1 to write driver circuit device 22, causing the inverter output signal D_int for bit line BL[0] to drop to logic 0, and the multiplexer output signal D_int_B for complementary bit line BLN[0] to rise to logic 1. Row decoder 18b asserts word line WL[0] to toggle the state of memory cell C[0,0], such that BLTI[0,0] is at logic 0 and BLFI[0,0] is at logic 1. Then, row decoder 18b deasserts the assertion of assertion word line WL[0] by deasserting the MUX signal MUX[0], and column decoder 20d deasserts the write driver by deasserting the MUX signal MUX[0], and the precharge control signal PCH is deasserted, thereby restoring the precharge of reset line BL[0] and complementary bit line BLN[0]. This completes the reset of the desired cell or desired row (if all columns are selected).

[0068] While this is functional and allows the desired rows and columns of the desired rows to be reset, the power and time consumed by the recovery of the precharge after each row reset is inefficient. Therefore, to perform a fast reset of multiple cells, the reset pin or pad MRST can have an assertion signal applied to it. MRST is directly electrically connected to the precharge circuit device 24, such that the assertion of MRST asserts the precharge control signal (thus releasing the precharge), and as explained above, MRST is directly electrically connected to the select input and data input of the multiplexer of the multiplexing circuit device 23 so that D_int is forced to logic 0 and D_int_B is forced to logic 1 when MRST is asserted. Therefore, by asserting different word lines WL[0],...,WL[n-1] while maintaining MRST as asserted, the reset of the selected columns of those rows can be achieved without the power consumption and time consumed by the recovery of the precharge between rows. This will be described below.

[0069] A. Quickly reset a single row to logic 0.

[0070] Now refer to another source Figure 3AThe timing diagram describes a fast reset enabled by SRAM device 30. Here it is assumed that a row of memory cells in memory array 12, namely row 0, is to be reset.

[0071] To facilitate this, an assertion MRST is made at time t0, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 0 and D_int_B is forced to logic 1. At this time, the address indicating row 0 is decoded by row decoder 18b. In addition, column decoder 18a selects all columns, meaning that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0072] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock CLK, the line decoder 18b asserts the word line WL[0], allowing the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic zero at time t2. As a result, nodes BLTI[0,0],...,BLTI[m-1,0] fall to logic low, and nodes BLFI[0,0],...,BLFI[m-1,0] rise to logic high. At time t3, note that due to the high rise of nodes BLFI[0,0],...,BLFI[m-1], the complementary bit line BLN[0],...,BLN[m-1] remains at logic high. Now the memory cells C[0,0],...,C[0,m-1] are reset, and at time t4, the word line WL[0] is released (e.g., allowing it to fall to logic low). Since the expected reset operation (reset of row 0) has been performed, at time t5, MRST and PCH are released (e.g., allowing a fall to a logic row), and bit lines BL[0],...,[m-1] rise back to logic high accordingly.

[0073] Note that the states of memory cells C[0,0],...,C[m-1,0] are all toggled at once, and each word does not require a separate write cycle. Therefore, in the example shown with n rows and m columns, for simplicity, assuming each word is a bit, it takes only one write cycle (i.e., one clock cycle) to write logic 0 to all memory cells in row 0 (e.g., reset cell), instead of taking m write cycles (i.e., m clock cycles) to write logic 0 to all memory cells in row 0.

[0074] It should be understood that although in this particular example all columns of the selected row are reset, not all columns can be reset; the column decoder 18a resets the column regardless of which column it selects through the above operation. Therefore, the above operation can be used to reset the selected column of the selected row.

[0075] B. Sequentially reset multiple rows to logic 0.

[0076] As another example, suppose we want to reset two rows of memory cells in memory array 12, here row 0 and row n-1. For how this will happen, see also... Figure 3B At time t0, MRST is asserted, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 0 and D_int_B is forced to logic 1. At this time, the address indicating row 0 is decoded by row decoder 18b. In addition, column decoder 18a selects all columns, indicating that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0077] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock, the row decoder 18b assertion word line WL[0] allows the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic zero at time t2. This means that nodes BLTI[0,0],...,BLTI[m-1,0] fall to logic low, and nodes BLFI[0,0],...,BLFI[m-1,0] rise to logic high. Note that the states of memory cells C[0,0],...,C[m-1,0] are all toggled at once. At time t3, due to the high rise of nodes BLFI[0,0],...,BLFI[m-1,0], the complementary bit line BLN[0],...,BLN[m-1] remains at logic high.

[0078] At time t4, line decoder 18b deasserts word line WL[0]. This completes the reset of memory cells C[0,0],...,C[m-1,0], and then memory cells C[0,n-1],...,C[m-1,n-1] can be reset. Note that at the end of the reset of memory cells C[0,0],...,C[m-1,0], MRST is not released (e.g., remains asserted), and PCH is not released (e.g., remains asserted), while precharge is not performed on bit lines BL BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1].

[0079] For the reset of memory cell C[0,n-1],...,C[m-1,n-1], since the states of bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] have already been reset as needed, a new address is received to reset memory cell C[0,n-1],...,C[m-1,n-1], and this address in row n-1 is decoded by row decoder 18b. Then, at time t5, the clock CLK pulses, and after the falling edge of the clock, row decoder 18b asserts word line WL[n-1].

[0080] The state of memory cells C[0,n-1],...,C[m-1,n-1] is toggled to logic zero at time t6, meaning that nodes BLTI[0,n-1],...,BLTI[m-1,n-1] fall to logic low and nodes BLFI[0,n-1],...,BLFI[m-1,n-1] rise to logic high. Afterward, the reset of memory cells C[0,n-1],...,C[m-1,n-1] is completed, and word line WL[n-1] is released at time t7.

[0081] Although the reset of the two rows is described sequentially in this particular example, it should be understood that the above operation can be repeated to reset many rows as desired, and these rows do not have to be sequential (e.g., row 0 can be reset, then row 2 can be reset, then row 4 can be reset, etc.). It should also be understood that although all columns of the selected row are reset in this particular example, not all columns can be reset, regardless of which column selected by column decoder 18a is reset by the above operation. Column decoder 18a can achieve this through internal circuitry that selects the desired column in response to an assertion of the MRST signal.

[0082] Since the desired reset operation (reset of rows 0 and n-1) has been performed, at time t8, MRST and PCH are released (e.g., allowing a fall to logic low), and bit lines BL[0],...,BL[m-1] rise back high. Note that the states of memory cells C[0,0],...,C[m-1,0] are all toggled at once, and each word does not require a separate write cycle. Therefore, for simplicity, assuming each word is one bit, it takes only one write cycle (i.e., one clock cycle) to write logic zero to all memory cells within row 0 (e.g., reset said cells), instead of taking m write cycles (i.e., m clock cycles). Similarly, the states of memory cells C[0,n-1],...,C[m-1,n-1] are all toggled at once, so only one write cycle is needed to reset them. Therefore, in general, only two clock cycles are used to reset rows 0 and n-1, instead of m clock cycles per row.

[0083] It should be understood that, in addition to time savings, the power consumed by multiple precharges will be saved due to the fact that bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are not precharged until the reset is complete. Therefore, in addition to saving time, this design also saves power. In fact, since precharging is eliminated between row resets and word resets, power consumption is reduced by a factor of 1 / (m*n), which has the additional benefit of helping to ensure that the current drawn during memory cell state changes is insufficient to cause device failure.

[0084] C. Simultaneously reset multiple rows to logic 0.

[0085] In the example above where multiple rows are expected to be reset, rows are reset sequentially, one row at a time, and when the reset is complete, the next row is reset, with the precharge initially released and remaining released until all desired rows are reset. Multiple rows can be reset simultaneously, rather than sequentially one after another. In fact, any number of rows can be reset simultaneously (e.g., two rows, four rows, eight rows, etc.). Note that the strength of write driver 22 can be increased to enable parallelism in resetting multiple rows simultaneously.

[0086] To facilitate resetting multiple rows, Figure 4 The embodiment of the SRAM device 30' shown is similar to Figure 2 The SRAM device 30 is identical, but has an MRST coupled to the row decoder 18b to instruct the row decoder 18b to activate multiple word lines simultaneously. The row decoder 18b may have internal circuitry that asserts multiple word lines simultaneously in response to, for example, an assertion MRST.

[0087] For further reference Figure 5 For this example, assume that rows 0 and n-1 are expected to be reset simultaneously. Now, the operation of resetting multiple rows simultaneously is described. MRST is asserted at time t0, having the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and having the effect of setting the multiplexer so that D_int is forced to logic 0 and D_int_B is forced to logic 1.

[0088] Then, at time t1, the clock signal CLK is pulsed, and the line decoder 18b, as shown in the figure, simultaneously asserts word lines WL[0] and WL[n-1] after the falling edge of CLK, thereby allowing the states of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1] to be flipped to logic zero at time t2. This means that nodes BLTI[0,0],...,BLTI[m-1,0] and BLTI[0,n-1],...,BLTI[m-1,n-1] fall to logic low, and nodes BLFI[0,0],...,BLFI[m-1,0] and BLFI[0,n-1],...,BLFI[m-1,n-1] rise to logic high. Note that the states of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1] are all flipped at once. At time t3, due to the high rise of node BLFI[0,0],...,BLFI[m-1,0], the complementary bit line BLN[0],...,BLN[m-1] remains at logic high.

[0089] At time t4, row decoder 18b deasserts word lines WL[0] and WL[n-1]. This completes the reset of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1]. It is understood here that all columns of rows 0 and n-1 have been reset simultaneously, meaning that increasing the strength of write driver 22 to help ensure sufficient capability to simultaneously reset memory cells to their desired default values ​​may be helpful.

[0090] After this, the memory cells C[0,n-1],...,C[m-1,n-1] are reset, and MRST (and therefore PCH) is released at time t5. This restores the precharge, charging bit lines BL[0],...,BL[m-1] back high.

[0091] Note that instead of performing one write cycle (i.e., clock cycle) per word in each row, only one write cycle is performed in total to simultaneously reset all columns of the selected row 0 and n-1. This significantly reduces the number of clock cycles required to reset row 0 and n-1. Furthermore, since pre-charging is not performed until the end of a single write cycle, this greatly reduces power consumption. In fact, power consumption is reduced by a factor of 1 / n because pre-charging between rows is eliminated, which has the additional benefit of helping to ensure that the current drawn during state changes of memory cells is insufficient to cause device failure.

[0092] Although the simultaneous reset of two rows is described in this particular example, it should be understood that the above can be used to simultaneously reset as many rows as possible, and those rows need not be sequential (e.g., rows 0, 2, 4, and 6 can be reset, etc.). Further understanding, the above can be used to sequentially reset multiple groups of rows simultaneously (e.g., rows 0, 2, 4, and 6 can be reset simultaneously, then rows 1, 3, 5, and 7 can then be reset simultaneously, etc.). It should also be understood that although all columns of the selected row in this particular example are reset, fewer than all columns can be reset, regardless of which column selected by column decoder 18a is reset by the above operation. Column decoder 18a can achieve this through internal circuitry that selects the desired column in response to an assertion of the MRST signal.

[0093] D. Use a counter to control the line decoder

[0094] In the example in Part B above, multiple rows are reset sequentially, with a new address received after each individual row is reset, indicating which row will be reset next. Conversely, some rows may be expected to be reset without needing to receive a new address for each row to be reset.

[0095] For ease of explanation, Figure 6 The SRAM device 30" includes a counter 19 timed by clock CLK and reset by MRST. Counter 19 is selectively coupled to line decoder 18b via transmission gate 42, which is activated when MRST is asserted to pass the output from counter 19 to line decoder 18b. Additionally, when MRST is asserted, transmission gate 41 disconnects the address input from line decoder 18b, causing line decoder 18b to operate based on the output from counter 19.

[0096] Therefore, in operation, the output of counter 19 determines which word lines WL[0],...,WL[n-1] are asserted by line decoder 18b. Counter 19 can count in any increment (e.g., count 1, count 2, count 4, etc.) from an initial value (e.g., 0) to a final value (e.g., 15).

[0097] Apart from counter 19 and transmission gates 41 and 42, SRAM device 30" is referenced above. Figure 2 The SRAM device 30 described is the same.

[0098] Now refer to another source Figure 7 Describe the operation using counter 19.

[0099] Assume that it is desired to reset all rows of memory cells in memory array 12, here rows 0 to n-1. To make this happen, MRST is asserted at time t0, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 0 and D_int_B is forced to logic 1. It is worth noting here that the assertion of MRST resets counter 19, opens transmission gate 42 (making it act as a short circuit), and closes transmission gate 19 (making it act as an open circuit). Furthermore, at this time, column decoder 18a selects all columns, indicating that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0100] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock, counter 19 begins counting, here at 0, and thus outputs 0 to the row decoder first. Also after the falling edge of the clock CLK, row decoder 18b asserts the word line corresponding to the first output of counter 19, which is here word line WL[0]. This allows the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic zero at time t2, meaning that node BLTI[0,0],...,BLTI[m-1,0] falls to logic low and node BLFI[0,0],...,BLFI[m-1,0] rises to logic high. Note that the state of memory cells C[0,0],...,C[m-1,0] is toggled all at once. At time t3, due to the high rise of node BLFI[0,0],...,BLFI[m-1,0], the complementary bit line BLN[0],...,BLN[m-1] remains at logic high. At time t4, line decoder 18b releases the assertion word line WL[0]. This completes the reset of memory cells C[0,0],...,C[m-1,0]. Note that, as mentioned above, at the end of the reset of memory cells C[0,0],...,C[m-1,0], MRST is not released (e.g., the assertion is held), and PCH is not released (e.g., the assertion is held), while precharging on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] is not performed.

[0101] At time t5, another clock pulse CLK is received, and counter 19 increments. In this example, assume that rows 2 to n-2 have already been reset at time t5, each row receives a clock pulse CLK to be reset, and that counter 19 increments after each row. At time t5, the clock pulse CLK increments counter 19 to n-1, which is then output to the row decoder 18b.

[0102] For the reset of memory cell C[0,n-1],...,C[m-1,n-1], since the states of bit line BL[0],...,BL[m-1] and complementary bit line BLN[0],...,BLN[m-1] have been reset as needed, in order to reset memory cell C[0,n-1],...,C[m-1,n-1], after time t5, the line decoder 18b assertion word line WL[n-1].

[0103] The state of memory cells C[0,n-1],...,C[m-1,n-1] is toggled to logic zero at time t6, meaning that nodes BLTI[0,n-1],...,BLTI[m-1,n-1] fall to logic low and nodes BLFI[0,n-1],...,BLFI[m-1,n-1] rise to logic high. Afterward, the reset of memory cells C[0,n-1],...,C[m-1,n-1] is completed, and word line WL[n-1] is released at time t7. At time t8, MRST is released, effectively releasing PCH, and thus charging bit lines BL[0],...,BL[m-1] back high.

[0104] Note that the states of all memory cells C[0,n-1],...,C[m-1,n-1] in each row are toggled again, and each word does not require a separate write cycle. Therefore, for simplicity, assuming each word is one bit, it takes only one write cycle (i.e., one clock cycle) to write logic zeros to all memory cells (e.g., reset cells) in each individual row, instead of taking m write cycles (i.e., m clock cycles). Therefore, using this technique, each row requires one clock cycle for reset to perform the aforementioned reset.

[0105] Although in this particular example, counter 19 is used to generate the address used by row decoder 18b to sequentially describe the reset of all rows, it should be understood that the operation of counter 19 can be modified to reset as many rows as possible, and those rows do not have to be sequential (e.g., row 0 can be reset, then row 2 can be reset, then row 4 can be reset, etc.). It should also be understood that although in this particular example all columns of the selected row are reset, not all columns can be reset, regardless of which column selected by column decoder 18a is reset by the above operation. Column decoder 18a can achieve this through internal circuitry that selects the desired row in response to an assertion of the MRST signal.

[0106] E. Sequential multi-row fast reset with selectable reset values

[0107] In the above example, the memory cells of the selected row and column that are being reset are reset to logic 0. It should be understood that, alternatively, those memory cells can be reset to logic 1. For example, the data input of a multiplexer coupled to MRST can alternatively be coupled to its complement, MRSTN.

[0108] Furthermore, it can be expected that the memory cells for the selected rows and columns can be reset to selectable values. Figure 8 An embodiment with this capability is shown.

[0109] Aside from the differences in the multiplexing circuit device 23', the SRAM device 30"' and Figure 2 The SRAM device 30 is identical. Here, for each bit line BL[0],...,BL[m-1], the multiplexing circuit device 23' includes: a first multiplexer 45a having a first data input coupled to VDD, a second data input coupled to ground, a select input coupled to the reset signal RST, and an output; and a second multiplexer 46a having a first data input coupled to the output of the first multiplexer 45a, a second data input coupled to receiving the output from the column decoder 18a, a select input coupled to MRST, and an output coupled to the driver circuit device 22. Similarly, for each complementary bit line BLN[0],...,BLN[m-1], the multiplexing circuit 23' includes: a first multiplexer 45b having a first data input coupled to VDD, a second data input coupled to ground, a select input coupled to the reset signal RST, and an output; and a second multiplexer 46b having a first data input coupled to the output of the first multiplexer 45b, a second data input coupled to receiving the output from the column decoder 18a, a select input coupled to MRST, and an output coupled to the driver circuit device 22.

[0110] Here, MRST is referenced. Figure 2The SRAM device 30 operates as described, wherein when the multiplexer 46a receives the asserted MRST, the RST is used to select the values ​​of D_int and D_int_B. Figure 9A As shown in -9B, SRAM device 30" operates in the same manner as SRAM device 30, except that, as stated, the value of RST is selected from the values ​​of D_int and D_int_B when MRST is asserted. Therefore, as Figure 9A As shown, when RST is logic high and MRST is asserted, D_int is forced to logic 0 and D_int_B is forced to logic 1, and the operation is the same as the above reference. Figure 3A The operations described are the same.

[0111] like Figure 9B As shown, when RST is logic low and MRST is asserted, D_int is forced to logic 1 and D_int_B is forced to logic 0. In more detail, MRST is asserted at time t0, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 1 and D_int_B is forced to logic 0. At this time, the address indicating row 0 is decoded by row decoder 18b. In addition, column decoder 18a selects all columns, which means that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0112] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock, the line decoder 18b asserts the word line WL[0], allowing the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic 1 at time t2, where the result is that nodes BLTI[0,0],...,BLTI[m-1,0] rise to logic high and nodes BLFI[0,0],...,BLFI[m-1,0] fall to logic low. At time t3, note that due to the decrease in nodes BLFI[0,0],...,BLFI[m-1], the bit line BL[0],...,BL[m-1] remains at logic high. Now the reset of memory cells C[0,0],...,C[0,m-1] is complete, and the word line WL[0] is released at time t4 (e.g., allowing it to fall to logic low). Since the expected reset operation (reset of row 1) has been performed, at time t5, MRST and PCH are released (e.g., allowing a fall to a logic row), and the complementary bit lines BLN[0],...,BLN[m-1] rise back to logic high.

[0113] It should be understood that although in this particular example all columns of the selected row are reset, not all columns can be reset; regardless of which column the column decoder 18a selects, it is reset by the operation described above. The column decoder 18a can achieve this through internal circuitry that selects the desired row in response to an assertion of the MRST signal.

[0114] exist Figure 10A The example shown is an example of using SRAM device 13”' to sequentially reset multiple rows. For example, it can be seen that... Figure 10A As observed, SRAM device 30" operates identically to SRAM device 30, except that, as stated, the value of RST is selected from the values ​​of D_int and D_int_B when MRST is asserted. Therefore, as Figure 10A As shown, when RST is logic high and MRST is asserted, D_int is forced to logic 0 and D_int_B is forced to logic 1, and the operation is the same as the above reference. Figure 3B The operations described are the same.

[0115] like Figure 10B As shown, when RST is logic low and MRST is asserted, D_int is forced to logic 1 and D_int_B is forced to logic 0. In more detail, MRST is asserted at time t0, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 1 and D_int_B is forced to logic 0. At this time, the address indicating row 0 is decoded by row decoder 18b. In addition, column decoder 18a selects all columns, indicating that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0116] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock, the line decoder 18b assertion word line WL[0] allows the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic 1 at time t2. This means that node BLTI[0,0],...,BLTI[m-1,0] rises to logic high, and node BLFI[0,0],...,BLFI[m-1,0] falls to logic low. The state of memory cells C[0,0],...,C[m-1,0] is toggled once. At time t3, due to the decrease in node BLFI[0,0],...,BLFI[m-1,0], the bit line BL[0],...,BL[m-1] remains at logic high.

[0117] At time t4, line decoder 18b deasserts word line WL[0]. This completes the reset of memory cells C[0,0],...,C[m-1,0], and then memory cells C[0,n-1],...,C[m-1,n-1] can be reset. Note that at the end of the reset of memory cells C[0,0],...,C[m-1,0], MRST is not released (e.g., remains asserted), and PCH is not released (e.g., remains asserted), while precharging on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] is not performed.

[0118] For the reset of memory cell C[0,n-1],...,C[m-1,n-1], since the states of bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] have been reset as needed, in order to reset memory cell C[0,n-1],...,C[m-1,n-1], a new address is received, and the address including row n-1 is decoded by row decoder 18b. Then, at time t5, the clock CLK pulses, and after the falling edge of the clock, row decoder 18b asserts word line WL[n-1].

[0119] The state of memory cells C[0,n-1],...,C[m-1,n-1] is toggled to logic 1 at time t6, meaning that nodes BLTI[0,n-1],...,BLTI[m-1,n-1] rise to logic high and nodes BLFI[0,n-1],...,BLFI[m-1,n-1] fall to logic low. Afterward, the reset of memory cells C[0,n-1],...,C[m-1,n-1] is completed, and word line WL[n-1] is released at time t7.

[0120] Although Figure 10A In the specific example of -10B, the reset of two rows is described sequentially; however, it should be understood that the above can be repeated to reset as many rows as possible, and these rows do not have to be sequential (e.g., row 0 can be reset, then row 2 can be reset, then row 4 can be reset, etc.). It should also be understood that although all columns of the selected row are reset in this specific example, not all columns can be reset, regardless of which column is selected by column decoder 18a and reset by the above operation.

[0121] Since the expected reset operation (reset of rows 0 and n-1) has been performed, at time t8, MRST and PCH are released (e.g., allowed to fall to logic low), so the complementary bit lines BLN[0],...,BLN[m-1] rise back to high.

[0122] Note that the desired pattern can be formed upon reset by using the RST signal for selection. For example, some selected rows can be reset to logic 0 by multiplexing multiplexers 45a and 45b that select those rows of Vdd, and some selected rows can be reset to logic 1 by multiplexing multiplexers 45a and 45b that select those rows of ground. For example, this pattern could be a checkerboard pattern.

[0123] F. Simultaneously and quickly reset multiple rows; reset values ​​are selectable.

[0124] Figure 11 The SRAM device 50 shown is... Figure 8 The SRAM device 30"' is identical to the SRAM device 50, except that the MRST is also coupled to the row decoder 10b. This provides the SRAM device 50 with the functionality of the SRAM device 30', as it can reset multiple rows simultaneously during a single clock cycle. For example, any number of rows can be reset simultaneously (e.g., two rows can be reset simultaneously, four rows can be reset simultaneously, eight rows can be reset simultaneously, etc.). Note that the strength of the write driver 22 can be increased to enable the parallelism of resetting multiple rows simultaneously.

[0125] For further reference Figure 12A For this example, assume that it is desired to reset rows 0 and n-1 simultaneously. MRST is as follows: Figure 4 The SRAM device 30' operates as described, wherein RST is used to select the values ​​of D_int and D_int_B when the multiplexer 46a receives the assertion MRST. Figure 12A As shown in -12B, SRAM device 50 operates in the same manner as SRAM device 30', except that, as stated, the value of RST is selected from the values ​​of D_int and D_int_B when asserting MRST. Therefore, as... Figure 10A As shown, when RST is logic high and MRST is asserted, D_int is forced to logic 0 and D_int_B is forced to logic 1, and the operation is the same as the above reference. Figure 5 The operations described are the same.

[0126] Now for reference Figure 12B The description describes the operation of simultaneously resetting multiple rows to logic 1. MRST is asserted at time t0, having the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and having the effect of setting the multiplexer so that D_int is forced to logic 1 and D_int_B is forced to logic 0.

[0127] Then, at time t1, the clock signal CLK pulses, and the line decoder 18b, as shown in the figure, simultaneously asserts word lines WL[0] and WL[n-1] after the falling edge of CLK, thereby allowing the states of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1] to be flipped to logic 1 at time t2. This means that nodes BLTI[0,0],...,BLTI[m-1,0] and BLTI[0,n-1],...,BLTI[m-1,n-1] rise to logic high, and nodes BLFI[0,0],...,BLFI[m-1,0] and BLFI[0,n-1],...,BLFI[m-1,n-1] fall to logic low. Note that the states of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1] are all toggled at once. At time t3, due to the decrease of node BLFI[0,0],...,BLFI[m-1,0], bit line BL[0],...,BL[m-1] remains at logic high.

[0128] At time t4, row decoder 18b releases assertion word lines WL[0] and WL[n-1]. This completes the reset of memory cells C[0,0],...,C[m-1,0] and C[0,n-1],...,C[m-1,n-1]. It is understood here that all columns of rows 0 and n-1 have been reset simultaneously, meaning that increasing the strength of write driver 22 to help ensure sufficient capability to simultaneously reset memory cells to their desired default values ​​may be helpful.

[0129] After this, the memory cells C[0,n-1],...,C[m-1,n-1] are reset, and MRST (and therefore PCH) is released at time t5. This restores the precharge, charging the complementary bit lines BLN[0],...,BLN[m-1] back high.

[0130] G. Using a counter to control a line decoder with an optional reset value

[0131] Figure 13 The SRAM device 50' shown is... Figure 8The SRAM device 50' is identical to SRAM device 30', except that SRAM device 50' here includes a counter 19 timed by clock CLK and reset by MRST. Counter 19 is selectively coupled to line decoder 18b via transmission gate 42, which is activated when MRST is asserted to pass the output from counter 19 to line decoder 18b. Additionally, when MRST is asserted, transmission gate 41 disconnects the address input from line decoder 18b, causing line decoder 18b to operate based on the output from counter 19.

[0132] Therefore, in operation, the output of counter 19 determines which word lines WL[0],...,WL[n-1] are asserted by line decoder 18b. Counter 19 can count any increment (e.g., count 1, count 2, count 4, etc.) from an initial value (e.g., 0) to a final value (e.g., 15).

[0133] Now refer to another source Figure 14A -14B describes the operation using counter 19. (For example...) Figure 14A As shown in -14B, SRAM device 50' operates identically to SRAM device 30", except that, as stated, the value of RST is selected from the values ​​of D_int and D_int_B when MRST is asserted. Therefore, as... Figure 14A As shown, when RST is logic high and MRST is asserted, D_int is forced to logic 0 and D_int_B is forced to logic 1, and the operation is the same as the above reference. Figure 6 The same applies to sequentially resetting the desired number of rows. Counter 19 provides the address used by row decoder 18 to assert the word lines selected from WL[0],...,WL[n-1].

[0134] Now for reference Figure 14B Describe the operation of simultaneously resetting multiple rows to logic 1.

[0135] Assume that it is desired to reset all rows of memory cells in memory array 12, here rows 0 to n-1. To make this happen, MRST is asserted at time t0, which has the effect of releasing the precharge on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1], and has the effect of setting the multiplexer so that D_int is forced to logic 1 and D_int_B is forced to logic 0. It is worth noting here that the assertion of MRST resets counter 19, opens transmission gate 42 (making it act as a short circuit), and closes transmission gate 19 (making it act as an open circuit). Furthermore, at this time, column decoder 18a selects all columns, indicating that all bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] are selected.

[0136] Then, at time t1, the clock CLK pulses, and after the falling edge of the clock, counter 19 begins counting at 0, and thus outputs 0 to the row decoder first. Also after the falling edge of the clock CLK, row decoder 18b asserts the word line corresponding to the first output of counter 19, which is here word line WL[0]. This allows the state of memory cells C[0,0],...,C[m-1,0] to be toggled to logic 1 at time t2, meaning that nodes BLTI[0,0],...,BLTI[m-1,0] rise to logic high and nodes BLFI[0,0],...,BLFI[m-1,0] fall to logic low. Note that the state of memory cells C[0,0],...,C[m-1,0] is toggled all at once. At time t3, due to the decrease in nodes BLFI[0,0],...,BLFI[m-1,0], bit line BL[0],...,BL[m-1] remains at logic high. At time t4, line decoder 18b releases the assertion word line WL[0]. This completes the reset of memory cells C[0,0],...,C[m-1,0]. As explained above, at the end of the reset of memory cells C[0,0],...,C[m-1,0], MRST is not released (e.g., remains asserted), and PCH is not released (e.g., remains asserted), while precharging on bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BLN[m-1] is not performed.

[0137] At time t5, another clock pulse CLK is received, incrementing counter 19. In this example, assume that rows 2 to n-2 have already been reset at time t5, each row receives a clock pulse CLK to be reset, and counter 19 increments after each row. At time t5, the clock pulse CLK increments counter 19 to n-1, which is then output to the row decoder 18b.

[0138] For the reset of memory cell C[0,n-1],...,C[m-1,n-1], since the states of bit line BL[0],...,BL[m-1] and complementary bit line BLN[0],...,BLN[m-1] have been reset as needed, in order to reset memory cell C[0,n-1],...,C[m-1,n-1], after time t5, the line decoder 18b assertion word line WL[n-1].

[0139] The state of memory cells C[0,n-1],...,C[m-1,n-1] is toggled to logic 1 at time t6, meaning that nodes BLTI[0,n-1],...,BLTI[m-1,n-1] rise to logic high and nodes BLFI[0,n-1],...,BLFI[m-1,n-1] fall to logic low. Afterward, the reset of memory cells C[0,n-1],...,C[m-1,n-1] is completed, and word line WL[n-1] is released at time t7. At time t8, MRST is released, effectively releasing PCH, and thus charging complementary bit lines BLN[0],...,BLN[m-1] back high.

[0140] The above technology is applicable to both self-timed SRAM memories and non-self-timed SRAM memories.

[0141] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art to which this invention pertains will understand that other embodiments can be conceived without departing from the scope of the invention disclosed herein. Therefore, the scope of this disclosure will be limited only by the appended claims.

Claims

1. A method for resetting a memory, comprising: a) The bit lines are precharged by applying a precharge voltage to the bit lines of the memory array; b) Assert the signal at the reset node to thereby remove the precharge voltage from the bit line; c) Select the write driver associated with the bit line, which is associated with a column of the memory array containing the memory cell to be reset; The assertion of the signal at the reset node also causes an assertion of the input of the selected write driver, thereby causing the selected write driver to change the logic state of the bit line associated with the write driver. d) Assert the word line associated with the row of the memory containing the memory cell to be reset, thereby writing the desired logic state to all the memory cells to be reset in the column and row of the memory during the first clock cycle, and then deassert the word line; as well as e) Without first reapplying the precharge voltage to the bit line, asserting the word line associated with other rows of the memory containing the memory cell to be reset, thereby writing the desired logic state to all the memory cells to be reset in the column and the other rows of the memory during the second clock cycle, and then deasserting the word line.

2. The method according to claim 1, further comprising: f) Repeat step e) until each row containing the memory cell to be reset has reset the memory cell; and g) deasserting the signal at the reset node; and h) reapply the precharge voltage to the bit line.

3. The method of claim 1, wherein all columns contain memory cells to be reset; and wherein at c), all write drivers associated with the bit line are selected.

4. The method of claim 1, wherein the assertion of the signal at the reset node causes an assertion of the input of the selected write driver, thereby causing the selected write driver to pull the bit line associated with the write driver to logic low; wherein the desired logic state of all memory cells to be reset that have been written to the column and the row of the memory is logic 0; and wherein the desired logic state of all memory cells to be reset that have been written to the column and the other rows of the memory is logic 0.

5. The method of claim 1, wherein the assertion of the signal at the reset node causes a desired logic signal to be applied to the input of the selected write driver, thereby causing the selected write driver to drive the bit line associated with the driver to a desired logic state; wherein the desired logic state of all memory cells to be reset, written to the column and the row of the memory, represents a predefined pattern; and wherein the desired logic state of all memory cells to be reset, written to the column and the other rows of the memory, represents the predefined pattern.

6. The method of claim 1, wherein the assertion of the signal at the reset node results in an assertion of the input of the selected write driver, thereby causing the selected write driver to pull the bit line associated with the write driver to logic high; wherein the desired logic state of all memory cells to be reset that have been written to the column and the row of the memory is logic 11; and wherein the desired logic state of all memory cells to be reset that have been written to the column and the other rows of the memory is logic 1.

7. The method of claim 1, wherein the assertion of the word line associated with the row of the memory containing the memory cell to be reset causes the same logic state to be written to all the memory cells to be reset in the column and the row of the memory during the first clock cycle, and then the assertion of the word line is released.

8. The method of claim 1, further comprising using a counter to determine the row to be reset; further comprising: f) Repeat step e) until each row containing the memory cell to be reset has reset the memory cell, while incrementing the counter after each execution of step e).

9. A method for resetting a memory, comprising: a) The bit lines are precharged by applying a precharge voltage to the bit lines of the memory array; b) Assert the signal at the reset node to thereby remove the precharge voltage from the bit line; c) Select the write driver associated with the bit line, which is associated with a column of the memory array containing the memory cell to be reset; The assertion of the signal at the reset node also causes the desired logic state to be applied to the input of the selected write driver, thereby causing the selected write driver to change the logic state of the bit line associated with the write driver. as well as d) Assert each word line associated with a row of the memory containing the memory cell to be reset, thereby writing the desired logic state to all the memory cells to be reset in the column and row of the memory during a single clock cycle, and then deasserting the word line.

10. The method of claim 9, further comprising: g) De-assert the signal at the reset node; and h) Reapply the pre-charge voltage to the bit line.

11. The method of claim 9, wherein not all columns contain memory cells to be reset; and wherein at c), not all write drivers associated with the bit line are selected.

12. The method of claim 9, wherein an assertion of the signal at the reset node results in an assertion of the input to the selected write driver, thereby causing the selected write driver to pull the bit line associated with the write driver to logic low; and wherein the desired logic state of all the memory cells to be reset, written to the column and the row of the memory, is logic 0.

13. The method of claim 9, wherein the assertion of the signal at the reset node causes a desired logic signal to be applied to the input of the selected write driver, thereby causing the selected write driver to drive the bit line associated with the driver to a desired logic state; wherein the desired logic state of all the memory cells to be reset, written to the column and row of the memory, represents a predefined pattern.

14. The method of claim 9, wherein an assertion of the signal at the reset node results in an assertion of the input to the selected write driver, thereby causing the selected write driver to drive the bit line associated with the write driver to logic high; and wherein the desired logic state of all the memory cells to be reset, written to the column and the row of the memory, is logic 1.

15. A static random access memory (SRAM) device, comprising: A memory array comprising memory cells organized into rows and columns, wherein each row has a word line associated therewith and each column has a bit line and a complementary bit line associated therewith. A line decoder, configured to selectively assert word lines of desired lines; A column decoder, configured to select the desired column; A pre-charge circuit arrangement associated with the bit line and the complementary bit line; as well as A column driving circuit device configured to selectively drive the bit lines and the complementary bit lines of the desired column to opposite logic states; Among them, the assertions in response to the reset signal: The pre-charge circuit device is configured to release the pre-charge voltage applied to the bit line and the complementary bit line; The line decoder is configured to assert the word line of each desired line within a given time period, the given time period being sufficient to allow a reset of the memory cell in the desired line, wherein the precharge circuitry maintains the precharge voltage for release between the assertions of the word line; and The precharge circuit is configured to restore the precharge voltage after the given time period for the last desired row has expired.

16. The SRAM device of claim 15, wherein the row decoder is configured to selectively assert the word lines of desired rows simultaneously.

17. The SRAM device of claim 15, wherein the row decoder is configured to sequentially assert the word lines of a desired row under the control of a counter, wherein the counter is incremented between assertions of different word lines.

18. The SRAM device of claim 15, wherein the column driving circuit means drives the bit line and the complementary bit line to the opposite logic states such that the bit line is driven to a first logic state and the complementary bit line is driven to a second logic state.

19. The SRAM device of claim 15, wherein the column drive circuit means comprises: An inverter associated with each different bit line, the output of which is coupled to the bit line; as well as Multiplexing circuits, including: Each of the different first multiplexers associated with each different bit line; and Different second multiplexers are associated with each different complementary bit line; Each of the first multiplexers has: a first data input coupled to the reset signal, a second data input coupled to the column decoder, and a selection input coupled to the reset signal; Each of the second multiplexers has: a first data input coupled to the two's complement of the reset signal, a second data input coupled to the column decoder, and a selection input coupled to the reset signal; and In response to the assertion of the reset signal, each first multiplexer and each second multiplexer of each selected column transmits its first data input as an output, thereby driving the bit line and the complementary bit line of the desired column to the opposite logic state.

20. The SRAM device of claim 15, wherein the column drive circuit means comprises: An inverter associated with each different bit line, the output of which is coupled to the bit line; as well as Multiplexing circuits, including: Each of the different first multiplexers and first additional multiplexers is associated with a different bit line; and Different second multiplexers and second additional multiplexers are associated with each different complementary bit line; Each of the first additional multiplexers has: a first data input coupled to a logic high voltage, a second data input coupled to a logic low voltage, a selection input coupled to a logic state selection signal, and an output; Each of the first multiplexers has: a first data input coupled to the output of the first additional multiplexer, a second data input coupled to the column decoder, a selection input coupled to the reset signal, and an output coupled to the inverter for its respective bit line; Each of the second additional multiplexers has: a first data input coupled to a logic high voltage, a second data input coupled to a logic low voltage, a selection input coupled to a logic state selection signal, and an output; Each of the second multiplexers has: a first data input coupled to the output of the first additional multiplexer, a second data input coupled to the column decoder, a selection input coupled to the reset signal, and an output coupled to its corresponding complementary bit line; and In response to the assertion of the reset signal, each first multiplexer and each second multiplexer of each selected column transmits its first data input as an output, thereby driving the bit line and the complementary bit line of the desired column to the opposite logic state.

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