Decoder, decoding method, memory system, and controller

Abstract

The invention provides a decoder, a decoding method, a memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, wherein the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check formula, the check matrix and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to select a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the checkout weight in the initial iteration; distributing one flipping threshold in the initial threshold sequence to a bit flipping circuit; and the bit flipping circuit is configured to output the to-be-decoded code word in the next iteration based on the comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value allocated by the processor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a decoder, decoding method, memory system, and controller. Background Technology

[0002] Memory devices are storage equipment used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, and suitable erase / encode speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have considerable room for improvement. Summary of the Invention

[0003] This disclosure provides a decoder, a decoding method, a memory system, and a controller.

[0004] In a first aspect, embodiments of this disclosure provide a decoder, including a first processing circuit, a second processing circuit, a processor, and a bit-flipping circuit; wherein,

[0005] The first processing circuit is configured to: obtain the check formula and the check formula weight based on the codeword to be decoded and the check matrix in the current iteration;

[0006] The second processing circuit is configured to: obtain the energy of the codeword to be decoded in the current iteration based on the check formula, the check matrix, and the flip state of the codeword to be decoded in the current iteration;

[0007] The processor is configured to: in the initial iteration, select one of the preset threshold sequences as the initial threshold sequence based on the check weight; and assign a flip threshold from the initial threshold sequence to the bit flipping circuit;

[0008] The bit-flipping circuit is configured to output the codeword to be decoded in the next iteration based on a comparison between the energy of the codeword to be decoded in the current iteration and the flipping threshold assigned by the processor.

[0009] In some implementations, the processor is specifically configured to:

[0010] In the initial iteration, N+1 preset threshold sequences are obtained, the verification weight is compared with N first thresholds, and based on the comparison result, one of the preset threshold sequences is selected from the N+1 preset threshold sequences as the initial threshold sequence; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1;

[0011] In the Lth iteration, the Lth flip threshold in the initial threshold sequence is assigned to the bit flip circuit; where L is a positive integer less than or equal to M.

[0012] In some implementations, N is 1; the processor is specifically configured as follows:

[0013] In the initial iteration, the verification weight is compared with a first threshold.

[0014] If the checksum weight is greater than the first threshold, a preset threshold sequence corresponding to the checksum weight being greater than the first threshold is selected as the initial threshold sequence; or, if the checksum weight is less than or equal to the first threshold, a preset threshold sequence corresponding to the checksum weight being less than or equal to the first threshold is selected as the initial threshold sequence.

[0015] In some implementations, N is greater than 1; the processor is specifically configured as follows:

[0016] In the initial iteration, the verification weight is compared with multiple first thresholds to determine the threshold range in which the verification weight is located;

[0017] Select a preset threshold sequence corresponding to the threshold interval where the verification weight is located as the initial threshold sequence.

[0018] In some implementations, the processor is further configured to:

[0019] In the M+Xth iteration, a cyclic threshold sequence is obtained, and one of the flip thresholds in the cyclic threshold sequence is assigned to the bit flipping circuit; where X is a positive integer.

[0020] In some implementations, the processor is further configured to:

[0021] In the (M+1)th iteration, P+1 preset cyclic sequences are obtained. The check weight in the first iteration or the check weight in the (M+1)th iteration is compared with P second thresholds. Based on the comparison result, one of the preset cyclic sequences is selected from the P+1 preset cyclic sequences as the cyclic threshold sequence; where P is a positive integer.

[0022] In some embodiments, the second processing circuit is specifically configured as follows:

[0023] Perform a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration;

[0024] Based on the flip state of each bit in the codeword to be decoded in the current iteration, the tag value corresponding to each bit is obtained;

[0025] A second calculation is performed on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0026] In some implementations, the bit-flipping circuit is specifically configured as follows:

[0027] Compare the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold;

[0028] The bit is flipped if its energy is greater than the flip threshold, or the bit is kept unchanged if its energy is less than or equal to the flip threshold, so as to obtain the decoded codeword in the current iteration.

[0029] The codeword decoded in the current iteration is output as the codeword to be decoded in the next iteration.

[0030] In some embodiments, the first processing circuit is specifically configured as follows:

[0031] A third calculation is performed on the codeword to be decoded in the current iteration and the parity check matrix to obtain the parity formula;

[0032] Calculate the number of bits that are 1 in the check expression to obtain the check expression weight.

[0033] In some implementations, the decoder further includes:

[0034] The output circuit is configured to output the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

[0035] Secondly, embodiments of this disclosure provide a decoding method, including:

[0036] The check formula and check formula weight are obtained based on the codeword to be decoded and the check matrix in the current iteration.

[0037] The energy of the codeword to be decoded in the current iteration is obtained based on the verification formula, the verification matrix, and the flip state of the codeword to be decoded in the current iteration.

[0038] In the initial iteration, based on the verification weight, one of the preset threshold sequences is selected as the initial threshold sequence from multiple preset threshold sequences;

[0039] The codeword to be decoded in the next iteration is output based on the comparison result between the energy of the codeword to be decoded in the current iteration and one of the flip thresholds in the initial threshold sequence.

[0040] In some implementations, the step of selecting one preset threshold sequence from multiple preset threshold sequences as an initial threshold sequence based on the check weight in the initial iteration, and the step of outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and one of the flip thresholds in the initial threshold sequence, includes:

[0041] In the initial iteration, N+1 preset threshold sequences are obtained, the verification weight is compared with N first thresholds, and based on the comparison result, one of the preset threshold sequences is selected from the N+1 preset threshold sequences as the initial threshold sequence; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1;

[0042] In the Lth iteration, the codeword to be decoded in the next iteration is output based on the comparison result between the energy of the codeword to be decoded in the current iteration and the Lth flip threshold in the initial threshold sequence; where L is a positive integer less than or equal to M.

[0043] In some implementations, N is 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting one of the preset threshold sequences from N+1 preset threshold sequences as the initial threshold sequence based on the comparison results, includes:

[0044] In the initial iteration, the verification weight is compared with a first threshold.

[0045] If the checksum weight is greater than the first threshold, a preset threshold sequence corresponding to the checksum weight being greater than the first threshold is selected as the initial threshold sequence; or, if the checksum weight is less than or equal to the first threshold, a preset threshold sequence corresponding to the checksum weight being less than or equal to the first threshold is selected as the initial threshold sequence.

[0046] In some implementations, N is greater than 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting one of the preset threshold sequences from N+1 preset threshold sequences as the initial threshold sequence based on the comparison results, includes:

[0047] In the initial iteration, the verification weight is compared with multiple first thresholds to determine the threshold range in which the verification weight is located;

[0048] Select a preset threshold sequence corresponding to the threshold interval where the verification weight is located as the initial threshold sequence.

[0049] In some embodiments, the decoding method further includes:

[0050] In the (M+X)th iteration, a cyclic threshold sequence is obtained, and the codeword to be decoded in the next iteration is output based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the cyclic threshold sequence; where X is a positive integer.

[0051] In some embodiments, the decoding method further includes:

[0052] In the (M+1)th iteration, P+1 preset cyclic sequences are obtained. The check weight in the first iteration or the check weight in the (M+1)th iteration is compared with P second thresholds. Based on the comparison result, one of the preset cyclic sequences is selected from the P+1 preset cyclic sequences as the cyclic threshold sequence; where P is a positive integer.

[0053] In some implementations, obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration includes:

[0054] Perform a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration;

[0055] Based on the flip state of each bit in the codeword to be decoded in the current iteration, the tag value corresponding to each bit is obtained;

[0056] A second calculation is performed on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0057] In some implementations, the step of outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence includes:

[0058] Compare the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold;

[0059] The bit is flipped if its energy is greater than the flip threshold, or the bit is kept unchanged if its energy is less than or equal to the flip threshold, so as to obtain the decoded codeword in the current iteration.

[0060] The codeword decoded in the current iteration is output as the codeword to be decoded in the next iteration.

[0061] In some implementations, obtaining the check expression and check expression weight based on the codeword to be decoded and the check matrix in the current iteration includes:

[0062] A third calculation is performed on the codeword to be decoded in the current iteration and the parity check matrix to obtain the parity formula;

[0063] Calculate the number of bits that are 1 in the check expression to obtain the check expression weight.

[0064] In some embodiments, the decoding method further includes:

[0065] Based on the fact that each bit of the check expression in the current iteration is 0, the codeword to be decoded in the current iteration is output as the final decoded codeword.

[0066] Thirdly, embodiments of this disclosure provide a memory system, including:

[0067] The memory is configured to output read data;

[0068] The decoder described in any of the above embodiments is configured to decode the codewords to be decoded in the read data.

[0069] In some embodiments, the memory system further includes:

[0070] The encoder is configured to receive written data and encode the written data;

[0071] The memory is also configured to receive encoded write data.

[0072] In some embodiments, the memory system includes a controller coupled to the memory, the controller including the decoder and the encoder.

[0073] Fourthly, embodiments of this disclosure provide a controller, including:

[0074] The interface is configured to receive and read data.

[0075] The decoder described in any of the above embodiments is configured to decode the codewords to be decoded in the read data.

[0076] In the technical solution provided in this disclosure, the processor can acquire multiple pre-set threshold sequences and select one of the multiple pre-set threshold sequences as the initial threshold sequence based on the relationship between the initial check weight and the first threshold. In each iteration, a flip threshold from the initial threshold sequence is assigned to the bit-flipping circuit, which determines whether to flip the bits of the codeword to be decoded in the current iteration based on the relationship between the flip threshold and the check weight. On the one hand, selecting the initial threshold sequence based on the initial check weight can provide different flip thresholds for codewords to be decoded with different error rates, which can improve the flexibility and specificity of the flip threshold selection, thereby improving the decoding performance of the decoder. On the other hand, the initial threshold sequence includes multiple flip thresholds, which can avoid the extension of decoding time caused by the need to determine the corresponding flip threshold through a complex algorithm in each iteration, thereby improving the decoding efficiency of the decoder. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. Figure 1 .

[0078] Figure 2 This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure.

[0079] Figure 3 This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure.

[0080] Figure 4 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure.

[0081] Figure 5 This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present disclosure.

[0082] Figure 6 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. Figure 2 .

[0083] Figure 7 A schematic diagram of the decoder structure provided in an embodiment of this disclosure Figure 1 .

[0084] Figure 8 A flowchart of a decoding process provided in one embodiment of this disclosure.

[0085] Figure 9 A schematic diagram of the decoder structure provided in an embodiment of this disclosure Figure 2 .

[0086] Figure 10This is a schematic diagram of the structure of a first processing circuit provided in an embodiment of the present disclosure.

[0087] Figure 11 This is a schematic diagram of the structure of a second processing circuit provided in an embodiment of the present disclosure.

[0088] Figure 12 This is a schematic diagram of the structure of a bit-flipping circuit provided in an embodiment of the present disclosure.

[0089] Figure 13 A schematic diagram of the circuit structure of a processor provided as a specific example of this disclosure Figure 1 .

[0090] Figure 14 A schematic diagram of the circuit structure of a processor provided as a specific example of this disclosure Figure 2 .

[0091] Figure 15 This is a flowchart illustrating a decoding method provided in an embodiment of the present disclosure. Detailed Implementation

[0092] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0093] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0094] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0095] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0096] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0097] To improve the reliability of data transmission and storage, error-correcting code (ECC) technology has been widely used in digital communication fields, such as wireless and fiber optic communications, and in data storage fields, such as memory systems. Among various error-correcting codes, LDPC (Low Density Parity Check) code is a parallel iterative decoding algorithm based on sparse matrices. It has performance approaching the Shannon limit, is simple to decode, and can be performed in parallel, making it one of the most widely used error-correcting codes.

[0098] As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production cost, and suitable erasure speed. During data transmission and storage in NAND memory, data errors may occur due to hardware failures, software failures, hard disk errors, etc. To ensure the integrity of user data, LDPC codes have been proposed for error detection and correction of data stored in memory systems including NAND memory. The memory system provided in this disclosure will be described below using a memory system including three-dimensional NAND memory as an example.

[0099] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host system 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host system 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host system 101 may be configured to send data to or receive data from the memory system 102.

[0100] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0101] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0102] In such Figure 2 In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The memory card connector 202 is coupled to the host 101. Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1 The SSD connector 204 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0103] Figure 4A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0104] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0105] like Figure 4As shown, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0106] like Figure 4 As shown, the memory cell string 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0107] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0108] Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register set 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0109] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0110] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0111] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register set 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bitline driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0112] Figure 6 A system diagram including a host and a memory system is provided for embodiments of this disclosure, such as... Figure 6As shown, the memory system 102 is connected to the host 101. The memory system 102 may include a memory controller 104 and a memory device 103. The memory controller 104 controls the memory device 103 to perform read, write, and erase operations. The memory controller 104 and the memory device 103 can also be coupled in any suitable manner. The memory controller 104 may include a host interface (I / F) 1041, a memory interface (I / F) 1042, a control unit 1043, an error correction module 1044, a cache 1047, and a bus 1040. The host interface 1041 is the connection interface between the host 101 and the memory controller 104, allowing the host 101 and the memory controller 104 to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1042 is the connection interface between the memory controller 104 and the memory device 103, and is used to implement data transmission between the memory controller 104 and the memory device 103. The control unit 1043 is used to control the memory system 102 as a whole.

[0113] In some specific embodiments, the control unit 1043 may include one or more units with logic operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0114] In some specific embodiments, cache 1047 is used to cache data and can be a volatile memory device with relatively fast read and write speed, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM).

[0115] In some specific embodiments, the error correction module 1044 can be configured to encode and decode data in the memory system 102 using error correction code technology. Specifically, the error correction module 1044 may include an encoder 1045 and a decoder 1046, wherein the encoder 1045 can be configured to encode data to be written to the memory device during a write operation; and the decoder 1046 can be configured to decode codewords to be decoded in the read data during a read operation.

[0116] In some embodiments, during the decoding of the codeword to be decoded in the read data using the decoder 1046, the flipping threshold used to determine whether the bits in the codeword to be decoded need to be flipped decreases monotonically to a fixed value as the number of decoding iterations increases, indicating that the decoding performance of the decoder 1046 needs further improvement. To address this, the present disclosure proposes the following implementation methods.

[0117] This disclosure provides a decoder, Figure 7 A schematic diagram of the decoder provided in the embodiments of this disclosure is shown below. Figure 7 As shown, the decoder 1046 includes: a first processing circuit 501, a second processing circuit 502, a processor 503, and a bit-flipping circuit 504; wherein, the first processing circuit 501 is configured to: obtain a check expression and a check expression weight based on the codeword to be decoded in the current iteration and the check matrix; the second processing circuit 502 is configured to: obtain the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flipping state of the codeword to be decoded in the current iteration; the processor 503 is configured to: in the first iteration, select one of the preset threshold sequences as an initial threshold sequence based on the check expression weight; allocate a flipping threshold from the initial threshold sequence to the bit-flipping circuit; the bit-flipping circuit 504 is configured to: output the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flipping threshold allocated by the processor.

[0118] In this embodiment of the disclosure, the processor can be configured to select a preset threshold sequence as the initial threshold sequence from multiple preset threshold sequences in the initial iteration based on the check weight calculated by the original codeword to be decoded and the check matrix. The initial threshold sequence may include multiple flip thresholds. In each iteration, the processor can assign one flip threshold from the initial threshold sequence to the bit-flipping circuit, so that the bit-flipping circuit can determine whether to perform bit flipping on the codeword to be decoded based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flip threshold. That is, the processor can be configured to select the corresponding initial threshold sequence based on the bit error rate of the original codeword to be decoded, instead of using the same flip threshold or a threshold sequence composed of multiple flip thresholds for any codeword to be decoded. This can improve the flexibility of the decoder in performing decoding operations, reduce decoding time, and improve decoding performance.

[0119] Figure 8 This is a schematic flowchart illustrating the decoding process provided in an embodiment of this disclosure. (Refer to...) Figure 8The main process of decoding using a decoder in this embodiment includes: multiplying the parity check matrix by the original codeword to be decoded to obtain the parity check formula. Each bit in the parity check formula represents the result of parity check, where 0 represents passing and 1 represents a parity error. The weight of the parity check formula can be obtained by calculating the number of bits that are 1 in the parity check formula. The original codeword to be decoded can be a vector. If each bit in the parity check formula is 0, the weight of the parity check formula is 0, indicating successful decoding, and the decoder can output the original codeword to be decoded as the final decoded codeword. If there is a bit that is 1 in the parity check formula, the weight of the parity check formula is not 0, and iteration is required. Specifically, the original codeword to be decoded is used as the codeword to be decoded in the first iteration. In the first iteration, the energy of the original codeword to be decoded is calculated. The energy of the original codeword to be decoded can be understood as the energy of each bit in the original codeword to be decoded, and the energy of the original codeword to be decoded is compared with the flip threshold. If the energy of a bit in the original codeword to be decoded is greater than the flip threshold, the bit is flipped; if the energy of a bit in the original codeword to be decoded is less than or equal to the flip threshold, the bit remains unchanged, thus obtaining the decoded codeword in the first iteration. The parity-check matrix is ​​multiplied by the decoded codeword from the first iteration to obtain the parity expression and its weight. If the parity-check weight is 0, decoding is successful, and the decoder can output the decoded codeword from the first iteration as the final decoded codeword. If the parity-check weight is not 0, a second iteration is performed, in which the codeword to be decoded is the decoded codeword from the first iteration. Each iteration follows a similar process and will not be described further. Decoding ends when the parity-check weight is 0 in any iteration; otherwise, the next iteration begins.

[0120] Figure 9 This is a schematic diagram of the structure of a decoder provided in an embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of a first processing circuit provided in an embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of a second processing circuit provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of a bit-flipping circuit provided in an embodiment of this disclosure. The following is in conjunction with... Figures 9 to 12 The decoder and its decoding process provided in the embodiments of this disclosure will be described in detail.

[0121] Reference Figure 9The decoder 1046 also includes a first selector 506, a first buffer 507, and a second buffer 508. The first selector 506 can select either the original codeword to be decoded or the iterative codeword to be decoded as output based on whether the current iteration is the first iteration. If the current iteration is the first iteration, the first selector 506 selects the original codeword to be decoded as output; if the current iteration is not the first iteration, the first selector 506 selects the iterative codeword to be decoded as output. Here, the iterative codeword to be decoded is the codeword decoded in the previous iteration. The codeword output from the first selector 506 can be buffered in the first buffer 507, and the original codeword to be decoded can be buffered in the second buffer 508.

[0122] In some embodiments, the first processing circuit 501 is specifically configured to: perform a third calculation on the codeword to be decoded in the current iteration and the parity check matrix to obtain the parity check formula; calculate the number of bits that are 1 in the parity check formula to obtain the weight of the parity check formula.

[0123] Reference Figure 9 as well as Figure 10 The first processing circuit 501 includes a third calculation circuit 515 and a fourth calculation circuit 516, wherein the third calculation circuit 515 is connected to the first buffer 507, and the fourth calculation circuit 516 is connected to the third calculation circuit 515. In some specific embodiments, the third calculation circuit 515 may include a matrix multiplier, and the fourth calculation circuit 516 may include an adder. The decoder also includes a third buffer 509, in which the parity check matrix is ​​cached, and the third buffer 509 is connected to the third calculation circuit 515. The third calculation circuit 515 receives the codeword to be decoded in the current iteration from the first buffer 507 and the parity check matrix from the third buffer 509. The third calculation circuit 515 multiplies the parity check matrix with the codeword to be decoded to obtain the parity expression. In this embodiment, the parity expression can be a vector, and each element in the vector can be obtained by performing a corresponding multiplication and addition operation on an element of the codeword to be decoded and a portion of the elements in the parity check matrix, and the addition operation is modulo-2 addition (1+1=0). The fourth calculation circuit 516 is configured to calculate the number of bits that are 1 in the check expression, thereby obtaining the check expression weight.

[0124] In some embodiments, refer to Figure 9 The decoder further includes an output circuit 505 configured to output the codeword to be decoded in the current iteration as the final decoded codeword based on the fact that each bit of the check expression in the current iteration is 0.

[0125] In some specific examples, refer to Figure 9The output circuit 505 includes a third logic circuit 512 and an output switch 518. The third logic circuit 512 is connected to the third calculation circuit 515, and the output switch 518 is connected to both the third logic circuit 512 and the first buffer 507. Specifically, the third logic circuit 512 can be an OR gate, which can determine whether each bit in the check expression is 0. The output switch 518 can be closed based on each bit in the check expression being 0, thereby allowing the codeword to be decoded in the current iteration buffered in the first buffer 507 to be output as the final codeword. The output switch 518 can also be open based on a bit being 1 in the check expression. It should be noted that the third logic circuit 512 can also be other combinations of logic gates that achieve the same function.

[0126] In some embodiments, the second processing circuit 502 is specifically configured to: perform a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtain a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and perform a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded in the current iteration.

[0127] Reference Figure 9 as well as Figure 11 The second processing circuit 502 may specifically include a first calculation circuit 513, a second calculation circuit 514, and a second logic circuit 511. The first calculation circuit 513 may be connected to both the third calculation circuit 515 and the third buffer 509, and the second logic circuit 511 may be connected to both the first buffer 507 and the second buffer 508. The first calculation circuit 513 may specifically be a matrix multiplier. It multiplies the parity check matrix with the parity check expression to obtain the number of error bits. This number of error bits can be a vector, where each element represents the number of errors corresponding to one bit in the codeword to be decoded in the current iteration. The second logic circuit 511 can be an XOR gate. Based on the codeword to be decoded in the current iteration cached in the first buffer 507 and the original codeword to be decoded cached in the second buffer 508, the second logic circuit 511 can determine whether each bit of the codeword to be decoded in the current iteration has been flipped. For example, if a bit in the codeword to be decoded in the current iteration is the same as the bit in the original codeword to be decoded, then the bit has not been flipped, and the bit's flag value is 0; if a bit in the codeword to be decoded in the current iteration is different from the bit in the original codeword to be decoded, then the bit has been flipped, and the bit's flag value is 1. It should be noted that the second logic circuit 511 can also be a combination of other logic gates that achieve the same function.

[0128] In some embodiments, the bit-flipping circuit 504 is specifically configured to: compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold in the current iteration; flip the bit if the energy of the bit is greater than the flipping threshold in the current iteration, or keep the bit unchanged if the energy of the bit is less than or equal to the flipping threshold in the current iteration, so as to obtain the decoded codeword in the current iteration; and output the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0129] Reference Figure 9 as well as Figure 12 The bit-flipping circuit 504 includes a bit-flipping determination circuit 517 and a first logic circuit 510. The bit-flipping determination circuit 517 is connected to the second calculation circuit 514, the processor 503, and the first logic circuit 510. The first logic circuit 510 is connected to the first buffer 507 and the first selector 506. The bit-flipping determination circuit 517 can be configured to compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold in the current iteration. In some specific examples, if the energy of a bit in the codeword to be decoded in the current iteration is greater than the flipping threshold, the flipping flag value of that bit is set to 1; if the energy of a bit in the codeword to be decoded in the current iteration is less than or equal to the flipping threshold, the flipping flag value of that bit is set to 0. The first logic circuit 510 can be an XOR gate. The first logic circuit 510 performs an XOR operation on each bit in the codeword to be decoded in the current iteration with the corresponding bit's flipping flag value to obtain the decoded codeword in the current iteration. In other specific instances, if the energy of a bit in the codeword to be decoded in the current iteration is greater than the flip threshold, the flip flag value of that bit is set to 0; if the energy of a bit in the codeword to be decoded in the current iteration is less than or equal to the flip threshold, the flip flag value of that bit is set to 1. The first logic circuit 510 can be an XNOR gate. The first logic circuit 510 performs an XNOR operation on each bit in the codeword to be decoded in the current iteration with the corresponding bit's flip flag value, thereby obtaining the decoded codeword in the current iteration, i.e. Figure 9 The iterative codeword to be decoded in the circuit. It should be noted that the first logic circuit 510 can also be a combination of other logic gates to achieve the same function.

[0130] In this embodiment of the disclosure, the flip threshold in each iteration can be allocated by the processor 503 to the bit flipping circuit 504. Here, the processor 503 can be the control unit in the memory controller, or it can be a hardware processor independent of the control unit of the memory system.

[0131] In some embodiments, the processor 503 is specifically configured to: in the initial iteration, acquire N+1 preset threshold sequences, compare the checksum weight with N first thresholds, and select one preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence based on the comparison result; N is a positive integer. Here, the checksum weight in the initial iteration is the initial checksum weight of the codeword to be decoded in the read data.

[0132] In some embodiments, N can be 1, and the processor 503 is specifically configured to: in the initial iteration, compare the verification weight with a first threshold; select a preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence if the verification weight is greater than the first threshold, or select a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence if the verification weight is less than or equal to the first threshold.

[0133] In some embodiments, N can be greater than 1, and the processor 503 is specifically configured to: in the initial iteration, compare the verification weight with multiple first thresholds to determine the threshold interval in which the verification weight is located; and select a preset threshold sequence corresponding to the threshold interval in which the verification weight is located as the initial threshold sequence. Here, the values ​​of the multiple first thresholds can be different from each other.

[0134] In some embodiments, the initial threshold sequence includes M flip thresholds, where M is an integer greater than 1; the processor 503 is specifically configured to: in the Lth iteration, assign the Lth flip threshold in the initial threshold sequence to the bit flip circuit 504; where L is a positive integer less than or equal to M.

[0135] In some specific examples, the processor 503 may sequentially distribute the M flip thresholds in the initial threshold sequence to the bit flip circuit 504 in a certain order. For example, the processor 503 may distribute the M flip thresholds in the initial threshold sequence to the bit flip circuit 504 in the order in which the flip thresholds are arranged in the initial threshold sequence, but this disclosure is not limited thereto.

[0136] In this embodiment, the processor 503 can acquire multiple preset threshold sequences and select one of the preset threshold sequences as the initial threshold sequence based on the relationship between the initial check weight and the first threshold. In each iteration, a flip threshold from the initial threshold sequence is assigned to the bit-flipping circuit, which determines whether to flip the bits of the codeword to be decoded in the current iteration based on the relationship between the flip threshold and the check weight. On the one hand, selecting the initial threshold sequence based on the initial check weight can provide different flip thresholds for codewords to be decoded with different error rates, improving the flexibility and specificity of the flip threshold selection, thereby improving the decoding performance of the decoder. On the other hand, including multiple flip thresholds in the initial threshold sequence avoids the need to determine the corresponding flip threshold through a complex algorithm in each iteration, which would prolong the decoding time and improve the decoding efficiency of the decoder.

[0137] In some embodiments, when all M flip thresholds in the initial threshold sequence have been assigned to the bit flip circuit, and the bits in the check formula obtained by iterating the codeword to be decoded and the check matrix are still not all 0, indicating that the decoding process still needs to continue, the processor 503 is further configured to: in the M+Xth iteration, obtain the cyclic threshold sequence and assign one flip threshold in the cyclic threshold sequence to the bit flip circuit; X is a positive integer.

[0138] In some embodiments, the processor 503 is further configured to: acquire P+1 preset cyclic sequences, compare the check weight in the first iteration or the check weight in the M+1th iteration with P second thresholds, and select a preset cyclic sequence from the P+1 preset cyclic sequences as the cyclic threshold sequence according to the comparison result; P is a positive integer.

[0139] In some specific examples, refer to Figure 9 The decoder 1046 may also include a fourth buffer 519, which may be configured to store a preset threshold sequence and a preset loop sequence, and the processor 503 may be configured to retrieve the preset threshold sequence and the preset loop sequence from the fourth buffer 519.

[0140] In a specific example, in conjunction with reference Figure 6 and Figure 9 For the decoder 1046 in the memory system 102, the preset threshold sequence and the preset loop sequence can be configured to be stored in the memory device 103. When the memory system 102 is powered on, the multiple preset threshold sequences stored in the memory device 103 can be read out and cached in the fourth buffer 519.

[0141] In this embodiment, after all the flip thresholds in the initial threshold sequence have been used up, the processor 503 can use one of a plurality of preset cyclic sequences as a cyclic threshold sequence. In each subsequent iteration, the processor 503 can allocate one flip threshold from the cyclic threshold sequence to the bit-flipping circuit 504, and the plurality of flip thresholds in the cyclic threshold sequence can be reused, thereby saving cache space used to store the preset threshold sequence and the preset cyclic sequence. In addition, the processor 503 can select the corresponding preset cyclic sequence as the cyclic threshold sequence based on the threshold range where the initial check weight or the check weight after the initial threshold sequence has been used up, which can further allocate different flip thresholds to codewords to be decoded with different error rates, thereby further improving decoding performance.

[0142] Figure 13 and Figure 14 The following are schematic diagrams of partial circuit structures in processor 503 provided in two specific examples of this disclosure. The flip threshold allocation process of processor 503 will be described below with reference to specific examples.

[0143] In a specific example, such as Figure 13 As shown, the processor 503 may include a second selector 521 and a third selector 522. The input of the second selector 521 can receive two preset threshold sequences. One of the preset threshold sequences corresponds to a checksum weight greater than a first threshold, and the other preset threshold sequence corresponds to a checksum weight less than or equal to the first threshold. The control terminal of the second selector 521 can receive the comparison result between the initial checksum weight and the first threshold. The second selector 521 can be configured to: output the preset threshold sequence corresponding to the checksum weight being greater than the first threshold if the checksum weight is greater than the first threshold, or output the preset threshold sequence corresponding to the checksum weight being less than or equal to the first threshold if the checksum weight is less than or equal to the first threshold. The input of the third selector 522 can receive a cyclic threshold sequence. The third selector 522 can be configured to: output the flip threshold in the initial threshold sequence when the initial threshold sequence is not used up; and output the flip threshold in the cyclic threshold sequence after the initial threshold sequence is used up.

[0144] In another specific example, such as Figure 14As shown, processor 503 may include a fourth selector 523, a fifth selector 524, and a sixth selector 525. The input of the fourth selector 523 can receive four preset threshold sequences. Processor 503 can be configured to: in the initial iteration, compare the checksum weight with three first thresholds to determine the threshold interval where the initial checksum weight is located; the fourth selector 523 can be configured to: output the preset threshold sequence corresponding to the threshold interval among the four preset threshold sequences as the initial threshold sequence. The input of the fifth selector 524 can receive three preset loop sequences. Processor 503 can be configured to: in the (M+1)th iteration, compare the initial checksum weight or the checksum weight in the current iteration with two second thresholds to determine the threshold interval where the initial checksum weight or the checksum weight in the current iteration is located, where M is the number of flipped thresholds in the initial threshold sequence; the fifth selector 524 can be configured to: output the preset loop sequence corresponding to the threshold interval among the three preset loop sequences as the loop threshold sequence. The sixth selector 525 can be configured to: output the flip threshold in the initial threshold sequence when the initial threshold sequence is not used up; and output the flip threshold in the cyclic threshold sequence after the initial threshold sequence is used up.

[0145] It should be noted that in the above examples, the number of preset threshold sequences, the number of preset loop sequences, and the number of flip thresholds in each sequence are merely examples, and this disclosure does not impose any specific limitations on them, nor does this disclosure impose any specific limitations on the size of each flip threshold.

[0146] In this embodiment of the disclosure, when the preset threshold sequence is N+1 and the preset cyclic sequence is P+1, the processor 503 can be configured to allocate the flip threshold of one of the threshold sequence combinations of (N+1)*(P+1) threshold sequence combinations to the bit flip circuit when performing decoding operations on the codeword to be decoded, thereby improving the flexibility of the flip threshold allocation and improving the decoding efficiency and decoding performance of the decoder.

[0147] Based on the decoder described above, this disclosure also provides a controller, including: an interface configured to receive read data; and a decoder described in any of the above embodiments configured to decode the codewords to be decoded in the read data.

[0148] The controller here can be, for example Figure 1 as well as Figure 6 The memory controller 104 shown here. The interface here can be as follows: Figure 6 The memory interface 1042 shown is shown.

[0149] Based on the decoder described above, this disclosure also provides a memory system, including: a memory configured to output read data; and a decoder described in any of the above embodiments configured to decode the codeword to be decoded in the read data.

[0150] In some embodiments, the memory system further includes: an encoder configured to: receive write data and encode the write data; the memory is further configured to: receive the encoded write data.

[0151] In some embodiments, the memory system includes a controller coupled to the memory, the controller including the decoder and the encoder.

[0152] The structure and composition of the memory system here can be referenced from the... Figures 1 to 6 For the sake of brevity, a detailed introduction will not be repeated. The memory here can be, for example... Figures 1 to 6 The memory device 103 shown here. The controller here can be, for example, Figure 1 as well as Figure 6 The memory controller 104 shown is illustrated.

[0153] Based on the decoder described above, this disclosure also provides a decoding method. Figure 15 This is a flowchart illustrating the decoding method provided in the embodiments of this disclosure, as shown below. Figure 15 As shown, the decoding method includes: obtaining a check expression and a check expression weight based on the codeword to be decoded and the check matrix in the current iteration; obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration; in the first iteration, selecting one of the preset threshold sequences as the initial threshold sequence based on the check expression weight; and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and one of the flip thresholds in the initial threshold sequence.

[0154] In some embodiments, the step of selecting a preset threshold sequence as an initial threshold sequence from multiple preset threshold sequences based on the check weight in the initial iteration, and the step of outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence, includes: in the initial iteration, obtaining N+1 preset threshold sequences, comparing the check weight with N first thresholds, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; in the Lth iteration, outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and the Lth flip threshold in the initial threshold sequence; L is a positive integer less than or equal to M.

[0155] In some embodiments, N is 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting one of the preset threshold sequences from N+1 preset threshold sequences as the initial threshold sequence based on the comparison result, includes: in the initial iteration, comparing the verification weight with one of the first thresholds; selecting the preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence based on the verification weight being greater than the first threshold, or selecting the preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence based on the verification weight being less than or equal to the first threshold.

[0156] In some embodiments, N is greater than 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting one of the preset threshold sequences from N+1 preset threshold sequences as the initial threshold sequence based on the comparison results, includes: in the initial iteration, comparing the verification weight with multiple first thresholds to determine the threshold interval in which the verification weight is located; and selecting one of the preset threshold sequences corresponding to the threshold interval in which the verification weight is located as the initial threshold sequence.

[0157] In some embodiments, the decoding method further includes: in the M+Xth iteration, obtaining a cyclic threshold sequence, and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the cyclic threshold sequence; where X is a positive integer.

[0158] In some embodiments, the decoding method further includes: in the (M+1)th iteration, obtaining P+1 preset cyclic sequences, comparing the check weight in the first iteration or the check weight in the (M+1)th iteration with P second thresholds, and selecting one of the preset cyclic sequences as the cyclic threshold sequence according to the comparison result; where P is a positive integer.

[0159] In some embodiments, obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration includes: performing a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtaining a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and performing a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0160] In some embodiments, outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence includes: comparing the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold; flipping the bit if the energy of the bit is greater than the flip threshold, or keeping the bit unchanged if the energy of the bit is less than or equal to the flip threshold, to obtain the decoded codeword in the current iteration; and outputting the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0161] In some embodiments, obtaining the check expression and check expression weight based on the codeword to be decoded and the check matrix in the current iteration includes: performing a third calculation on the codeword to be decoded and the check matrix in the current iteration to obtain the check expression; and calculating the number of bits that are 1 in the check expression to obtain the check expression weight.

[0162] In some embodiments, the decoding method further includes: outputting the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

[0163] Based on the above decoding method, this disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the decoding method described in any of the above embodiments.

[0164] Here, implementing all or part of the decoding methods in the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. In some specific embodiments, the computer-readable storage medium 601 can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above memory devices.

[0165] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0166] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0167] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A decoder, characterized by The first processing circuit, the second processing circuit, the processor and the bit flipping circuit are included; wherein, The first processing circuit is configured to obtain a check equation and a check equation weight based on a to-be-decoded codeword in a current iteration and a check matrix; The second processing circuit is configured to obtain an energy of the to-be-decoded codeword in the current iteration based on the check equation, the check matrix and a flipping state of the to-be-decoded codeword in the current iteration; The processor is configured to select one of a plurality of preset threshold sequences as an initial threshold sequence based on the check equation weight in a first iteration; and assign one flipping threshold in the initial threshold sequence to the bit flipping circuit; The bit flipping circuit is configured to output a to-be-decoded codeword in a next iteration based on a comparison result of the energy of the to-be-decoded codeword in the current iteration and the flipping threshold assigned by the processor.

2. The decoder of claim 1, wherein, The processor is specifically configured to: In the first iteration, obtain N+1 preset threshold sequences, compare the check equation weight with N first thresholds, and select one of the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result; The initial threshold sequence includes M flipping thresholds; the N is a positive integer; and the M is an integer greater than 1; In the Lth iteration, assign an Lth flipping threshold in the initial threshold sequence to the bit flipping circuit; The L is a positive integer less than or equal to the M.

3. The decoder of claim 2, wherein, The N is 1; and the processor is specifically configured to: In the first iteration, compare the check equation weight with one of the first thresholds; According to the check equation weight being greater than the first threshold, select a preset threshold sequence corresponding to the check equation weight being greater than the first threshold as the initial threshold sequence, or according to the check equation weight being less than or equal to the first threshold, select a preset threshold sequence corresponding to the check equation weight being less than or equal to the first threshold as the initial threshold sequence.

4. The decoder of claim 2, wherein, The N is greater than 1; and the processor is specifically configured to: In the first iteration, compare the check equation weight with a plurality of the first thresholds to determine a threshold interval in which the check equation weight is located; Select one of the preset threshold sequences corresponding to the threshold interval in which the check weight is located as the initial threshold sequence.

5. The decoder of claim 2, wherein, The processor is further configured to: In the M+Xth iteration, obtain a cyclic threshold sequence, and assign one flipping threshold in the cyclic threshold sequence to the bit flipping circuit; The X is a positive integer.

6. The decoder of claim 5, wherein, The processor is further configured to: In the M+1th iteration, obtain P+1 preset cyclic sequences, compare the check equation weight in the first iteration or the check equation weight in the M+1th iteration with P second thresholds, and select one of the P+1 preset cyclic sequences as the cyclic threshold sequence according to the comparison result; the P is a positive integer.

7. The decoder of claim 1, wherein, The second processing circuit is specifically configured to: performing a first calculation on the check equation and the check matrix to obtain a number of errors corresponding to each bit in a to-be-decoded codeword in the current iteration; obtaining a marking value corresponding to each bit in the to-be-decoded codeword in the current iteration according to a flipping state of the bit; performing a second calculation on the number of errors corresponding to each bit in the to-be-decoded codeword in the current iteration and the marking value to obtain an energy of the to-be-decoded codeword.

8. The decoder of claim 7, wherein, The bit flipping circuit is specifically configured to: compare the energy of each bit in the to-be-decoded codeword in the current iteration with the flipping threshold value; flip the bit according to the energy of the bit being greater than the flipping threshold value, or keep the bit unchanged according to the energy of the bit being less than or equal to the flipping threshold value, to obtain a decoded codeword in the current iteration; output the decoded codeword in the current iteration as the to-be-decoded codeword in the next iteration.

9. The decoder of claim 1, wherein, The first processing circuit is specifically configured to: perform a third calculation on the to-be-decoded codeword in the current iteration and the check matrix to obtain the check equation; calculate a number of bits being 1 in the check equation to obtain a check equation weight.

10. The decoder of claim 1, wherein, The decoder further includes: an output circuit configured to output the to-be-decoded codeword in the current iteration as a final decoded codeword according to each bit in the check equation in the current iteration being 0.

11. A decoding method, comprising: including: obtaining a check equation and a check equation weight based on a to-be-decoded codeword in a current iteration and a check matrix; obtaining an energy of the to-be-decoded codeword in the current iteration based on the check equation, the check matrix, and a flipping state of the to-be-decoded codeword in the current iteration; in an initial iteration, selecting one of a plurality of preset threshold value sequences as an initial threshold value sequence based on the check equation weight; outputting a to-be-decoded codeword in a next iteration based on a comparison result of the energy of the to-be-decoded codeword in the current iteration and one of the flipping threshold values in the initial threshold value sequence.

12. The decoding method of claim 11, wherein, The in the initial iteration, selecting one of a plurality of preset threshold value sequences as an initial threshold value sequence based on the check equation weight, and the outputting a to-be-decoded codeword in a next iteration based on a comparison result of the energy of the to-be-decoded codeword in the current iteration and one of the flipping threshold values in the initial threshold value sequence, include: in the initial iteration, obtaining N+1 preset threshold value sequences, comparing the check equation weight with N first threshold values, and selecting one of the N+1 preset threshold value sequences as the initial threshold value sequence according to a comparison result; the initial threshold value sequence includes M flipping threshold values; the N is a positive integer; the M is an integer greater than 1; in an Lth iteration, outputting a to-be-decoded codeword in a next iteration based on a comparison result of the energy of the to-be-decoded codeword in the current iteration and an Lth flipping threshold value in the initial threshold value sequence; the L is a positive integer less than or equal to the M.

13. The decoding method of claim 12, wherein, The N is 1; the check weight is compared with N first thresholds in the initial iteration, and one preset threshold sequence corresponding to the threshold interval of the check weight is selected as the initial threshold sequence according to the comparison result. The check weight is compared with one first threshold in the initial iteration. According to the check weight being greater than the first threshold, a preset threshold sequence corresponding to the check weight being greater than the first threshold is selected as the initial threshold sequence, or according to the check weight being less than or equal to the first threshold, a preset threshold sequence corresponding to the check weight being less than or equal to the first threshold is selected as the initial threshold sequence.

14. The decoding method of claim 12, wherein, The N is greater than 1; the check weight is compared with N first thresholds in the initial iteration, and one preset threshold sequence corresponding to the threshold interval of the check weight is selected as the initial threshold sequence according to the comparison result. The check weight is compared with multiple first thresholds in the initial iteration to determine the threshold interval of the check weight. One preset threshold sequence corresponding to the threshold interval of the check weight is selected as the initial threshold sequence.

15. The decoding method of claim 12, wherein, The decoding method further comprises: In the M+Xth iteration, a cyclic threshold sequence is obtained, and a code word to be decoded in the next iteration is output based on the comparison result of the energy of the code word to be decoded in the current iteration and one flip threshold in the cyclic threshold sequence; the X is a positive integer.

16. The decoding method of claim 15, wherein, The decoding method further comprises: In the M+1th iteration, P+1 preset cyclic sequences are obtained, the check weight in the initial iteration or the check weight in the M+1th iteration is compared with P second thresholds, and one preset cyclic sequence is selected as the cyclic threshold sequence from the P+1 preset cyclic sequences according to the comparison result; the P is a positive integer.

17. The decoding method of claim 11, wherein, The energy of the code word to be decoded in the current iteration is obtained based on the check equation, the check matrix and the flip state of the code word to be decoded in the current iteration, comprising: A first calculation is performed on the check equation and the check matrix to obtain the error number corresponding to each bit in the code word to be decoded in the current iteration; According to the flip state of each bit in the code word to be decoded in the current iteration, a mark value corresponding to each bit is obtained; A second calculation is performed on the error number corresponding to each bit in the code word to be decoded in the current iteration and the mark value to obtain the energy of the code word to be decoded.

18. The decoding method of claim 17, wherein, The code word to be decoded in the next iteration is output based on the comparison result of the energy of the code word to be decoded in the current iteration and one flip threshold in the initial threshold sequence, comprising: The energy of each bit in the code word to be decoded in the current iteration is compared with the flip threshold; flip the bit according to that the energy of the bit is greater than the flip threshold, or keep the bit unchanged according to that the energy of the bit is less than or equal to the flip threshold, to obtain a decoded codeword in the current iteration; output the decoded codeword in the current iteration as a to-be-decoded codeword in the next iteration.

19. The decoding method of claim 11, wherein, the obtaining of the check equation and the check equation weight based on the to-be-decoded codeword in the current iteration and the check matrix comprises: performing third calculation on the to-be-decoded codeword in the current iteration and the check matrix to obtain the check equation; calculating the number of bits being 1 in the check equation to obtain the check equation weight.

20. The decoding method of claim 11, wherein, the decoding method further comprises: outputting the to-be-decoded codeword in the current iteration as a final decoded codeword according to that each bit of the check equation in the current iteration is 0.

21. A memory system, comprising: comprise: a memory configured to output read data; the decoder of any one of claims 1 to 10, configured to decode a to-be-decoded codeword in the read data.

22. The memory system of claim 21, wherein, the memory system further comprises: an encoder configured to receive write data and encode the write data; the memory is further configured to receive the encoded write data.

23. The memory system of claim 22, wherein, the memory system comprises a controller coupled to the memory, and the controller comprises the decoder and the encoder.

24. A controller characterized by comprise: an interface configured to receive read data; the decoder of any one of claims 1 to 10, configured to decode a to-be-decoded codeword in the read data.

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