Data internal storage managing system and method, and related multiprocessor network

Abstract

The present invention relates to a system and a method of memory management of data consistency relating to a main memory (4) accessible by at least two processors (1,2), as well as an associated multiprocessor network. The management system comprises an assembly for management of shared access of the processors to a common area (9) of the main memory, referred to as the exchanges area, at least one copy module (12,13) intended for performing a data copy between at least one first processor comprising at least one cache memory and the exchanges area and at least one transfer module (12,13) intended for performing a transfer of data between the exchanges area and at least one second processor. Triggering means controlled by the second processors trigger the copy modules and transfer modules when the first processors submit requests involving transfers of data between the first and second processors.

Description

Technical field

[0001] The invention relates to a data consistency memory management system and method and a corresponding multi-processor network. Background technique

[0002] In order to achieve efficient operation, fast processors with a clock frequency higher than 100 MHz usually use cache memory, which is also referred to as cache for short. This type of cache copies certain data present in the main memory (such as synchronous access memory or SDRAM) to a memory that has a much faster access time than the memory. In traditional systems, the size of the cache is limited due to cost and size, so only a small part of the memory content can be stored in the cache at a given time. In the improved system, several levels of caches are connected in series, and the time for accessing data items and their storage capacity are specified for each level. Generally, the first-level cache allows data to be accessed at the processing speed of the processor.

[0003] Difficulties arise in t...

Examples

Embodiment Construction

[0075] in Figure 2 to Figure 6 , The size and distribution of the memory and memory space or storage area required to be able to clearly illustrate the example, and does not indicate the actual size and distribution used. By convention, the solid arrow indicates the data transfer in the read mode (the arrow from the memory to the processor) or the write-read mode (the arrow from the processor to the memory); the dashed arrow ( figure 2 Shown) means pointing to the data in the memory; and the thin dotted arrow ( image 3 (Shown) illustrates the memory space allocation.

[0076] figure 1 The digital decoder 3 shown includes a processor 1 and a processor 2. Set up software 10 and software 11 for processor 1 and processor 2, respectively. Software 10 and software 11 respectively include part 12 and part 13 related to data communication. Part 12 and part 13 allow the connection between processor 1 and processor 2. Exchange information. In addition, a cache 5 and a cache 6 managed b...

Technical field

[0001] The invention relates to a data consistency memory management system and method and a corresponding multi-processor network. Background technique

[0002] In order to achieve efficient operation, fast processors with a clock frequency higher than 100 MHz usually use cache memory, which is also referred to as cache for short. This type of cache copies certain data present in the main memory (such as synchronous access memory or SDRAM) to a memory that has a much faster access time than the memory. In traditional systems, the size of the cache is limited due to cost and size, so only a small part of the memory content can be stored in the cache at a given time. In the improved system, several levels of caches are connected in series, and the time for accessing data items and their storage capacity are specified for each level. Generally, the first-level cache allows data to be accessed at the processing speed of the processor.

[0003] Difficulties arise in t...

Examples

Embodiment Construction

[0075] in Figure 2 to Figure 6 , The size and distribution of the memory and memory space or storage area required to be able to clearly illustrate the example, and does not indicate the actual size and distribution used. By convention, the solid arrow indicates the data transfer in the read mode (the arrow from the memory to the processor) or the write-read mode (the arrow from the processor to the memory); the dashed arrow ( figure 2 Shown) means pointing to the data in the memory; and the thin dotted arrow ( image 3 (Shown) illustrates the memory space allocation.

[0076] figure 1 The digital decoder 3 shown includes a processor 1 and a processor 2. Set up software 10 and software 11 for processor 1 and processor 2, respectively. Software 10 and software 11 respectively include part 12 and part 13 related to data communication. Part 12 and part 13 allow the connection between processor 1 and processor 2. Exchange information. In addition, a cache 5 and a cache 6 managed b...

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