847 results about "High performance computation" patented technology

The invention provides a computing system and method for GPU computing power scheduling, and the method comprises the following steps: 1, obtaining computing task data, and carrying out the information collection of each task through receiving a to-be-processed computing task queue; according to the invention, through task information collection and deep analysis, and GPU resource omnibearing monitoring and workload prediction, deep understanding of tasks and GPU resources is realized, highly accurate computing power distribution can be carried out, resource waste is avoided, and the resource utilization rate is improved; advanced technologies such as a knowledge graph, mixed integer programming and deep reinforcement learning are fused through the intelligent scheduling model, the fusion mode is innovative in the GPU computing power scheduling field, the limitation of singleness of a traditional scheduling model is overcome, the method can better adapt to a complex and changeable computing environment, the task execution efficiency is optimized, and the task scheduling efficiency is improved. The adaptability and competitiveness of the whole system in a complex environment are remarkably improved, and an excellent solution is provided for the GPU computing power scheduling problem in the field of high-performance computing.

The invention discloses a control method for heat dissipation of a high-performance computing cluster platform, which comprises the following steps of: firstly, establishing a three-dimensional temperature distribution model of a high-performance computing cluster, acquiring data such as temperature and power consumption of each node in real time, obtaining deviation data of each node by utilizing a prediction model, and dynamically evaluating a heat dissipation risk level of each node; dividing the whole cluster into different risk areas; computing tasks are intelligently distributed based on risk levels, and high-load tasks are preferentially scheduled to a low-temperature area; and then, starting graded cooling measures for the high-risk area, continuously monitoring the cooling effect, and feeding back the result to an early warning system and a hardware maintenance module to form'prediction-regulation-feedback 'closed-loop control. The heat dissipation efficiency of the high-performance computing cluster platform is remarkably improved, the overheat fault risk is reduced while the computing performance is guaranteed, the service life of key hardware is prolonged through dynamic optimization, and intelligent cooperation of heat dissipation resources and computing tasks is achieved.

The invention belongs to the field of high-performance computing, and relates to an integer parallel computing method and device based on distributed storage and computer equipment, and the method comprises the steps of collecting real-time resource indexes, dynamically identifying fault nodes, triggering task migration, and performing data verification and hard disk fault detection. The weight value of each node is calculated, the nodes are arranged according to the descending order of the weight values, and the nodes with high load capacity are selected to distribute tasks; dynamically distributing a data generation task to a computing node, executing parallel computing, and performing distributed storage on a result; obtaining an operand, converting the operand into a first-order tensor form of a basic operand, serializing tensor data, and sending the serialized tensor data to a parallel computing layer; distributing a search task to a computing node, retrieving storage data in parallel, reading effective data from a storage layer, and combining search results into a partial sum; and summarizing and then outputting. The system has dynamic resource management and fault-tolerant capabilities, and can realize efficient task allocation and load balancing.

The invention relates to the technical field of computer architecture and parallel computing, and discloses a parallel task scheduling algorithm for a heterogeneous multi-core processor, which comprises the steps of task modeling, resource mapping, dynamic load balancing, communication optimization, task scheduling decision and execution monitoring. Task allocation is adjusted in real time through dynamic load balancing, cross-core communication delay is reduced in combination with communication optimization, and an efficient task allocation sequence is generated by using an improved genetic algorithm. According to the method, the resource utilization rate and the task execution efficiency of the heterogeneous multi-core processor in a high-performance computing scene can be improved, meanwhile, the robustness and adaptability of an algorithm are enhanced, and the task allocation problem in a complex computing scene is effectively solved.

The invention discloses a low-code platform and Wasm high-performance computing integration system and method, and relates to the technical field of front-end development. In order to solve the problems that an existing low-code platform is limited in calculation performance and poor in security isolation performance, the scheme adopted by the invention comprises five modules: a description and registration module establishes a metadata structure for a Wasm module; the dynamic loading and asynchronous compiling module realizes loading as required and compiling during operation, and supports caching, version verification and hot replacement; the authority sandbox and resource isolation module constructs a security environment based on authority configuration to prevent illegal operation; the parameter binding and safety bridging module encapsulates a uniform interface to realize standardized interaction; the packaging and life cycle management module packages the module into a visual component, and supports full life cycle management. According to the method, high-performance, high-safety and visual integration of the Wasm module in a low-code platform is realized.

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a neural network large model efficient reasoning method based on multiple GPGPUs. The method aims to solve the problems of high communication overhead, non-uniform load, low resource utilization rate, high data transmission delay and the like among multiple processors. Dividing a calculation task into a plurality of sub-graphs through static analysis and mixed granularity partitioning of a model calculation graph; distributing the sub-graphs to the optimal GPGPU based on a weighted cost function in combination with heterogeneous resource perception and a dynamic mapping strategy; a global pipeline scheduling plan is constructed by using communication topology perception, and calculation and communication overlap are maximized; data are loaded in advance through a host side hierarchical caching and asynchronous prefetching mechanism, and transmission delay is hidden; multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU, so that waiting overhead is reduced. According to the method, the reasoning delay can be remarkably reduced, the throughput and the hardware utilization rate are improved, and the method has good adaptivity and expandability.

The invention discloses a high-low voltage linkage line loss comprehensive intelligent diagnosis system and method. The system comprises a distributed storage and high-performance calculation module, a data fusion and processing module, a multi-dimensional feature construction module, a high-low voltage linkage analysis module and a line loss intelligent diagnosis module. The method is used for carrying out line loss comprehensive intelligent diagnosis based on the system, and comprises the following steps: processing multi-source data in real time through the distributed storage and high-performance calculation module; bus-line-user archive data are fused, and a line loss index is calculated; extracting time, space and electrical three-dimensional characteristic indexes; performing high-low voltage linkage analysis based on the Pearson's correlation coefficient and the DTW distance; and fusing the system state model and the isolated forest anomaly detection model to output an anomaly diagnosis result. The method is suitable for accurate analysis and treatment of line loss in an intelligent power grid environment, and the efficiency and quality of line loss management can be improved.

The invention discloses a quantum computer and super computer connection fusion method, which comprises the following steps of: constructing a quantum computer architecture and a super computer architecture, and realizing connection between the quantum computer architecture and the super computer architecture through a hardware layer; inputting the calculation data into a super computer, and performing task classification on the calculation data by utilizing an innovation fusion module to obtain a plurality of calculation tasks; utilizing an AI model to predict execution time and resource consumption of the plurality of calculation tasks on the quantum computer and the super computer respectively, and adjusting the distribution proportion of the plurality of calculation tasks on the quantum computer and the super computer; and transmitting the calculation data to the super computer and the quantum computer for classical calculation and quantum calculation according to the distribution proportion, and transmitting a calculation result back to a central node of the super computer to complete a calculation task. The invention relates to the field of quantum computing and high-performance computing, and solves the technical problem that the computing efficiency is low when a quantum computer and a super computer are used for computing in the prior art.

The invention provides a chip system and an access method, relates to the technical field of chips, and improves the data access performance of a high-performance computing system. According to the specific scheme, the chip system comprises a snoop filter, a plurality of processor cluster nodes and a plurality of memories, the processor cluster nodes are coupled through a bus, the snoop filter is coupled with the bus, the processor cluster nodes are in one-to-one correspondence with the memories, and the snoop filter adopts a unified directory format. The snoop filter is used for obtaining an access request initiated by the processor cluster node, and the access request comprises address information. The snoop filter is further used for determining an access mode of the access request based on the address information, wherein the access mode comprises a unified memory access mode and a non-unified memory access mode. The processor cluster node is to access the memory based on the access pattern and the access request. The embodiment of the invention is used for the process of accessing the memory by the processor cluster node.

The invention relates to the field of artificial intelligence, in particular to a deployment method and system for a large language model, and the method comprises the steps: (1) a service request end receives at least one piece of service request information, and stores the service request information in a service request message queue; (2) responding to a pre-filling stage calculation unit request and a load condition, and distributing service request information; (3) finishing the processing of the pre-filling stage to obtain at least one operation result; (4) the load balancer determines a task operation calculation unit in the stage according to the load condition of the calculation unit in the decoding stage; and (5) inputting the operation result of the pre-filling stage into the task operation calculation unit of the decoding stage, and outputting the result. The method has the advantages that the pre-filling stage and the decoding stage are deployed on a machine with high-performance computing power and a large memory respectively, load tasks are balanced, maximum hardware utilization is achieved, idle computing power is reduced, overall delay is reduced, throughput is improved, and expansibility and fault tolerance of the system are enhanced.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

The invention relates to the technical field of automobile material temperature simulation analysis, in particular to an automobile cabin temperature field simulation analysis method and system based on multi-physics field coupling. According to the method, high-precision and high-efficiency simulation is realized through thermal-solid-fluid-electric coupling modeling in combination with the genetic algorithm, the neural network and reinforcement learning AI dynamic optimization, and the problems that the multi-physical field coupling effect cannot be comprehensively reflected and the parameter optimization efficiency is low in the prior art are solved. Time sequence analysis and dynamic boundary condition adjustment are introduced, transient working condition simulation is supported, and temperature field changes in actual driving can be better predicted. Through simultaneous solution of the Maxwell equation and the heat conduction equation, the temperature rise risk of the electronic component is accurately predicted, and the method is suitable for heat management optimization of key components such as a battery pack and a motor controller of a new energy automobile. Cloud high-performance calculation and edge end lightweight model cooperation are adopted, efficient simulation and real-time early warning are achieved, and rapid analysis and design optimization of extreme working conditions are supported.

The present disclosure herein addresses the problem of synthesizing a series of documents and extracting or summarizing meaningful information or content embedded as tacit knowledge in the series of documents. The embodiment of the present disclosure provides a system and method for tacit knowledge generation using large language model (LLM) in document synthesis. The method of the present disclosure performs intelligent document generation orchestrating a generative artificial intelligence solution workflow. In the present disclosure, tacit knowledge of subject matter experts in a knowledge base or in a series of documents is extracted. Further a content capturing the tacit knowledge is generated leveraging a large language models (LLMs) framework as the underlying architecture. The system of the present disclosure is artificial intelligence (AI) accelerated, cloud agnostic, latency defined, and security enabled.

According to the house leasing information management system and method provided by the invention, comprehensive, efficient and safe management of house leasing information is realized in combination with a special hardware system and terminal equipment. The system integrates a plurality of cooperative work modules such as block chain data storage, intelligent housing resource recommendation, dynamic credit evaluation, automatic contract management and privacy protection, and adopts advanced technologies such as a distributed account book, a deep neural network, a graph neural network and an intelligent contract. And data cannot be tampered, recommendation is personalized, credit evaluation is accurate, contract management is automatic, and user privacy is strictly protected. Meanwhile, the system is provided with hardware supports such as a high-performance computing and storage cluster, security encryption and privacy protection equipment and the like, and special terminal equipment provides convenient user interaction experience. According to the invention, transparency, efficiency and user experience of the house renting market can be significantly improved, renting risks are reduced, rights and interests of both renting parties are guaranteed, and healthy development of the house renting industry is promoted.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention relates to the technical field of forest fire management, in particular to an integrated forest fire intelligent analysis method and system. The system comprises a background service system, a central intelligent analysis system and a mobile intelligent analysis system. The background service system is deployed in a cloud computing server cluster and is used for uniformly storing personnel information, fire scene information and geographic information data and realizing multi-source data fusion and authority management through a standardized API (Application Program Interface); the central intelligent analysis system is deployed in a high-performance computer, integrates a forest fire danger auxiliary decision-making model, a forest fire spreading trend prediction model, a force distribution dynamic display module and a collaborative plotting module, and supports fire spreading prediction and real-time decision-making instruction issuing based on multi-dimensional data such as weather, terrain and vegetation; the mobile intelligent analysis system realizes fire spreading trend analysis, mobile plotting and instruction receiving in an offline environment, supports offline data caching and calling in an emergency scene, and effectively improves forest fire emergency response efficiency and resource scheduling accuracy.

The invention provides a Cholesky decomposition heterogeneous parallel optimization method and system based on an SW architecture, and relates to the technical field of high-performance computing. The method comprises the following steps: performing sub-block division on a symmetric positive definite matrix based on a distributed parallel distribution scheme, and performing iteration to complete matrix decomposition; each sub-block is distributed to different processes through an MPI programming model, data exchange is carried out between the processes through asynchronous communication, and coarse-grained task-level parallel acceleration is carried out; performing two-stage parallel acceleration on four operations in Cholesky decomposition by utilizing the acceleration parallel characteristic of a master core and a slave core of the SW architecture; wherein for GEMM and SYRK operations, column vectors of a matrix are mapped to a slave core array, and columns are divided according to the number of slave cores; the calculation process is optimized through a double-buffering mechanism, vectorization operation and a loop expansion technology, and the parallel efficiency is improved; and for the TRSM operation, the TRSM operation is decomposed into a plurality of TRSV operations, the TRSV operations are allocated to the slave cores for parallel execution, and a circular reading and data broadcasting mode is adopted to reduce data dependence and realize efficient parallel calculation.

Embodiments for communicating using a switch configured to establish multiple types of communication routes. First and second upstream switch ports (USPs) communicate with first and second hosts according to first and second Compute Express Link (CXL) protocols, respectively. A downstream switch port (DSP) communicates with a device according to a third CXL protocol. The switch couples the first USP to the DSP via a first route traversing a single Virtual CXL Switch (VCS), and couples the first USP to the second USP via a second route traversing two VCSs. Optionally, the switch includes a Resource Provisioning Unit (RPU) coupling the two VCSs of the second route, terminating the first and second CXL protocols, and translating between CXL messages conforming to the first and second CXL protocols.

The satellite-borne heterogeneous computing system comprises a CPU (central processing unit) module, an FPGA (field programmable gate array) module and an NPU (network processing unit) module, the CPU module is used for receiving instructions and telemetering polling of a satellite service computer, reading load scientific data received by the FPGA module, providing installation and operation environments for various types of universal application programs, and scheduling and controlling the NPU module; the FPGA module is used for providing external interface expansion, receiving load scientific data and sending the load scientific data to the CPU module, and is also used for providing a logic control function comprising SPI FLASH triple modular redundancy logic and barking reset; and the NPU module is used for performing high-performance calculation and providing a high-computing-power environment for the system. The system has high flexibility, reliability and universality, and can operate various computing software and neural network algorithms; the power consumption is low, and strict requirements of a satellite platform on power consumption can be met. And a plurality of systems are interconnected to form a distributed computing system, so that the performance is extremely high.

The invention relates to the technical field of high-performance computing resource management, and discloses a computing resource allocation method for a distributed supercomputing center. The method comprises the following steps: on the basis of obtaining real-time computing task and supercomputing center resource data and uniformly quantifying, integrally predicting resource requirements of future tasks; constructing a mixed integer linear programming model with the minimization of the total operation cost as a single target, wherein the total operation cost is the sum of the energy cost, the carbon emission cost, the data transmission cost and the SLA default penalty cost; solving the model by taking the time-varying electricity price, the green energy ratio, the resource capacity and the network parameters of each center as constraint conditions to generate an optimal resource allocation scheme; and then, by dynamically monitoring the resource state and the task progress, the model is triggered to resolve when the resource utilization rate is detected to be unbalanced or default risks, so that self-adaptive adjustment is realized. According to the invention, global collaborative resource allocation across super computing centers is realized, and operation economy, environmental sustainability and service reliability are considered.

The invention provides a multi-level performance analysis and optimization method based on an RISC-V framework, and aims to position and optimize performance bottlenecks in application programs through efficient performance data acquisition and analysis means. The method comprises the following steps: firstly, sampling and monitoring all application programs by utilizing an eBPF, capturing applications or processes with abnormal performance, then deeply analyzing the abnormal applications by utilizing a perf tool, and obtaining performance indexes such as function call, instruction number, CPU period and the like. A hot function generated by perf is analyzed, a specific performance counter of an RISC-V architecture is further used, data of the performance counter is read from a user mode, the performance data in the function execution process are accurately monitored in combination with the uprobe technology, and the performance bottleneck is deeply analyzed and positioned. Finally, the performance problem is solved by means of code optimization, system architecture adjustment and the like, and the performance is continuously optimized in multiple iterations. According to the scheme, global performance monitoring can be converted into accurate function level analysis, dependence on a kernel module is reduced, the flexibility and accuracy of performance analysis are improved, and the method has wide application value and is particularly suitable for performance adjustment and optimization in the fields of high-performance calculation, embedded systems, cloud services and the like.

The invention relates to the technical field of battery testing, and provides a flow battery bipolar plate flow channel diversion performance testing device, which comprises an intelligent testing galvanic pile, which is composed of a plurality of detachable flow channel units, each flow channel unit comprises a bipolar plate and two flow channel frames, the flow channel frames adopt a modular design, and the flow channel units are connected with the intelligent testing galvanic pile; a plurality of micro pressure sensors, temperature sensors and flow sensors are embedded in the shell; the intelligent liquid path system comprises a plurality of independent liquid path circulating units, and each unit is composed of a liquid tank, an intelligent liquid pump, a liquid supply pipeline and a liquid return pipeline; a plurality of independent test chambers are arranged in the multifunctional shell, and a temperature and humidity control system and an intelligent drainage system are arranged in the shell; and the data acquisition and analysis system consists of a high-performance computer, a data acquisition card, a signal amplifier and analysis software. The problems that in the prior art, the local flow characteristic of the electrolyte on the surface of the carbon felt is difficult to accurately evaluate, and the requirement of optimizing flow channel design on refined data cannot be met are solved.

The invention discloses a high-performance computing memory optimization method and system based on cache classification, and the method comprises the following steps: S1, dividing a physical memory page into different categories according to the number of cache groups mapped to a target cache, and distributing the divided categories to a target process running in the target cache; and S2, when the target process requests the physical memory page from the operating system, allocating the physical memory page of the same category to the target process based on the category corresponding relationship between the process and the physical memory page. According to the method, the problem of cache conflict among a plurality of processes under the condition of high CPU utilization rate is solved, so that the performance of the whole system is improved.

The invention relates to a calculation task execution method and device, equipment and a storage medium. According to the main technical scheme, the method comprises the steps of obtaining to-be-processed computing tasks, a preset mapping table and computing resource available information of computing nodes, performing topological sorting on the to-be-processed computing tasks according to a dependency relationship among the to-be-processed computing tasks to obtain a priority execution sequence of the to-be-processed computing tasks, and based on the priority execution sequence, a preset mapping table and the computing resource available information, determining a real-time execution sequence of the to-be-processed computing tasks, and executing the to-be-processed computing tasks through the first group of computing chips or the second group of computing chips according to the real-time execution sequence of the to-be-processed computing tasks. According to the method, high-complexity heterogeneous computing of computing chips of different types and different sources can be realized, high-performance computing and intelligent computing service scenes are supported, and compatibility of a high-performance computing related service system and a hyper-converged computing cluster is facilitated.

The invention relates to the technical field of interface impedance adjustment, and discloses an impedance matching adjustment method and device for an FPC high-performance computing chip interface. The method comprises: collecting impedance parameters of the FPC high-performance computing chip interface and establishing an impedance characteristic mathematical model; constructing a scalar differential equation group including an impedance change rate, a temperature change rate and a signal characteristic change rate, and solving the scalar differential equation group to obtain a dynamic compensation parameter matrix; adjusting and controlling the interlayer relative positions of an FPC multilayer structure, adjusting impedance gradient parameters in an interlayer transition region of the FPC multilayer structure, and obtaining initial impedance optimization data; inputting the initial impedance optimization data and historical temperature data into a recurrent neural network model to perform impedance matching parameter optimization calculation, and generating an impedance matching optimization parameter group. The invention improves the adaptability of the FPC high-performance computing chip interface to complex working conditions and improves the convergence speed of the impedance matching parameters.

The invention discloses a verification method for a second-level cache interface protocol, which belongs to the technical field of multi-core verification, and comprises the following steps of: setting verification targets, including function correctness, performance standard, compatibility and exception handling capacity; establishing a verification environment, wherein the verification environment comprises a hardware platform and a test tool; function verification, including read-write operation verification, cache line state transition verification and consistency verification; performance verification including delay testing and bandwidth testing; the compatibility verification comprises the compatibility with a first-level cache and the compatibility with a processor core; the abnormal condition verification comprises interrupt processing verification and error injection verification; and analyzing a test result. According to the verification method for the second-level cache interface protocol, the second-level cache interface protocol can be comprehensively and deeply verified, the function correctness, the performance standard reaching performance and the compatibility with other components of the second-level cache interface protocol are ensured, and a solid guarantee is provided for stable operation of a high-performance computer system.

The invention provides an automatic SEM image analysis and process defect detection system based on a full database, and relates to the technical field of semiconductor manufacturing, the system combines self-adaptive feature extraction and density anomaly detection of a high-performance calculation unit through dynamic feature fusion (Sp1) of a multi-scale SEM image and a multi-channel acquisition device, and realizes automatic analysis of the SEM image. Precise classification of defect types and automatic identification of new defects are achieved, the feature range and the fusion weight are dynamically adjusted, traditional static detection limitation is broken through, adaptive analysis of process context is supported, the detection precision is improved to 98%, the misjudgment and missing judgment rate is reduced by 30%-50%, especially in advanced processes such as 3nm, the new defects can be rapidly identified, rules can be updated, and the method is suitable for large-scale popularization and application. The process research and development efficiency and the product reliability are remarkably improved, and the flexible and intelligent detection capability is provided for semiconductor manufacturing.