198 results about "Opcode" patented technology

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

The invention discloses a self-adaptive threat blocking method and system oriented to industrial control protocol deep analysis, and the method comprises the steps: constructing an industrial control protocol multi-dimensional analysis model, extracting an operation code semantic rule, a parameter structure constraint and session state hopping features based on protocol reverse engineering, generating a protocol syntax tree, and blocking a threat from the protocol syntax tree. Wherein the operation code semantic rule is matched with the service primitive mapping of an abstract communication service interface in the IEC 61850 standard; based on the protocol syntax tree, semantic-level analysis is carried out on real-time communication flow, dynamic indexes are extracted, the dynamic indexes comprise a process value mutation gradient, an instruction sequence logic conflict degree and a session state abnormal jump rate scale, and a three-dimensional threat feature vector is generated. According to the method, hidden attacks are accurately recognized through industrial control protocol semantic analysis and multi-dimensional dynamic blocking, so that the defense action and the production stability can be collaboratively optimized.

The invention discloses a protocol conversion method and device, a medium and a server system, and relates to the technical field of servers. Once an original protocol type is determined, a dynamic interface routing controller calls a corresponding conversion program stored in a mapping table; and converting the detected heterogeneous bus protocol command into a unified single-line serial bus protocol operation code. As the conversion program and the protocol characteristics are stored in the mapping table, the method has infinite protocol expansion capability, a new protocol can be supported by updating the mapping table and a detection engine without redesigning hardware or modifying codes of an editable logic device, the system design is greatly simplified, and the development cost is reduced. Therefore, the problem that the current programmable logic device can only realize single interface protocol conversion is solved.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The invention discloses a contract vulnerability detection method and system based on cross-granularity feature fusion and meta-learning, and relates to the technical field of block chain security, the method comprises the following steps: obtaining a source code and a compiled byte code of a contract to be detected; source code semantic features are extracted from the source code, operation code execution features are extracted from the byte code, and graph structure features are extracted after a program dependency graph is constructed from the source code; performing cross-granularity attention interaction to generate cross-granularity fusion features; performing type-aware feature modulation on the cross-granularity fusion feature and a vulnerability type identifier of the current detection task, training a classifier by adopting a meta-learning strategy, and outputting a vulnerability detection result; and in response to the vulnerability detection result that the vulnerability exists, positioning the vulnerability code position based on the graph-source code attention weight matrix generated in the cross-granularity attention interaction process, thereby solving the problem of poor generalization ability in a rare vulnerability scene with scarce samples.

The embodiment of the invention discloses a data processing system and a data processing method based on RISC-V. The data processing system comprises an instruction coding space and a reconfigurable execution unit, the instruction coding space comprises an operation code area, a reserved area and an expansion area; the instruction coding space is used for defining a basic operation to be executed by an instruction in the operation code area, defining an extended operation to be executed by the instruction in the reserved area and defining the length of the instruction in the extended area so as to configure different types of instructions; the reconfigurable execution unit is used for constructing a data path matrix of the instruction based on the configuration information of the instruction; transmitting data required when the instruction is executed based on the data path matrix; and executing an operation corresponding to the instruction based on the data of the instruction.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

CAN bus signal format inference includes: extracting candidate signals from training CAN bus message traffic; defining one or more signals, each signal being a candidate signal that matches structural characteristics of a matching data type and each signal being assigned the matching data type; and generating an inferred CAN bus protocol with which the defined one or more signals conform. Signals are extracted from CAN bus message traffic using the inferred CAN bus protocol, an anomaly in an extracted signal is detected, and an alert is generated indicating the detected anomaly. In another aspect, a transport protocol (TP) signal is extracted and analyzed to determine a fraction of the TP signal that matches opcodes of a machine language instruction set, and an anomaly is detected based at least in part on the determined fraction exceeding an opcode anomaly threshold.

The invention is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and a program product, and the method comprises the steps: obtaining instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on the original effective vector; each index value in the index vector is subjected to one-hot code conversion, a one-hot code matrix corresponding to the instruction set to be processed is generated, and each row of one-hot code vector in the one-hot code matrix corresponds to each path of input instruction; and according to the original effective vector and the one-hot code matrix, sorting operation codes of each path of input instruction to obtain processed operation code information, so that a processor executes corresponding operation based on the processed operation code information. The method can meet the requirement that the high-performance processor completes instruction processing in a single cycle, the processing delay is low, and therefore the instruction execution efficiency of the processor is improved.

The invention relates to the field of code vulnerability detection, in particular to a vulnerability detection method and system based on code block features. The method comprises the steps that firstly, a binary file is analyzed, and a machine instruction is analyzed through a hybrid disassembling engine; secondly, performing static linear scanning on the extracted binary file instruction, constructing a control flow graph, dividing basic blocks, extracting an operation code sequence in the basic blocks, and constructing a cross-basic-block data dependency graph and a system calling sequence called by the basic blocks; secondly, using an LSH algorithm to realize rapid filtering, performing similarity comparison on extracted basic block features and vulnerability feature library features, realizing coarse-grained matching, and screening out a matching candidate set; feature fusion is carried out on the candidate set basic block operation code sequence, the basic block data dependency graph and the system calling sequence called by the basic block, GNN fine-grained matching is carried out on the fused features, and vulnerability detection is carried out. The problems that traditional binary vulnerability detection is poor in adaptability and low in result reliability are solved.

The invention discloses an operating system containerized kernel compatibility method based on mixed binary translation, which comprises the following steps of: constructing a container kernel data structure feature library containing field access frequency through static source code analysis and dynamic runtime tracking, generating a unique identifier consisting of a structure name and a high-frequency field offset sequence for a target structure, and generating a container kernel data structure feature library containing field access frequency; establishing an association graph between the system call and the target field; in a host machine, a static translation service is adopted to decompile a binary code of a container application, instrumentation is performed on a high-frequency site and a low-frequency site respectively, and an intermediate operation code sequence containing an operation code, a field name and double-end offset is pre-generated for the high-frequency site and stored in a cache; during operation, a pre-translation result is preferentially loaded from the cache for a high-frequency site, the pre-translation result is processed by the dynamic translation engine if the pre-translation result is not hit, and the pre-translation result is processed by the dynamic translation engine as required for a low-frequency site, so that efficient conversion combining field-level static preprocessing and on-demand dynamic conversion is realized.

CAN bus signal format inference includes: extracting candidate signals from training CAN bus message traffic; defining one or more signals, each signal being a candidate signal that matches structural characteristics of a matching data type and each signal being assigned the matching data type; and generating an inferred CAN bus protocol with which the defined one or more signals conform. Signals are extracted from CAN bus message traffic using the inferred CAN bus protocol, an anomaly in an extracted signal is detected, and an alert is generated indicating the detected anomaly. In another aspect, a transport protocol (TP) signal is extracted and analyzed to determine a fraction of the TP signal that matches opcodes of a machine language instruction set, and an anomaly is detected based at least in part on the determined fraction exceeding an opcode anomaly threshold.

The invention discloses a data processing method, a solid state disk, a system and a storage medium, and relates to the technical field of solid state disk storage, and the data processing method comprises the steps that it is detected that an NVMe PCIe link configures an instruction register, and an NVMe KV instruction is loaded from a host memory; based on the NVMe KV instruction, obtaining a key value pair configured by a host according to to-be-operated data and an operation code corresponding to a host demand operation type; the KV operation corresponding to the operation code is executed according to the key value pair, and the configuration operation of the key value pair is unloaded to the host to be executed, so that the computing resource occupation amount of the SSD is reduced, and the service quality of the SSD is improved.

Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

The application is suitable for the technical field of data processing, and provides a software type detection method and device, terminal equipment and storage medium, the method comprises the following steps: obtaining software data of a to-be-detected software; extracting software features of the to-be-detected software from the software data, wherein the software features comprise operation code features, text features, permission features and image features; classifying the to-be-detected software according to the software features to obtain multiple classification results of the to-be-detected software; determining composite software features of the to-be-detected software according to the multiple classification results; and determining the software type of the to-be-detected software according to the composite software features. The application can solve the defect that the use of a single data type leads to low detection accuracy in the related art, help to improve the accuracy and robustness of detection, and does not need to update a feature library, thus helping to reduce the maintenance cost.

An operator compilation method includes: obtaining a compilation operator, where the compilation operator indicates a compilation rule for a source code; compiling the source code based on the compilation operator to obtain one or more tensor instructions, where the tensor instruction is used to execute a computing task in a compute-in-memory system, and the tensor instruction comprises one or more of the following instruction segments: an operation code, a tensor address, a data type, a data bit width, or a tensor length; and storing the tensor instruction into an instruction storage list, where the instruction storage list is used to store a compiled tensor instruction.

Embodiments detailed herein relate to matrix operations. In particular, support for a matrix transpose instruction is detailed. In some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.

The application discloses a kind of based on coprocessor's taint propagation method and system.The steps of the method include:1) pre-analysis instruction semantics, construct the taint propagation mask table of instruction;2) by coprocessor, intervene CPU instruction pipeline decoding, write-back process;3) in decoding stage, the opcode and operand of current instruction are acquired in real time quickly, and the taint propagation mask corresponding to instruction is found in taint propagation mask table by coprocessor;4) in write-back stage, the mask table corresponding to current instruction is searched in real time quickly, and taint propagation calculation is implemented.The application can analyze the semantics of instruction, calculate taint propagation process by using the characteristics of hardware fast and accurate when CPU instruction is executed by configuring the input function return value of monitoring.

Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

The invention relates to a processor and a memory access method. The processor comprises a UAV instruction sending unit, a UAV register management unit, a general register unit, a UAV data caching unit and a loading storage unit; the loading storage unit is configured to receive an SIMD instruction; reading resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; under the condition that the SIMD instruction is determined to be a loading instruction according to the operation code, reading channel logic address information of each channel from the general register unit; under the condition that the memory addresses to be accessed by the multiple channels of the SIMD instruction are judged to be continuous, calculating the memory access address of the first channel, and calculating the memory access addresses of the other channels based on the memory access address of the first channel; and generating a memory access request based on the memory access address of each channel. According to the method, the throughput rate of the loading storage instruction of the continuous address is improved, the number of ALUs calculated by the memory address is reduced, and meanwhile, the power consumption is reduced.

Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.

A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.

A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source / destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.

The application discloses a decompilation processing method and device, electronic equipment and a storage medium, and relates to the field of computers.The method comprises the following steps: creating three dynamic arrays in the form of class objects, namely a first dynamic array, a second dynamic array and a third dynamic array; traversing each Java Card bytecode, and based on the operation code and the operand of the Java Card bytecode, dynamically filling the Java Card bytecode and the generated Java bytecode information after conversion into the first dynamic array, the second dynamic array and the third dynamic array; and reading the Java Card bytecode in the dynamic array in sequence, and performing linkage address conversion mapping of the Java Card bytecode, so as to realize decompilation processing of the Java Card bytecode.The application can normally process decompilation operations in a scenario where the length of an operation object exceeds the agreed length.

A processor (101) with an instruction set comprising a looping instruction and corresponding method are provided. The looping instruction is defined by a corresponding opcode and comprises a register operand for holding a sequence of subinstructions. The looping instruction causes the processor (101) to: repeatedly execute the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions.

Disclosed are an SM access method and device, a computer equipment, and a non-transitory computer-readable storage medium. The method includes: receiving an SM reduction instruction; performing an equal-reduction judgment on valid lanes according to address information in the SM reduction instruction, and splitting the valid lanes according to a result of the equal-reduction judgment; reading data from the SM according to split results of the valid lanes, the split result being associated with the number of times the data need to be read from the SM; performing a reduction operation according to the data read from the SM, the source data and the operation code in the SM reduction instruction, and writing a result of the reduction operation into the SM.

The embodiment of the invention provides an instruction processing method and device, electronic equipment and a readable medium, and relates to the technical field of computers.The method comprises the steps that a to-be-replaced instruction in a target binary program is recognized, and operation codes and operands of the to-be-replaced instruction are extracted respectively; the instruction to be replaced is a vector instruction which is not supported by the current equipment. Based on the operation code and the operand, obtaining a scalar instruction sequence corresponding to the instruction to be replaced; wherein functions realized by the scalar instruction sequence are correspondingly the same as functions realized by the instruction to be replaced. And before the to-be-replaced instruction is executed, replacing the to-be-replaced instruction with the scalar instruction sequence. Therefore, by identifying the vector instruction which is not supported by the current equipment, only the vector instruction which is not supported by the current equipment is replaced by the corresponding scalar instruction sequence, so that the overall processing overhead can be reduced and the processing efficiency can be improved while the replaced instruction can be normally executed in the current equipment.

A processor for executing neural network inference includes a CPU, weight and state memory, and a fabric comprising a plurality of programming elements. Each programming element comprises an ALU, having a controller and a core, and a sequencer configured to receive a sequencer program comprising at least one sequencer instruction, the at least one sequencer instruction comprising a compressed representation of one or more arithmetic ALU op codes; decompress the sequence instruction to produce the one or more ALU op codes; and provide the one or more ALU op codes thus produced to the ALU controller. The ALU controller is configured to output a control signal to configure a data path of the ALU for executing one or more operations in performing inference, for each op code received from the sequencer. The CPU controls execution of sequencer programs by the plurality of programming elements.

Circuits and methods for conditional fence instructions are described. In some examples, a hardware processor (e.g., a core) includes a branch predictor to predict one of an taken path and an untaken path of a conditional branch instruction; decoder circuitry to decode an instruction to a decoded instruction, the instruction including a field indicating a condition set by executing another instruction and an opcode indicating that the execution circuitry will implement an execution fence in response to the condition being satisfied to delay execution of the instruction prior to execution of a previous instruction in a program order, the opcode indicating that the execution circuitry will implement the execution fence in response to the condition being satisfied. And before the instruction is executed, delaying execution of an instruction following the instruction according to the program order; and the execution circuit is used for executing the decoded instruction according to the operation code.