393 results about "Opcode" patented technology

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

The invention discloses a self-adaptive threat blocking method and system oriented to industrial control protocol deep analysis, and the method comprises the steps: constructing an industrial control protocol multi-dimensional analysis model, extracting an operation code semantic rule, a parameter structure constraint and session state hopping features based on protocol reverse engineering, generating a protocol syntax tree, and blocking a threat from the protocol syntax tree. Wherein the operation code semantic rule is matched with the service primitive mapping of an abstract communication service interface in the IEC 61850 standard; based on the protocol syntax tree, semantic-level analysis is carried out on real-time communication flow, dynamic indexes are extracted, the dynamic indexes comprise a process value mutation gradient, an instruction sequence logic conflict degree and a session state abnormal jump rate scale, and a three-dimensional threat feature vector is generated. According to the method, hidden attacks are accurately recognized through industrial control protocol semantic analysis and multi-dimensional dynamic blocking, so that the defense action and the production stability can be collaboratively optimized.

The invention relates to the technical field of wind power generation. The invention provides a network security protection method and system of main control equipment for wind power generation. The method comprises the following steps: receiving a control instruction, performing syntax tree analysis on an industrial control protocol, extracting an operation code and a parameter value, verifying the operation code, and verifying the parameter value; dynamically calculating a threat value based on the control instruction frequency, the cross-protocol request ratio and the deviation between the actual parameter value and the predicted value, and judging an attack risk according to the threat value level; establishing a normal operation baseline of the main control equipment or the remote terminal, and detecting the abnormal probability of the control instruction sequence in real time; calculating the physical rationality probability of the control instruction through a Bayesian network in combination with the environmental parameters of the wind speed, the power grid frequency and the equipment operation state; and according to the threat value level, the abnormal probability and the physical rationality probability, executing a multi-level response action. The problems of protocol protection superficial layer, environment correlation deficiency, emergency mechanism stiffness and the like in existing wind power generation main control equipment network security protection are solved.

One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.

Techniques for early fetch of one or more call instructions are described. In certain examples, a hardware processor comprises a memory; an instruction fetch circuit to fetch an instruction from the memory for decode; a decoder circuit to decode the fetched instruction; and an early “call instruction” fetch circuit to determine that the instruction is a direct call, and in response to the instruction being the direct call, determine a target address for the direct call, and cause the target address to be sent to the instruction fetch circuit for a fetch of one or more instructions at the target address. In certain examples, the early call instruction fetch circuit is to determine that the instruction is the direct call based on an opcode of the fetched instruction.

Methods and systems, including computer-readable media, are described for exploiting data sparsity during computations for a neural network implemented on a hardware accelerator. Using a system controller, a set of compressed sparse parameters is derived from a parameter tensor and a mapping vector is generated based on the set of compressed sparse parameters. When the system(s) processes an opcode in an instruction indicating sparsity of the parameter tensor, an input vector is obtained from a first memory of the hardware accelerator and the compressed sparse parameters and the mapping vector are retrieved from a second memory of the hardware accelerator. The input vector is processed through a layer of the neural network using the mapping vector and the set of compressed sparse parameters.

The invention discloses a protocol conversion method and device, a medium and a server system, and relates to the technical field of servers. Once an original protocol type is determined, a dynamic interface routing controller calls a corresponding conversion program stored in a mapping table; and converting the detected heterogeneous bus protocol command into a unified single-line serial bus protocol operation code. As the conversion program and the protocol characteristics are stored in the mapping table, the method has infinite protocol expansion capability, a new protocol can be supported by updating the mapping table and a detection engine without redesigning hardware or modifying codes of an editable logic device, the system design is greatly simplified, and the development cost is reduced. Therefore, the problem that the current programmable logic device can only realize single interface protocol conversion is solved.

The invention relates to the technical field of chip control management, in particular to a multi-level control chip channel management method and device.Firstly, a BMC analyzes an operation instruction sent by a user and sends a packaged internal instruction message to a master control MCU chip; after the MCU verifies that the message is complete, a target FPGA is determined based on the packaged internal instruction message, and then an operation code and a target identifier are sent to the target FPGA in a first instruction message mode; and finally, the target FPGA analyzes the first instruction message after receiving the first instruction message, extracts the operation code and the target identifier, searches a local SoC control interface mapping relation according to the target identifier, and drives a corresponding pin according to the operation code and the local SoC control interface mapping relation. When the SoC chip is added, only a new FPGA + SoC needs to be expanded on an existing FPGA or added to a new block. The master control MCU chip can be connected with the newly-added FPGA only by adding a small number of UART channels or multiplexing an existing bus, and expansion is achieved.

The invention discloses a loop control method and system based on RISC-V expansion. The loop control method comprises the following steps: customizing a loop control instruction in a main operation code and an instruction coding space reserved by RISC-V; an instruction fetching module, a decoding module, a state control register and a hardware loop control module are designed, loop information is written into the state control register by the decoding module, the loop information is read from the state control register by the hardware loop control module, arbitration is carried out by combining a control signal and an instruction address of the decoding module, and when a current address does not reach a loop end, the hardware loop control module is started. Sending an enable signal to enable the instruction fetching module to fetch instructions in sequence, and sending a cycle start address to the instruction fetching module to enable the instruction fetching module to circulate continuously when the current address reaches the last instruction of the cycle section and the cycle times are not reset to zero, so that a condition jump instruction of existing cycle judgment is omitted; and an assembly instruction part for loop control is replaced by an expanded loop control instruction, so that the performance loss caused by a loop program can be effectively reduced.

One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.

The disclosure relates to systems and methods for executing instructions to convert into a 16-bit floating point format. In one embodiment, a processor includes fetch circuitry to fetch an instruction having a field to specify positions of an opcode and a first source vector including N single precision elements and a target vector including at least N 16-bit floating point elements, the opcode instructs execution circuitry to convert each element of the first source vector into a 16-bit floating point format and store each converted element into a corresponding position of the target vector, the conversion including truncation and rounding if necessary; the decoding circuit is used for decoding the instruction; and execution circuitry to respond to the instruction in accordance with the opcode.

Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the first and second matrices, broadcast up to two NZ elements at a time from each row of the first matrix and each column of the second matrix to a processing engine (PE) grid, each PE to multiply and accumulate matching NZ elements of the first and second matrices with corresponding elements of the third matrix. Each PE further to store an NZ element for use in a subsequent multiplications.

The invention discloses an intelligent contract vulnerability detection method based on a multi-level data dependence heterogeneous graph, and belongs to the technical field of intelligent contract security. Intelligent contract byte codes are used as input, contract byte codes are converted into operation codes, and a control-data heterogeneous graph with basic blocks as nodes is constructed; designing an in-block data dependency sub-graph, and forming multi-level data dependency with the inter-block data stream; based on the generated control-data heterogeneous graph, a feature weighted relation graph convolutional network is provided, and control flow and data flow feature weights are dynamically adjusted and optimized by using node static attributes such as dominating tree depth and the like, so that multi-modal semantic efficient aggregation is realized. According to the method, for the contract without a public source code on the block chain, vulnerability detection only for the bytecode of the intelligent contract is realized, and high detection efficiency can be achieved under the condition that the detection accuracy is guaranteed.

The invention discloses a video card information monitoring system, a server, a monitoring method and a storage medium. Comprising a graphics card and a substrate management controller, the display card comprises a command register, a data register and a processor; the baseboard management controller generates a request instruction containing a first type of operation codes and at least one parameter according to a monitoring demand, sends the request instruction to the command register, reads a status bit from the command register, and reads data from the data register or writes the data according to the request instruction; the command register receives a request instruction sent by the substrate management controller, stores an operation code, a parameter and a status bit, and feeds the status bit back to the substrate management controller; the processor analyzes and executes the request instruction in the command register, and updates the status bit in the command register; the data register stores data written by the baseboard management controller or the processor and allows the baseboard management controller or the processor to read the data, and the problem that the number of monitorable information is limited due to I2C address limitation is solved.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

The invention discloses a contract vulnerability detection method and system based on cross-granularity feature fusion and meta-learning, and relates to the technical field of block chain security, the method comprises the following steps: obtaining a source code and a compiled byte code of a contract to be detected; source code semantic features are extracted from the source code, operation code execution features are extracted from the byte code, and graph structure features are extracted after a program dependency graph is constructed from the source code; performing cross-granularity attention interaction to generate cross-granularity fusion features; performing type-aware feature modulation on the cross-granularity fusion feature and a vulnerability type identifier of the current detection task, training a classifier by adopting a meta-learning strategy, and outputting a vulnerability detection result; and in response to the vulnerability detection result that the vulnerability exists, positioning the vulnerability code position based on the graph-source code attention weight matrix generated in the cross-granularity attention interaction process, thereby solving the problem of poor generalization ability in a rare vulnerability scene with scarce samples.

According to the branch prediction method provided by the invention, the branch prediction result is obtained by indexing the historical branch prediction instructions in the branch prediction condition table, and the relevance between the historical branch prediction instructions can be well utilized, so that the success rate of branch prediction is greatly improved; meanwhile, the last four bits of the branch prediction instruction and values in the global historical register are subjected to logical operation, an operation value is obtained and then indexed, and the influence of the alias of the branch prediction instruction on branch prediction can be reduced; meanwhile, when the branch prediction result is skipping and the operation code of the branch prediction result is matched with the operation code of the indexed historical branch prediction instruction, the branch prediction result is trusted, so that the branch prediction accuracy is further improved; and moreover, the jump address is obtained by adopting a direct operation method, so that the area overhead and the delay caused by storing a large number of branch addresses by the BTB (Branch Target Buffer) can be saved.

The invention relates to a malicious APP family identification method based on multi-modal feature fusion, and belongs to the technical field of information security. The method comprises the following steps: performing data preprocessing on the Android APK, including unpacking and decompiling operations, to obtain a byte code file and a smali code file; respectively extracting byte code image features, operation code sequence features and control flow chart features; according to the method, byte code image features are extracted by using an OfficientNetV2L convolutional neural network, operation code sequence features are extracted by using a k-Shingles algorithm and a SimHash algorithm, and control flow chart features are extracted by using a static analysis tool and a capsule graph neural network. And carrying out low-rank multi-modal fusion on the three features, and constructing a CNN-BiLSTM-Attention detection classification model, so as to realize identification and judgment on the malicious APP family. According to the method, the recognition accuracy is improved, and the generalization ability of the model is enhanced.

The embodiment of the invention discloses a data processing system and a data processing method based on RISC-V. The data processing system comprises an instruction coding space and a reconfigurable execution unit, the instruction coding space comprises an operation code area, a reserved area and an expansion area; the instruction coding space is used for defining a basic operation to be executed by an instruction in the operation code area, defining an extended operation to be executed by the instruction in the reserved area and defining the length of the instruction in the extended area so as to configure different types of instructions; the reconfigurable execution unit is used for constructing a data path matrix of the instruction based on the configuration information of the instruction; transmitting data required when the instruction is executed based on the data path matrix; and executing an operation corresponding to the instruction based on the data of the instruction.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.

CAN bus signal format inference includes: extracting candidate signals from training CAN bus message traffic; defining one or more signals, each signal being a candidate signal that matches structural characteristics of a matching data type and each signal being assigned the matching data type; and generating an inferred CAN bus protocol with which the defined one or more signals conform. Signals are extracted from CAN bus message traffic using the inferred CAN bus protocol, an anomaly in an extracted signal is detected, and an alert is generated indicating the detected anomaly. In another aspect, a transport protocol (TP) signal is extracted and analyzed to determine a fraction of the TP signal that matches opcodes of a machine language instruction set, and an anomaly is detected based at least in part on the determined fraction exceeding an opcode anomaly threshold.

The invention discloses an industrial control system configuration cloud compiling method and system, and relates to the technical field of cloud computing cross.The method comprises the steps that a logic flow graph is traversed in a depth-first mode, the occurrence frequency of an instruction operation code is counted, and an information density degree evaluation value of a program code is calculated; based on the information intensive evaluation value, analyzing the distribution characteristics of the occurrence frequency of the operation code type and the weight of the operation code, and combining with an instruction entropy threshold comparison result, identifying a high-frequency redundant instruction operation code, compressing and combining the high-frequency redundant instruction operation code, optimizing a conditional jump structure of a logic flow graph, and generating an intermediate optimization code unit; and based on the intermediate optimization code unit, carrying out topological dependency analysis and implementing local increment compiling verification to generate an executable machine code. According to the method, the information intensity evaluation value of the program code is calculated, the high-frequency redundant operation code is accurately recognized, semantic-level compression and combination are carried out, and a simple and reliable control program code is generated under the condition of maintaining industrial hard real-time constraint.

The invention provides a near-memory computing system based on an RISC-V instruction set architecture, and belongs to the technical field of near-memory computing. The system comprises a near storage architecture instruction set module based on software and hardware collaboration, an instruction set model module, an energy efficiency instruction path module and a storage and calculation integrated module. The near storage architecture instruction set module integrates an operation code configuration and operation mechanism in each instruction of the RISC-V instruction set, so that the special instruction set realizes corresponding execution control; the instruction set model module adopts an instruction arrangement mode of neural network layer structure mapping, and minimizes the number of instructions through a loop instruction to support an iteration process; the special instruction set of the energy efficiency instruction path module follows an instruction path for sequentially executing each stage; and the storage and calculation integrated module dynamically switches a calculation path according to an instruction demand by fusing storage and calculation. According to the customized RISC-V ISA for the NMC system provided by the invention, neural network reasoning with energy efficiency optimization is realized.

The invention provides a power management chip dynamic control method and system based on hybrid modulation. According to the method, an instruction decoding unit is arranged in a chip to intercept an operation code sequence feature identifier, and a current detection unit is activated to collect a transient power consumption fluctuation curve of a power supply loop; the operation code identifiers and the power consumption curves are aligned and associated according to timestamps in a time sequence alignment module, and a load behavior feature library is constructed; the magnetic flux control current is adjusted through the driving circuit, so that the medium reaches the preset magnetic flux saturation before load transition; decomposing instruction stream fragments, performing waveform similarity matching on the instruction stream and the magnetic flux control current, and detecting a specific instruction combination mode; and writing a control parameter into the modulation logic unit based on the detection result and the magnetic flux saturation, and switching the working state combination of the step-down and step-up hybrid conversion mode. According to the invention, the transient response speed and the energy transmission efficiency of the power management chip in a video rendering burst load scene are improved.

Instructions to execute in a computing environment are obtained. The instruction includes an opcode indicating a diagnostic operation. The instruction is executed. The execution includes obtaining a token as input to the instruction and comparing the token to a current token of the computing environment for configuration. Based on the token matching the current token, one or more verification certificates are returned from a certificate store.

Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

The invention is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and a program product, and the method comprises the steps: obtaining instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on the original effective vector; each index value in the index vector is subjected to one-hot code conversion, a one-hot code matrix corresponding to the instruction set to be processed is generated, and each row of one-hot code vector in the one-hot code matrix corresponds to each path of input instruction; and according to the original effective vector and the one-hot code matrix, sorting operation codes of each path of input instruction to obtain processed operation code information, so that a processor executes corresponding operation based on the processed operation code information. The method can meet the requirement that the high-performance processor completes instruction processing in a single cycle, the processing delay is low, and therefore the instruction execution efficiency of the processor is improved.