36 results about "Opcode" patented technology

Embodiments detailed herein relate to matrix operations. In particular, support for a matrix transpose instruction is detailed. In some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.

Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.

Disclosed are an SM access method and device, a computer equipment, and a non-transitory computer-readable storage medium. The method includes: receiving an SM reduction instruction; performing an equal-reduction judgment on valid lanes according to address information in the SM reduction instruction, and splitting the valid lanes according to a result of the equal-reduction judgment; reading data from the SM according to split results of the valid lanes, the split result being associated with the number of times the data need to be read from the SM; performing a reduction operation according to the data read from the SM, the source data and the operation code in the SM reduction instruction, and writing a result of the reduction operation into the SM.

A processor for executing neural network inference includes a CPU, weight and state memory, and a fabric comprising a plurality of programming elements. Each programming element comprises an ALU, having a controller and a core, and a sequencer configured to receive a sequencer program comprising at least one sequencer instruction, the at least one sequencer instruction comprising a compressed representation of one or more arithmetic ALU op codes; decompress the sequence instruction to produce the one or more ALU op codes; and provide the one or more ALU op codes thus produced to the ALU controller. The ALU controller is configured to output a control signal to configure a data path of the ALU for executing one or more operations in performing inference, for each op code received from the sequencer. The CPU controls execution of sequencer programs by the plurality of programming elements.

This invention proposes an on-network computing request message management method, switch, device, and medium, relating to the field of network communication technology. The method includes: allocating corresponding cache space based on read request messages sent by the GPU; generating a state table corresponding to the read request message and refreshing the state table to a first state; scanning the cache space according to a preset time; if no feedback message corresponding to the read request message is found, refreshing the state table to a second state; the second state is different from the first state; generating a corresponding aging opcode based on the second state and clearing the cache space; feeding back the aging opcode to the GPU so that the GPU releases memory associated with the read request message. This invention can achieve timely processing of message-related storage space, saving system resources.

Embodiments of the present application provide a data processing method, smart glasses, a storage medium and a program product. The method comprises: obtaining a first target data frame, the first target data frame comprising at least one first sub-data frame, the first sub-data frame comprising a frame header and a payload, the frame header comprising an operation code field; determining format information and length information of the payload according to the value of the operation code field corresponding to the first sub-data frame; parsing the payload according to the format information and the length information to obtain parsed data; and performing a corresponding processing operation according to the parsed data. The present application uses a preset binding mechanism of the operation code and the payload length and format, so that the payload length can dynamically change according to the actual business data, significantly reducing the invalid transmission bytes, improving the effective payload ratio of a single frame of data, and for long data, being able to accommodate longer effective data in one frame, thereby reducing the additional frame header overhead and transmission times due to forced packeting, and improving the overall transmission efficiency.

The present application relates to the technical field of Ethereum smart contract vulnerability detection, and discloses an operation code sequence generation method based on Ethereum transaction data replay, comprising the following steps: S1: Geth client plug-in stage, S2: data replay stage, S3: transaction operation code sequence acquisition stage, and S4: transaction operation code sequence storage stage. When executing in a virtual machine, the bytecode is converted into operation codes by using the API provided by Geth. Therefore, the process of calling a method in a smart contract is actually the process of executing the operation code sequence in the method, and thus it can be considered that the operation code sequence executed in the calling order constitutes a control flow path of a transaction execution. The operation code sequence generation method based on Ethereum transaction data replay collects the operation code sequence in the transaction execution process, is used for machine learning and deep learning model training, and can improve the accuracy of detecting known vulnerabilities and unknown vulnerabilities of a smart contract.

Techniques for implementing instructions for a trust domain implemented by a processor are described. In certain examples, a hardware processor core, that implements a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, includes a debug register; a control register; decoder circuitry to decode a first single instruction into a first decoded instruction, the first single instruction having a field to indicate a data structure to store a control state of a trust domain and a debug state of the trust domain, and an opcode to indicate execution circuitry is to load the control state of the trust domain from the data structure into the control register and load the debug state of the trust domain from the data structure into the debug register; and the execution circuitry to execute the first decoded instruction according to the opcode.

This invention discloses a smart contract vulnerability detection method based on opcode semantic enhancement and multi-instance learning. The method first compiles the smart contract into bytecode and disassembles it into an opcode sequence, constructing a control flow graph to extract multiple execution paths. Then, it achieves opcode-level semantic enhancement by classifying the operands following the opcode and concatenating them with the opcode, using a BERT pre-trained model for semantic encoding, and designing an attention pooling layer to aggregate path-level features. Finally, it employs a multi-instance learning framework, using a hybrid loss function and a periodic data update mechanism to achieve accurate vulnerability localization from contract-level labels to path-level vulnerabilities. Compared with existing static analysis tools and traditional machine learning methods, this method has significant advantages in detection accuracy, false positive rate, and interpretability, accurately identifying vulnerabilities and mapping them to their source code locations.

This paper relates to a method and apparatus for implementing a write mask vector instruction based on RISC-V. The method includes generating the original mask for the current uop based on the mask calculation identifier in the instruction opcode; adapting the original mask to the vlen value to obtain the final mask; after processing the mask, when executing the current uop, obtaining the execution result of the previous uop, the first source operand, the second source operand, and the final mask, and utilizing the characteristics of the mask, ensuring that the current uop maintains the calculation result of the previous uop during execution, thus saving the calculation result of the current uop, the calculation result of the previous uop, and the target operand, keeping the number of uops and VRF ports unchanged, thereby completing the instruction calculation. Compared to existing methods that increase the number of uops or increase VRF ports, the method described in this paper improves instruction execution efficiency and reduces resource consumption.

This invention discloses a secure access method for network interface card (NIC) firmware based on dynamic instruction mapping and transactional buffering. During session initialization, the driver and application construct an instruction opcode mapping table and data structure offset rules valid only for the current session based on a negotiated random seed, achieving dynamic obfuscation of communication protocol features. When processing write requests, the driver temporarily stores the data, reads the current hardware snapshot, performs semantic-level virtual assembly and logical conflict prediction, and intercepts dangerous operations with valid signatures but mutually exclusive configuration logic. Only after pre-verification passes and a commit instruction is received does the driver calculate the differential bitstream between the shadow buffer and the hardware data, lock the bus, and perform atomic incremental synchronization. This invention effectively resists reverse engineering and replay attacks through three mechanisms: dynamic protocol transformation, logical conflict immunity, and differential atomic commit, while also preventing firmware corruption caused by configuration errors or abnormal interruptions.

This application discloses a method, apparatus, medium, and product for reducing branch prediction error overhead. The method includes: in response to a signal indicating that both instructions are conditional jumps, obtaining a first target instruction, a second target instruction, and an update opcode of the first target instruction with identical physical registers; when the first target instruction is triggered again, if the prediction result of the first target instruction is a jump and the prediction is incorrect, obtaining the target register based on the update opcode, obtaining the branch jump target result accordingly, and re-fetching the second target instruction based on this result after pipeline flushing. This method can, when the first target instruction is triggered again and a predicted jump occurs with an error, obtain the branch jump target result corresponding to the associated second target instruction based on the corresponding register information, discarding the prediction result of the prediction module itself, effectively avoiding the overhead of a single branch prediction error and pipeline flushing.

Generally disclosed herein is an approach for an optimized data computation for machine learning (ML) operations using a plurality of small-sized ML accelerators integrated into a general-purpose compute system-on-chip (SoC). One or more processors of the general-purpose compute SoC may be configured to receive a workload and divide the workload into a plurality of sub-workloads. The plurality of sub-workloads may be distributed among the plurality of small-sized ML accelerators. Each of the plurality of the ML accelerators can be configured to output a partial outcome. The outputs from each ML accelerator can be combined using atomic store operations using a dedicated opcode and a specified memory address.

Fine-grained preemption of a data flow architecture based neural processing unit (NPU) includes executing, by a controller, control-code that implements a first context in the NPU. In response to the controller detecting a preemption opcode in the control-code, detecting, by the controller, a second context awaiting execution by the neural processing unit. The second context has a priority that is greater than a priority of the first context. In response to detecting the second context, the NPU switches from executing the first context to implementing the second context.

The application relates to the technical field of cloud network fusion, in particular to an operation and maintenance data processing method and system based on cloud network fusion technology, which comprises the following steps: according to cloud network edge node monitoring ports, CPU encoding time length, decoding time length and network data packet transmission time length of an IoT gateway are collected; the CPU encoding time length and the decoding time length are operated to obtain total serialization processing time length; and the total serialization processing time length is used as a basis. In the application, for the scene where heat dissipation is limited or voltage is unstable, a high-energy-consumption high-parallelism SIMD operation code is rewritten into a serial operation code, and a no-operation instruction is inserted according to a pipeline duty cycle. The instruction level fine energy efficiency control reduces instantaneous power density and chip heat consumption, ensures that business continuous operation and instruction flow stable throughput are maintained under the condition that the hardware physical boundary is limited, avoids system downtime or performance avalanche caused by overheating protection, and improves the survival ability of edge side equipment under complex working conditions.

This invention relates to the field of SOME / IP communication, and proposes a method and system for SOME / IP message serialization / deserialization based on IDL compilation. The method includes: parsing an IDL file to obtain data type definitions; calculating the offset of each field in the structure for each structure type; generating an opcode for each field according to the opcode rules and constructing an opcode array; constructing a descriptor based on the number of bytes occupied by the structure, the starting address of the opcode array, and the total number of opcodes; outputting C language code for each structure type, including header and source files; importing header files to create server / client instances; when sending data, looking up the descriptor through the communication identifier ID, serializing the data structure according to the corresponding opcode array, converting it into a SOME / IP format byte stream, encapsulating it into a message for transmission; and when receiving a message, deserializing the byte stream through the reverse operation direction of serialization.

An instruction has an opcode and at least one data operand, the opcode identifying a data processing operation to be performed on the at least one data operand. For a register-provided opcode instruction specifying at least one source register, at least a portion of the opcode is a register-provided opcode represented by a first portion of data stored in the at least one source register for the register-provided opcode instruction, and the at least one data operand includes data represented by a second portion of data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided opcode instruction.

The application discloses a malicious code semantic perception static detection method and system and a storage medium, and belongs to the technical field of cyberspace security. In view of the problems of poor anti-confusion ability of existing regular matching technology and high false alarm rate caused by the inability to distinguish RCE attacks from DoS abnormalities, the application proposes a solution based on an abstract stack machine and a taint analysis. The method first extracts a serialized operation code sequence, simulates stack behavior by using an abstract stack machine and a sentinel mechanism to restore instruction structure; secondly, in combination with a semantic environment knowledge base, a reflective call is deeply deduced, and obfuscated code is restored to real semantics; finally, based on a four-state taint analysis model, a judgment strategy of triggering an alarm only when a high-risk function is called and the parameters contain taint data is implemented. The application can effectively resist Fickling and other advanced obfuscation attacks, accurately filter non-malicious program noise, and significantly improve the accuracy and anti-interference ability of model security detection.

Fine-grained preemption of a data flow architecture based neural processing unit (NPU) includes executing, by a controller, control-code that implements a first context in the NPU. In response to the controller detecting a preemption opcode in the control-code, detecting, by the controller, a second context awaiting execution by the neural processing unit. The second context has a priority that is greater than a priority of the first context. In response to detecting the second context, the NPU switches from executing the first context to implementing the second context.

The application discloses an intelligent contract vulnerability detection method combining adversarial transfer learning and multi-task learning. First, in the data preprocessing stage, the operation code sequence formed by the decompilation of the intelligent contract sample source code is processed by using an N-Gram language model to construct a 2-gram operation code syntax sequence, and the input of the model is formed. Secondly, in the model construction stage, a bottom shared layer based on a mixed parameter sharing architecture design is constructed to extract general features and private features; a top task layer of a multi-task classification network based on a neural network is constructed to realize the detection and identification tasks of the intelligent contract vulnerability; and finally, the intelligent contract vulnerability detection model is constructed by combining adversarial transfer learning and multi-task learning. In the training stage, the 2-gram operation code syntax sequence obtained in the data preprocessing stage is input into the model for training, and the application has good generalization performance.

A method for processing an instruction includes storing a result of execution of an instruction in a table, calculating an index pointing to a specific entry in the table by using an opcode of the instruction and at least one operand, searching for the specific entry by using the index and transmitting data stored in the searched specific entry to a destination register or a memory.

Techniques for rotation in response to an instance of a single instruction are described. In some examples, an exclusive OR is also performed. In some examples, the instruction has one or more fields for an opcode, a first source operand, a second source operand, a third source operand location, a destination operand location, and an immediate, wherein the opcode is to indicate execution circuitry is to rotate each data element of the third source operand by 1 to generate a rotated third source operand, exclusive or (XOR) corresponding data elements of the first source operand, the second source operand, and the rotated third source operand, rotate the XORed data elements by an amount indicated by the immediate, and store a result of the rotated, XORed data elements. In some examples, a dispatch port is associated with a different set of execution circuitry, wherein each different set of execution circuitry is to support a different maximum rotate amount, and wherein the immediate is to be used to determine which of the dispatch ports to use.

Disclosed herein is a method for optimized data computation for machine learning (ML) operations using a plurality of small ML accelerators integrated into a general-purpose computing system on a chip (SoC). One or more processors of the general-purpose computing SoC can be configured to receive a workload and divide the workload into a plurality of sub-workloads. The plurality of sub-workloads can be distributed among the plurality of small ML accelerators. Each ML accelerator of the plurality of ML accelerators can be configured to output a partial result. The output of each ML accelerator can be combined using an atomic store operation with a dedicated opcode and a specified memory address.

This invention discloses a vulnerability detection method and system based on smart contract bytecode, belonging to the field of smart contract security. It addresses the problem in existing technologies where the model construction process is related to the vulnerability type, resulting in poor model versatility. This invention collects arbitrary smart contract bytecode to construct a smart contract opcode data flow graph, and then constructs a pre-training dataset based on the opcode data flow graph. Based on the pre-training dataset, it constructs and trains a pre-trained model to determine whether two basic blocks in the data flow graph are adjacent. It collects unlabeled smart contract bytecode to construct an opcode control flow graph, and then constructs a smart contract vulnerability dataset based on the opcode control flow graph. Based on the parameters of the trained pre-trained model and the smart contract vulnerability dataset, it constructs and trains a smart contract vulnerability detection model. Finally, it uses the trained smart contract vulnerability detection model to perform vulnerability detection on the control flow graph of the smart contract under test. This invention is used for vulnerability detection in smart contracts.

A command for causing a graphics processor to perform processing work for a graphics processing pipeline that the graphics processor can execute. A command to perform processing work for the graphics processing pipeline includes a first portion including a generic opcode that can be interpreted by a command processing circuit of the graphics processor to identify that the command is a command to perform processing work for the graphics processing pipeline and a second portion that is not used by command processing circuit but identifies to the graphics processing pipeline the particular processing operations to be performed. The first portion also includes information indicating a set of zero or more data values to be used for one or more processing operations for the graphics processing pipeline.

Techniques for an instruction for a Runtime Call operation are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of an opcode, the opcode to indicate execution circuitry is to execute a no operation when a runtime call destination equals a predetermined value; and execute an indirect call with the runtime call destination as a destination address when the runtime call destination does not equal the predetermined value. Other examples are described and claimed.

This specification discloses a risk detection method, apparatus, and device for a blockchain system. The method includes: acquiring transaction information of a transaction invoked through a smart contract and the opcode sequence executed by the transaction; based on the transaction information, running the opcode sequence through a blockchain client and calculating a first code coverage rate of the opcode sequence run by the blockchain client; performing mutation processing on the opcode sequence to obtain a mutated opcode sequence that meets preset target mutation conditions, wherein the change in the number of stack elements corresponding to the mutated opcode sequence meets a preset first sub-condition, and the code coverage rate of the mutated opcode sequence run by the blockchain client meets a preset second sub-condition with respect to the first code coverage rate; and sequentially executing the opcode sequence and the mutated opcode sequence in a local blockchain network composed of multiple blockchain nodes to obtain corresponding execution results, thereby determining the risks existing in the blockchain system.

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

The application discloses a contract vulnerability detection method and system based on cross-granularity feature fusion and meta-learning, relates to the technical field of blockchain security, and comprises the following steps: acquiring source code and compiled bytecode of a to-be-detected contract; extracting source code semantic features from the source code, extracting operation code execution features from the bytecode, and extracting graph structure features after constructing a program dependency graph from the source code; performing cross-granularity attention interaction to generate cross-granularity fusion features; performing type-aware feature modulation on the cross-granularity fusion features and a vulnerability type identifier of a current detection task, training a classifier by adopting a meta-learning strategy, and outputting a vulnerability detection result; and in response to the vulnerability detection result being that there is a vulnerability, locating a vulnerability code position based on a graph-source code attention weight matrix generated in the cross-granularity attention interaction process. The application solves the problem of poor generalization ability in the rare vulnerability scenario with scarce samples.