Secure microprocessor and method

a microprocessor and microprocessor technology, applied in the field of secure microprocessors and methods, can solve the problem that the cpu cannot install programs not encoded in the system, and achieve the effect of preventing access to the cpu

Inactive Publication Date: 2007-03-29
CZAJKOWSKI DAVID R +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0010] Briefly stated, in accordance with embodiments of the present invention a method and reconfigurable computer architecture protects binary opcode, or other data and instructions, by providing an encryption capability integrated into an instruction issue unit of each processor (CPU). Opcodes are encrypted at their source, and encrypted opcodes are then delivered to the CPU and decryp

Problems solved by technology

Also, the CPU will not be able to install programs not encode

Method used

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  • Secure microprocessor and method
  • Secure microprocessor and method
  • Secure microprocessor and method

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Embodiment Construction

[0028] Embodiments of the present invention will provide for processors which can safely store code and which are protected from reverse engineering. Processors may also be programmed by code transmitted by a developer at a remote location, and software may be maintained by an administrator at a remote location. The protected processor may be made accessible to a user either on a users own server or via a hosted service accessed through the Internet or other network.

[0029] This is particularly significant in the context of reconfigurable computer architecture. A reconfigurable computing system compiles program source code to an intermediate code suitable for programming runtime processors or reconfigurable field-programmable gate arrays, enabling a software design to be implemented directly in hardware. Since many different hardware-implemented programs can potentially perform in parallel, a reconfigurable computing system can be considered an advanced parallel processing architect...

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Abstract

A method and reconfigurable computer architecture protect binary opcode, or other data and instructions by providing an encryption capability integrated into an instruction issue unit of a protected processor. Opcodes are encrypted at their source, and encrypted opcodes are then delivered to the CPU and decrypted “inside” the CPU. Access into the CPU is prevented. Each form of code or data selected for protection is protected from unauthorized viewing or access. Commonly, the binary executable, or object, code is selected for protection. However, protected information could also include source code or data sets or both. Encrypting opcodes will result in making unique opcodes for each processor. Encryption keys and hidden opcode algorithms provide further security.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present application claims priority of U.S. Provisional Patent Application Ser. No. 60 / 719,563, filed Mar. 3, 2005, which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION [0002] The present subject matter relates to an apparatus and method for protecting software in binary format or interim data set solutions from reverse engineering, and in a further form to control operation of individual software programs only on authorized specific microprocessors by authorized persons. BACKGROUND OF THE INVENTION [0003] Reconfigurable computing hardware is programmable to provide a wide range of functions. The present discussion will refer to microprocessors since they are a prevalent from of reconfigurable hardware. However, the considerations discussed are applicable to many forms of reconfigurable computing hardware. Unique capabilities of microprocessors are enabled through the use of operation codes, also known as...

Claims

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Application Information

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IPC IPC(8): G06F12/14
CPCG06F21/14G06F21/75G06F21/72
Inventor CZAJKOWSKI, DAVID R.MURPHY, CARL
Owner CZAJKOWSKI DAVID R
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