110 results about "Reconfigurable computing" patented technology

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

The invention provides a high-performance volume rendering method and system based on autonomous controllable GPU pre-rendering. Curvature distribution characteristics of voxel surfaces are extracted through dynamic topology analysis to construct preprocessing metadata, and a reconfigurable computing array is driven to dynamically divide a hardware topology structure of a high-density ray casting unit and a hardware topology structure of a low-power-consumption interpolation unit according to the curvature characteristics. And task allocation and cooperative execution of heterogeneous computing units are realized based on an asynchronous computing engine, and finally, a multi-scale sampling result is fused through a hardware-level optimized mixed weight algorithm in an autonomous controllable rendering pipeline, and a closed-loop feedback mechanism of a rendering result and preprocessed metadata is established. According to the method, voxel geometric features, hardware architecture reconstruction and asynchronous calculation scheduling are innovatively and deeply coupled, and a technical closed loop of data feature driven hardware resource configuration and rendering result reverse optimization preprocessing parameters is formed. According to the technical scheme provided by the invention, high-fidelity real-time volume rendering of medical images and scientific data is realized.

A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.

The invention discloses a state space model accelerator, a Mama model calculation method and a Mama model calculation system. The state space model accelerator comprises a reconfigurable calculation unit used for linear calculation and element-by-element calculation; the reconfigurable computing unit comprises a reduction tree and a processing unit array; the processing unit array comprises a plurality of reconfigurable processing units; during linear calculation, each reconfigurable processing unit calculates input data; the reduction tree is in a reduction mode, and reduction tree slices in the reduction tree carry out reduction calculation on calculation results of the multiple corresponding reconfigurable processing units; when element-by-element calculation is carried out, each reconfigurable processing unit carries out element-by-element calculation on input data and outputs calculation results in parallel; the reduction tree is in a non-reduction mode. According to the Mama accelerator, a reduction-replaceable PE array architecture is adopted, and element-by-element operation and linear operation can be efficiently supported at the same time.

A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor comprising a grid of compute units and grid of memory units interconnected with a switching array. The compute graph includes a node specifying an operation on a tensor. The node may be split into multiple nodes that each specify the operation on a distinctive portion of the tensor to produce a first modified compute graph. The first modified compute graph may be executed. In addition, the multiple nodes may be within a single meta-pipeline stage and may be processed in parallel. Furthermore, the compute graph may further comprise a separate node for gathering the distinctive portions of the tensor into a complete tensor, to produce a second modified compute graph.

The invention discloses a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfiguration computing method. The reconfigurable computing array comprises a main control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconfiguration controller module, the reconfigurable computing array, an input buffer area module and an output buffer area module. The state machine module controls the whole reconstruction calculation process through state switching; the reconfiguration controller module configures the connection mode of PE units in the reconfigurable computing array according to the decoding result of the computing decoder module, and various computing functions are achieved so as to complete different types of data computing tasks. According to the method, the multiple computing units in the reconfigurable computing array are dynamically configured, so that a hardware architecture can be adjusted in real time according to different algorithm requirements, the reconfigurable computing array is accurately configured to complete different computing tasks, special hardware does not need to be designed for each task, and the computing efficiency is improved. Therefore, the flexibility of chip configuration and the resource utilization rate are improved.

The invention discloses a high-speed hardware acceleration system for a Kyber anti-quantum cryptography algorithm and an implementation method, and relates to the technical field of hardware acceleration of the anti-quantum cryptography algorithm, the high-speed hardware acceleration system comprises a dynamic resource management and scheduling center, a reconfigurable NTT computing cluster unit, a streaming polynomial coefficient cache network and a runtime security scheduler; and the dynamic resource management and scheduling center is respectively connected with the reconfigurable NTT computing cluster unit, the streaming polynomial coefficient cache network and the runtime security scheduler. According to the high-speed hardware acceleration system for the Kyber anti-quantum cryptography algorithm and the implementation method, the overall operation throughput rate and the response speed of the system are effectively improved, idle loss caused by fixed resource allocation or data waiting is reduced, the flexible reconstruction and reuse capability of hardware resources is improved, and the implementation efficiency is improved. Therefore, the same set of physical unit can efficiently adapt to different core operation modes in the Kyber algorithm, and the hardware utilization efficiency is improved.

The invention relates to the technical field of industrial automation control and robots, in particular to a heterogeneous high-real-time multi-axis robot cooperative motion control system and method.The system comprises an SoC main control layer, an FPGA driving layer and a hardware interconnection layer, the SoC main control layer adopts a heterogeneous SoC chip, an ARM processor is responsible for track planning and task scheduling, an FPGA logic deployment reconfigurable PID calculation engine is responsible for FPGA logic deployment, and the FPGA driving layer is responsible for FPGA logic deployment. A multi-axis position ring and speed ring algorithm is realized through the time division multiplexing processing unit; the FPGA driving layer comprises a plurality of FPGA coprocessors, and an FOC current loop IP core is instantiated to execute bottom layer vector control related operation; the hardware interconnection layer adopts an EPPI protocol supporting topology awareness, dynamic bandwidth allocation and a ping-pong buffering mechanism, and efficient transmission of a control instruction and feedback data is achieved. Through hierarchical control and hardware collaborative design, the problems that an existing multi-axis control system is large in calculation delay, insufficient in synchronization precision and low in hardware resource utilization rate are effectively solved.

A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein. The system includes a partitioning module that that partitions the plurality of operations into selected executable partitions according to the method describe above.

Methods, systems, and apparatus, including an apparatus for generating clusters of building blocks of compute nodes using an optical network. In one aspect, a method includes receiving request data specifying requested compute nodes for a computing workload. The request data specifies a target n-dimensional arrangement of the compute nodes. A selection is made, from a superpod that includes a set of building blocks that each include an m-dimensional arrangement of compute nodes, a subset of the building blocks that, when combined, match the target n-dimensional arrangement specified by the request data. The set of building blocks are connected to an optical network that includes one or more optical circuit switches. A workload cluster of compute nodes that includes the subset of the building blocks is generated. The generating includes configuring, for each dimension of the workload cluster, respective routing data for the one or more optical circuit switches.

The invention relates to the technical field of vehicle-mounted computing, in particular to a dynamic energy efficiency management and emergency redundancy processing device and method for vehicle-mounted heterogeneous computing, and the device comprises a reconfigurable computing array which is used for carrying out dynamic partitioning and resource scheduling on an FPGA (Field Programmable Gate Array) logic unit; the multi-protocol converged communication panel is used for receiving a plurality of sensor data input into the reconfigurable computing array and carrying out mixed scheduling on the plurality of sensor data; the AI resource scheduling engine is used for redistributing computing power in the reconfigurable computing array according to the biological characteristics and a pre-constructed reinforcement learning dynamic energy efficiency model; and the three-level emergency redundant equipment is used for switching a main power supply, activating a preset optical calculation standby channel and starting V2X point cloud reconstruction when a main calculation unit in the reconfigurable calculation array breaks down so as to release nuclear explosion calculation power. Therefore, the problems of dynamic energy efficiency deficiency, redundancy mechanism insufficiency, multi-sensor conflict and the like of an existing vehicle-mounted computing system are solved.

According to the reconfigurable multiply-accumulate unit for the neural network processor and the processor, an efficient reconfigurable multiplier is constructed by organizing a large number of low-precision multiplication units. A peripheral reconfigurable computing circuit is designed to form a multiply-accumulate unit, so that the multiply-accumulate unit can flexibly support computing requirements of various precisions, various computing types and various data paths, and the compatibility and efficiency of hardware to a neural network are remarkably improved.

The invention relates to a reconfigurable computing circuit. A reconfigurable computing circuit that performs fully homomorphic encryption (FHE) enables full utilization of computing resources and data movement resources by mapping a plurality of N * 1024 polynomials onto (M * N) * 1024 polynomials. To counteract scrambling of coefficients during number-theoretical transform (NTT) and inverse NTT operations, a computing element in a computing circuit operates in a bypass mode that is enabled by a data shift instruction to transition from a scrambled form to a continuous form without modifying the values of the coefficients.

The invention provides a lightweight elliptic curve cryptographic reconfigurable processor. The reconfigurable computing unit array comprises a shared data area and a reconfigurable instruction memory, the shared data area is used for an upper layer system to write initial data, global configuration parameters, two sets of moduli, two sets of pre-computing parameters Mu and to-be-computed data, the initial data comprises elliptic curve configuration parameters and a group of noise data, and the global configuration parameters comprise reconfigurable data of the computing unit array; the reconfigurable instruction memory is used for an upper-layer system to write reconfigurable instructions, and the reconfigurable instructions comprise an initialization instruction, an operation instruction and a jump instruction. The method can cope with application scenes such as high security, low power consumption, rapid switching and reconstruction of the ECC algorithm, can be flexibly applied to the fields of national password security, network security teaching and commercial password, and has a wide application prospect.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

The invention discloses a storage and calculation integrated architecture-based convolutional code parallel pipeline decoding acceleration system and method, and the system comprises a global data scheduling module which is used for slicing convolutional code data from magnetic tape storage equipment according to a set rule and carrying out the scheduling through a multi-stage cache mechanism; the storage and calculation integrated unit array is used for storing data tiles and intermediate results output by the global data scheduling module and executing convolution operation, path metric calculation and survival path selection through a reconfigurable calculation unit; the parallel pipeline controller is used for dynamically distributing decoding tasks and controlling the pipeline rhythm of the storage and calculation integrated unit array; the self-adaptive resource configuration module is used for monitoring system load in real time and dynamically adjusting a data distribution strategy and computing resource scheduling; the verification and error correction unit is used for performing verification and error correction on the decoding result output by the storage and calculation integrated unit array and then outputting the decoding result; according to the decoding acceleration system and method, high-efficiency and low-delay convolutional code decoding is realized.

The invention discloses a coarse-grained reconfigurable architecture cyclic mapping method and device based on a graph neural network, and relates to the technical field of computer reconfigurable computing. The method comprises the following steps: based on a priority prediction model, performing list scheduling according to a data flow diagram and hardware information to obtain a list scheduling table; performing modular scheduling according to the data flow diagram and the hardware information; pre-scheduling the data flow diagram on the basis of a list scheduling table according to the modular data flow diagram and the time extension coarse-grained array to obtain a time step attribute data flow diagram; obtaining a mapping result by using a mapping algorithm based on pattern diagram matching according to the time step attribute data flow diagram on the basis of the time extension coarse-grained array; based on the hardware information, processing unit isomorphism verification is carried out according to the mapping result; and compiling the verified mapping result to obtain an executable configuration information file. The invention provides an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on a graph neural network.

A method in a reconfigurable computing system includes connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers, which generates a plurality of skip-buffers. The method includes determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge. The method also includes merging, wholly or partially, the compatible skip-buffers to produce a merged skip-buffer having a minimal buffer depth. The described method may reduce memory unit consumption and latency.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. Executing the compute graph on the multiple RDPs.

The invention discloses a network security monitoring device based on FPGA (Field Programmable Gate Array) reconfigurable computing and a design method. The network security monitoring device comprises a general microprocessor, an input / output unit and a reconfigurable processing unit, the input and output unit is interactively connected with the reconfigurable processing unit through a bus; the universal microprocessor is in interactive connection with the reconfigurable processing unit through a bus, and the universal microprocessor is used for sending a control signal to the reconfigurable processing unit; the reconfigurable processing unit is an FPGA configuration circuit and comprises an I / O FPGA chip, a first Computing FPGA chip and a second Computing FPGA chip, and the I / O FPGA chip receives a control signal to start a configuration process; after configuration is completed, the reconfigurable processing unit has rule matching and network forwarding functions for network security monitoring. According to the invention, a monitoring environment with complex network security can be more flexibly coped with, reliable and stable network security monitoring is realized, invasion of external equipment to power grid equipment can be avoided to the greatest extent, and safe operation of the power grid equipment is protected.

A method and system for integrating buffer views into buffer access operations in reconfigurable computing environments. The method includes detecting, in a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The buffer view parameters are lowered into the tensor indexing expression, according to the buffer view indicator, to produce a modified tensor indexing expression. The buffer view indicator is removed from a buffer allocation statement to produce a modified buffer allocation statement and allocating a buffer according to the modified buffer allocation statement. The system implements the described method and further includes a non-transitory computer readable medium for executing the disclosed method.

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

The application belongs to the field of information technology and provides a column reconfigurable systolic array for a Transformer model. The main idea is to realize that each column computing unit of the array can work together for a single operator or can be split to work individually for multiple operators. The main scheme includes a reconfigurable computing unit of a two-dimensional network, which is composed of row and column distributed computing units, data is transferred from the previous row to the next row and from the previous column to the next column; a register unit of a two-dimensional network, which is composed of row and column distributed register units, data is transferred from the previous row to the next row and from the previous column to the next column, and the data transfer direction is opposite to that of the reconfigurable computing unit of the two-dimensional network; and the register and the computing unit of the same row and column are connected through a data path. A mixed parallel line is supported to improve the hardware efficiency of the Transformer-based model.

The invention provides a digital pre-distortion method, circuit and system, and relates to the technical field of communication, and the digital pre-distortion circuit comprises an upper path and a lower path which are processed in parallel, and a reconfigurable calculation module. Through the reconfigurable digital pre-distortion circuit, real-time adjustment of nonlinear order, memory depth and model item combination can be realized, and different nonlinear characteristics of PA can be matched; a reconfigurable computing module is adopted, dynamic allocation of computing units is supported, a multi-mode DPD function can be achieved on a single hardware platform, and redundant resource reservation is reduced; by selecting model item combinations according to gears, model item pruning can be achieved, parallel processing of combining an upper channel and a lower channel can be achieved, on the premise that linearization precision is guaranteed, calculation complexity and power consumption can be remarkably reduced, and therefore dynamic adaptation of PA nonlinear characteristics, efficient resource reuse, low delay and high energy efficiency are achieved.

The application discloses a Lamoeba chip architecture and a runtime reconstruction mechanism method based on an asynchronous mechanism, which combines an asynchronous reconfigurable Lamoeba chip and a reconstruction algorithm mechanism with time as a cost. The asynchronous mechanism provides a hardware basis for reconfigurable computing. The Lamoeba chip adopts a communication architecture of an on-chip mesh NoC to perform data transmission and communication on a network. The network adopts a 2D-mesh topology structure. Different types of computing modules are mounted in the network. In combination with a microprocessor in a single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of corresponding algorithms. The reconstruction algorithm calculates the data operation time, routing time and arbitration time of different paths in the network to find the shortest time allocation mode for algorithm mapping and change the deployment of the computing modules in the algorithm to the hardware resources. The application has the advantages of flexible general computing, high special computing, low power consumption without a clock and the ability to avoid various problems caused by the clock in the synchronous circuit.

A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a user program for execution on a reconfigurable dataflow computing system, comprising a grid of interconnected compute units and grid of memory units. The user program includes multiple tensor-based algebraic expressions that are converted to an intermediate representation comprising multiple stages. Each stage includes one or more logical operations executable via dataflow through compute units, and each stage is preceded by and followed by a stage buffer, each stage buffer corresponding to one or more memory units. The method includes detecting a final joining stage that consumes a first and second dataflow path, having a first and second total stage buffer depth, respectively, and balancing the first and second total stage buffer depths via tuning or inserting a whole stage buffer, wherein a total associated PMU cost is minimized.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. The detected compute graph node is partitioned into a compute subgraph corresponding to an RDP of the R interconnected RDPs. A first node is inserted into the compute subgraph that specifies a partial reduction operation for producing a partial reduction result corresponding to a shard of the first tensor and a shard of the second tensor. A second node is inserted for communicating the partial reduction result to an adjacent RDP. A third node is inserted that specifies a reduction operation for producing a total reduction result. A fourth node is inserted for communicating the total reduction result to at least one other RDP.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.