77 results about "Reconfigurable computing" patented technology

The invention discloses a configurable number-theory transformation parallel computing acceleration method and device for a post quantum cryptographic algorithm, and relates to the technical field of cryptographic algorithms. The number theory transformation is a calculation bottleneck in lattice-based post-quantum cryptography and PQC; a hardware accelerator specially designed for number theory transformation (NTT) is an effective solution for improving the execution speed. At present, a mainstream design neglects the influence of the scale of a calculation array, so that the design of an NTT calculation circuit is poor in flexibility and low in memory utilization rate, and a two-dimensional reconfigurable number theory transformation acceleration circuit is provided; the method is applied to a key generation stage, an encryption stage and a decryption stage of the post-quantum cryptographic algorithm. The NTT reconfigurable computing circuit provided by the invention can keep the utilization rate of hardware resources, and is suitable for mobile terminal equipment with limited resources; the NTT circuit adopts a low-complexity memory mapping scheme, so that the address control logic is greatly simplified, and the hardware overhead is reduced.

The invention discloses a high-speed hardware acceleration system for a Kyber anti-quantum cryptography algorithm and an implementation method, and relates to the technical field of hardware acceleration of the anti-quantum cryptography algorithm, the high-speed hardware acceleration system comprises a dynamic resource management and scheduling center, a reconfigurable NTT computing cluster unit, a streaming polynomial coefficient cache network and a runtime security scheduler; and the dynamic resource management and scheduling center is respectively connected with the reconfigurable NTT computing cluster unit, the streaming polynomial coefficient cache network and the runtime security scheduler. According to the high-speed hardware acceleration system for the Kyber anti-quantum cryptography algorithm and the implementation method, the overall operation throughput rate and the response speed of the system are effectively improved, idle loss caused by fixed resource allocation or data waiting is reduced, the flexible reconstruction and reuse capability of hardware resources is improved, and the implementation efficiency is improved. Therefore, the same set of physical unit can efficiently adapt to different core operation modes in the Kyber algorithm, and the hardware utilization efficiency is improved.

The invention relates to the technical field of industrial automation control and robots, in particular to a heterogeneous high-real-time multi-axis robot cooperative motion control system and method.The system comprises an SoC main control layer, an FPGA driving layer and a hardware interconnection layer, the SoC main control layer adopts a heterogeneous SoC chip, an ARM processor is responsible for track planning and task scheduling, an FPGA logic deployment reconfigurable PID calculation engine is responsible for FPGA logic deployment, and the FPGA driving layer is responsible for FPGA logic deployment. A multi-axis position ring and speed ring algorithm is realized through the time division multiplexing processing unit; the FPGA driving layer comprises a plurality of FPGA coprocessors, and an FOC current loop IP core is instantiated to execute bottom layer vector control related operation; the hardware interconnection layer adopts an EPPI protocol supporting topology awareness, dynamic bandwidth allocation and a ping-pong buffering mechanism, and efficient transmission of a control instruction and feedback data is achieved. Through hierarchical control and hardware collaborative design, the problems that an existing multi-axis control system is large in calculation delay, insufficient in synchronization precision and low in hardware resource utilization rate are effectively solved.

The invention relates to the technical field of vehicle-mounted computing, in particular to a dynamic energy efficiency management and emergency redundancy processing device and method for vehicle-mounted heterogeneous computing, and the device comprises a reconfigurable computing array which is used for carrying out dynamic partitioning and resource scheduling on an FPGA (Field Programmable Gate Array) logic unit; the multi-protocol converged communication panel is used for receiving a plurality of sensor data input into the reconfigurable computing array and carrying out mixed scheduling on the plurality of sensor data; the AI resource scheduling engine is used for redistributing computing power in the reconfigurable computing array according to the biological characteristics and a pre-constructed reinforcement learning dynamic energy efficiency model; and the three-level emergency redundant equipment is used for switching a main power supply, activating a preset optical calculation standby channel and starting V2X point cloud reconstruction when a main calculation unit in the reconfigurable calculation array breaks down so as to release nuclear explosion calculation power. Therefore, the problems of dynamic energy efficiency deficiency, redundancy mechanism insufficiency, multi-sensor conflict and the like of an existing vehicle-mounted computing system are solved.

According to the reconfigurable multiply-accumulate unit for the neural network processor and the processor, an efficient reconfigurable multiplier is constructed by organizing a large number of low-precision multiplication units. A peripheral reconfigurable computing circuit is designed to form a multiply-accumulate unit, so that the multiply-accumulate unit can flexibly support computing requirements of various precisions, various computing types and various data paths, and the compatibility and efficiency of hardware to a neural network are remarkably improved.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

The invention discloses a storage and calculation integrated architecture-based convolutional code parallel pipeline decoding acceleration system and method, and the system comprises a global data scheduling module which is used for slicing convolutional code data from magnetic tape storage equipment according to a set rule and carrying out the scheduling through a multi-stage cache mechanism; the storage and calculation integrated unit array is used for storing data tiles and intermediate results output by the global data scheduling module and executing convolution operation, path metric calculation and survival path selection through a reconfigurable calculation unit; the parallel pipeline controller is used for dynamically distributing decoding tasks and controlling the pipeline rhythm of the storage and calculation integrated unit array; the self-adaptive resource configuration module is used for monitoring system load in real time and dynamically adjusting a data distribution strategy and computing resource scheduling; the verification and error correction unit is used for performing verification and error correction on the decoding result output by the storage and calculation integrated unit array and then outputting the decoding result; according to the decoding acceleration system and method, high-efficiency and low-delay convolutional code decoding is realized.

The invention discloses a coarse-grained reconfigurable architecture cyclic mapping method and device based on a graph neural network, and relates to the technical field of computer reconfigurable computing. The method comprises the following steps: based on a priority prediction model, performing list scheduling according to a data flow diagram and hardware information to obtain a list scheduling table; performing modular scheduling according to the data flow diagram and the hardware information; pre-scheduling the data flow diagram on the basis of a list scheduling table according to the modular data flow diagram and the time extension coarse-grained array to obtain a time step attribute data flow diagram; obtaining a mapping result by using a mapping algorithm based on pattern diagram matching according to the time step attribute data flow diagram on the basis of the time extension coarse-grained array; based on the hardware information, processing unit isomorphism verification is carried out according to the mapping result; and compiling the verified mapping result to obtain an executable configuration information file. The invention provides an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on a graph neural network.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. Executing the compute graph on the multiple RDPs.

A method and system for integrating buffer views into buffer access operations in reconfigurable computing environments. The method includes detecting, in a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The buffer view parameters are lowered into the tensor indexing expression, according to the buffer view indicator, to produce a modified tensor indexing expression. The buffer view indicator is removed from a buffer allocation statement to produce a modified buffer allocation statement and allocating a buffer according to the modified buffer allocation statement. The system implements the described method and further includes a non-transitory computer readable medium for executing the disclosed method.

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

The application belongs to the field of information technology and provides a column reconfigurable systolic array for a Transformer model. The main idea is to realize that each column computing unit of the array can work together for a single operator or can be split to work individually for multiple operators. The main scheme includes a reconfigurable computing unit of a two-dimensional network, which is composed of row and column distributed computing units, data is transferred from the previous row to the next row and from the previous column to the next column; a register unit of a two-dimensional network, which is composed of row and column distributed register units, data is transferred from the previous row to the next row and from the previous column to the next column, and the data transfer direction is opposite to that of the reconfigurable computing unit of the two-dimensional network; and the register and the computing unit of the same row and column are connected through a data path. A mixed parallel line is supported to improve the hardware efficiency of the Transformer-based model.

The invention provides a digital pre-distortion method, circuit and system, and relates to the technical field of communication, and the digital pre-distortion circuit comprises an upper path and a lower path which are processed in parallel, and a reconfigurable calculation module. Through the reconfigurable digital pre-distortion circuit, real-time adjustment of nonlinear order, memory depth and model item combination can be realized, and different nonlinear characteristics of PA can be matched; a reconfigurable computing module is adopted, dynamic allocation of computing units is supported, a multi-mode DPD function can be achieved on a single hardware platform, and redundant resource reservation is reduced; by selecting model item combinations according to gears, model item pruning can be achieved, parallel processing of combining an upper channel and a lower channel can be achieved, on the premise that linearization precision is guaranteed, calculation complexity and power consumption can be remarkably reduced, and therefore dynamic adaptation of PA nonlinear characteristics, efficient resource reuse, low delay and high energy efficiency are achieved.

The application discloses a Lamoeba chip architecture and a runtime reconstruction mechanism method based on an asynchronous mechanism, which combines an asynchronous reconfigurable Lamoeba chip and a reconstruction algorithm mechanism with time as a cost. The asynchronous mechanism provides a hardware basis for reconfigurable computing. The Lamoeba chip adopts a communication architecture of an on-chip mesh NoC to perform data transmission and communication on a network. The network adopts a 2D-mesh topology structure. Different types of computing modules are mounted in the network. In combination with a microprocessor in a single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of corresponding algorithms. The reconstruction algorithm calculates the data operation time, routing time and arbitration time of different paths in the network to find the shortest time allocation mode for algorithm mapping and change the deployment of the computing modules in the algorithm to the hardware resources. The application has the advantages of flexible general computing, high special computing, low power consumption without a clock and the ability to avoid various problems caused by the clock in the synchronous circuit.

A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a user program for execution on a reconfigurable dataflow computing system, comprising a grid of interconnected compute units and grid of memory units. The user program includes multiple tensor-based algebraic expressions that are converted to an intermediate representation comprising multiple stages. Each stage includes one or more logical operations executable via dataflow through compute units, and each stage is preceded by and followed by a stage buffer, each stage buffer corresponding to one or more memory units. The method includes detecting a final joining stage that consumes a first and second dataflow path, having a first and second total stage buffer depth, respectively, and balancing the first and second total stage buffer depths via tuning or inserting a whole stage buffer, wherein a total associated PMU cost is minimized.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. The detected compute graph node is partitioned into a compute subgraph corresponding to an RDP of the R interconnected RDPs. A first node is inserted into the compute subgraph that specifies a partial reduction operation for producing a partial reduction result corresponding to a shard of the first tensor and a shard of the second tensor. A second node is inserted for communicating the partial reduction result to an adjacent RDP. A third node is inserted that specifies a reduction operation for producing a total reduction result. A fourth node is inserted for communicating the total reduction result to at least one other RDP.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

The application belongs to the technical field of face recognition, and discloses a real-time face recognition terminal based on edge computing and a fast matching method, which comprises a reconfigurable sensing front end, the output end of the reconfigurable sensing front end is connected with a reconfigurable computing array on a chip, the reconfigurable computing array on the chip is connected with a feature routing network on the chip; further comprising an environment perception unit, the output end of the environment perception unit is connected with a quality evaluation module, the output end of the quality evaluation module is connected with the feature routing network on the chip; further comprising a communication module, the communication module is connected with the reconfigurable computing array on the chip; further comprising a power management module. Through hardware dynamic on-demand reconfiguration and intelligent routing scheduling, combined with a two-level fast matching mechanism and a space-time context fingerprint, the application realizes the balance of high-precision recognition, fast response, low-power operation and anti-fake ability in a single system for the first time in a complex real scene.

The invention relates to a hybrid reconfigurable computing chip based on encryption and decryption computing and computer equipment. The method comprises the following steps: acquiring a first prime number and a second prime number, and determining a public key and an Euler function value according to the first prime number and the second prime number; the public key comprises a public key index and a modulus; performing linear operation in a private key calculation process by using the public key index and the Euler function value to obtain a first calculation result; outputting a first calculation result to a Boolean processor calculation core of a fine-grained reconfigurable architecture through a processing unit array data transmission unit and a Boolean processor array data transmission unit in sequence, so that the Boolean processor calculation core performs structured operation in a private key calculation process by using the first calculation result and an Euler function value, and a private key is obtained and output to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit in sequence. By adopting the method, the key calculation efficiency can be improved.

An integrated circuit (IC) includes an array of reconfigurable compute units organized into mutually exclusive groups. Each group includes no more than a reconfigurable number of reconfigurable compute units. Each compute unit includes group identifier circuitry and control circuitry configured to prevent the compute unit from starting to process data until a signal associated with a reconfigurable group identifier of the reconfigurable compute unit is received from the group identifier circuitry, where the reconfigurable group identifier identifies which group of the mutually exclusive groups the compute unit belongs to. According to operation of the group identifier circuitry and the control circuitry, no more than the reconfigurable number of the reconfigurable compute units are allowed to start processing data concurrently to mitigate supply voltage deviation caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

The invention discloses a bio-electricity signal recognition model and a reconfigurable hardware accelerator thereof, which adopt a multi-view learning method to comprehensively extract feature information from a plurality of feature views of bio-electricity signal data, can more comprehensively capture various characteristics of signals, and improve the recognition accuracy of the bio-electricity signals. The method comprises the following steps: firstly, learning initial features of three views by adopting a deep neural network to extract deep features; secondly, the depth features of all the views are fused to form a unified multi-view feature representation; and finally, inputting the fused multi-view features into a multi-layer perceptron for further feature learning to obtain a classification result, and finally completing the classification decision of the bio-electricity signals. A reconfigurable computing array is integrated in the reconfigurable hardware accelerator, dynamic multiplexing of hardware resources can be achieved through a time division multiplexing mechanism, a fast Fourier transform computing mode or a neural network reasoning computing mode is dynamically configured according to needs at different computing stages, and extra computing resources do not need to be introduced. Through the reconfigurable design, the overall area of the accelerator is reduced, and the utilization rate of computing resources is improved; data interaction is carried out among the modules through the data interfaces, instruction transmission is completed through the instruction interfaces, flexible reconstruction can be achieved, and it is ensured that in a bio-electricity signal processing task, different calculation stages are efficiently executed.

The application discloses a wafer-level chip, a chip system, an electronic device and a communication method, and relates to the technical field of integrated circuits. The wafer-level chip comprises a reconfigurable computing wafer, a cache storage wafer and an interconnection communication wafer which are stacked in sequence, and adjacent wafers are directly bonded wafer-to-wafer; the interconnection communication wafer comprises a photonic logic circuit, the cache storage wafer comprises an optical communication cache unit, and the optical communication cache unit is bonded with the photonic logic circuit; the optical communication cache unit caches data packets to be sent written by the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be sent from the optical communication cache unit and converts the data packets to optical signals and sends out the optical signals; and / or the photonic logic circuit receives optical signals and converts the optical signals to electrical signals and writes the electrical signals into the optical communication cache unit; the optical communication cache unit caches the electrical signals and informs the reconfigurable computing wafer to read the electrical signals.

The invention discloses an FPGA-based neural network acceleration method and system, and the method specifically comprises the steps: S1, carrying out the adaptive processing of input data, and converting original data into standardized feature data; s2, performing neural network model hardware mapping, and generating configuration parameters of the FPGA reconfigurable computing array; s3, parallel computing scheduling is carried out; s4, performing multi-level storage optimization; s5, integrating and outputting results, summarizing operation results of all the calculation units, executing interlayer data standardization processing, generating a current network layer output feature map, repeating the steps S3-S4 until all network layer operations are completed, and finally outputting a neural network reasoning result; dynamic energy efficiency adjustment is further included, and overall power consumption is reduced; the method has the advantages of multi-model adaptation, high calculation efficiency, low storage cost, high energy efficiency ratio and flexible precision, can be popularized on a large scale in scenes of edge calculation, automatic driving, intelligent security and protection and the like, and has practical application value and potential of nationwide multi-scene large-scale popularization.

The application relates to the technical field of computers and discloses an intelligent chip reconfigurable computing system based on FPGA, aiming to solve the inherent contradiction between the flexibility of FPGA configuration and the computing efficiency in the prior art. The system comprises: a configuration management module for receiving task scheduling instructions and generating a configuration parameter set containing computing core mapping parameters, data flow routing parameters and storage access parameters; a reconfigurable computing array composed of a plurality of dynamically configurable computing units; an intelligent resource scheduling engine for real-time monitoring of the operating state, adaptive resource allocation based on machine learning prediction analysis and dynamic programming scheduling; and a high-speed data interconnection network supporting multi-channel parallel data transmission. The application realizes dynamic optimal configuration of hardware resources, breaks through the limitations of traditional FPGA static configuration, significantly improves the computing efficiency and resource utilization of the system, effectively reduces the power consumption of the system, and can be widely applied in the fields of artificial intelligence reasoning, signal processing and the like.

The present invention discloses a real-time reconfigurable universal memristor simulation circuit. The memristor mathematical model is nonlinearly fitted using an m-term polynomial, where m is related to the amplitude and frequency of the input signal and the fitting accuracy. This allows for simple and rapid adaptation to a specified memristor model. Based on this, a system state variable generation module is constructed based on an FPGA for the system state variable, namely, magnetic flux or charge. A calculation module is used to calculate the polynomial coefficients and the system state variable in an m-stage pipeline mode in a reconfigurable manner to obtain a memristor value or a memristor value. A delay FIFO is used to delay the input signal x[n] by 3m clock cycles. An output module is used to multiply the input signal after the FIFO delay of 3m clock cycles by the memristor value or memristor value output by the calculation module to obtain an output signal, namely, a current signal or a voltage signal. By changing the polynomial coefficients, the memristor can be reconfigured in real time, thereby achieving the invention purpose of real-time reconfiguration to adapt to different memristor models. High-operating-frequency memristors can also be simulated. Simultaneously, digital circuits are used for reconstruction simulation, improving experimental accuracy.

The invention discloses a robot vision edge computing system and a computing method thereof. The system comprises a sensing layer, a reconfigurable computing platform and a robot decision-making layer, the reconfigurable computing platform comprises: an input adaptation and buffer module, which is used for receiving a multi-source sensing data stream of a sensing layer and carrying out hardware-level timestamp synchronization and format unification; the dynamic scheduler is used for receiving a mode instruction from a robot decision-making layer and generating a hardware control signal according to the mode instruction so as to control a switching path of a multi-source sensing data stream and distribute computing resources in the platform; the algorithm container loading and executing unit is used for loading and operating the algorithm container; and the time slice scheduler is activated and controlled by the dynamic scheduler and is used for periodically switching the algorithm containers running in the algorithm container loading and executing unit at a fixed time slice on the hardware level. The invention further comprises a calculation method of the robot vision edge calculation system. According to the invention, deterministic scheduling and efficient multiplexing of computing resources can be realized.

The invention discloses an auxiliary driving data decomposition method and system for a reconfigurable TPU computing device, and belongs to the technical field of electric digital data processing. The method comprises the steps of determining a preliminary decomposition parameter according to data attribute information of training aided driving data and operator combination information of an aided driving module deployed on a reconfigurable TPU computing device; the training auxiliary driving data are decomposed according to the preliminary decomposition parameters to obtain a preliminary decomposition result, and the reconfigurable TPU computing device is dynamically reconstructed based on the preliminary decomposition parameters; inputting the preliminary decomposition result into an auxiliary driving module, and collecting resource state information of the reconfigurable TPU computing device; and performing iterative optimization on the initial decomposition parameter according to the resource state information to obtain a target decomposition parameter. According to the technical scheme, self-adaptive and efficient data decomposition accurately matched with data characteristics and reasoning requirements is achieved, computing power optimization and resource dynamic adaptation are achieved, and reasoning efficiency and precision are remarkably improved.

A system for testing the firmware of a microcontroller (5) for an embedded system (7) is presented and claimed, comprising an interface (31) and a test environment. The test environment (39) includes a real-time capable reconfigurable computing system (35) and a non-real-time capable microprocessor-based computing system (37). The test environment (39) can simulate a response of a target system for which the microcontroller (5) is intended and / or of at least one component connected to the target system to the reception of signals from the microcontroller (5) in order to send responses to the received signals, based on the simulated response, to the microcontroller (5) via the counterparts (41a, 41b, ..., 41n). Furthermore, a use of the system and a method for testing the firmware of a microcontroller (5) for an embedded system (7) are described and claimed.

The application discloses a data processing method and device based on reconfigurable computing, equipment and a storage medium, wherein the method comprises the following steps: putting a task node of a current to-be-processed task into a to-be-scheduled task node table; performing cluster division on the task nodes in the to-be-scheduled task node table to obtain K clusters, wherein K is a positive integer; and mapping the K clusters to reconfigurable processing units respectively to process the current to-be-processed task in parallel. The technical scheme provided by the application can improve the utilization rate of redundant units in the reconfigurable computing module, and further improve the data processing efficiency.