48 results about "Reconfigurable computing" patented technology

The invention discloses a high-speed hardware acceleration system for a Kyber anti-quantum cryptography algorithm and an implementation method, and relates to the technical field of hardware acceleration of the anti-quantum cryptography algorithm, the high-speed hardware acceleration system comprises a dynamic resource management and scheduling center, a reconfigurable NTT computing cluster unit, a streaming polynomial coefficient cache network and a runtime security scheduler; and the dynamic resource management and scheduling center is respectively connected with the reconfigurable NTT computing cluster unit, the streaming polynomial coefficient cache network and the runtime security scheduler. According to the high-speed hardware acceleration system for the Kyber anti-quantum cryptography algorithm and the implementation method, the overall operation throughput rate and the response speed of the system are effectively improved, idle loss caused by fixed resource allocation or data waiting is reduced, the flexible reconstruction and reuse capability of hardware resources is improved, and the implementation efficiency is improved. Therefore, the same set of physical unit can efficiently adapt to different core operation modes in the Kyber algorithm, and the hardware utilization efficiency is improved.

The invention relates to the technical field of industrial automation control and robots, in particular to a heterogeneous high-real-time multi-axis robot cooperative motion control system and method.The system comprises an SoC main control layer, an FPGA driving layer and a hardware interconnection layer, the SoC main control layer adopts a heterogeneous SoC chip, an ARM processor is responsible for track planning and task scheduling, an FPGA logic deployment reconfigurable PID calculation engine is responsible for FPGA logic deployment, and the FPGA driving layer is responsible for FPGA logic deployment. A multi-axis position ring and speed ring algorithm is realized through the time division multiplexing processing unit; the FPGA driving layer comprises a plurality of FPGA coprocessors, and an FOC current loop IP core is instantiated to execute bottom layer vector control related operation; the hardware interconnection layer adopts an EPPI protocol supporting topology awareness, dynamic bandwidth allocation and a ping-pong buffering mechanism, and efficient transmission of a control instruction and feedback data is achieved. Through hierarchical control and hardware collaborative design, the problems that an existing multi-axis control system is large in calculation delay, insufficient in synchronization precision and low in hardware resource utilization rate are effectively solved.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

The invention discloses a coarse-grained reconfigurable architecture cyclic mapping method and device based on a graph neural network, and relates to the technical field of computer reconfigurable computing. The method comprises the following steps: based on a priority prediction model, performing list scheduling according to a data flow diagram and hardware information to obtain a list scheduling table; performing modular scheduling according to the data flow diagram and the hardware information; pre-scheduling the data flow diagram on the basis of a list scheduling table according to the modular data flow diagram and the time extension coarse-grained array to obtain a time step attribute data flow diagram; obtaining a mapping result by using a mapping algorithm based on pattern diagram matching according to the time step attribute data flow diagram on the basis of the time extension coarse-grained array; based on the hardware information, processing unit isomorphism verification is carried out according to the mapping result; and compiling the verified mapping result to obtain an executable configuration information file. The invention provides an efficient and accurate coarse-grained reconfigurable architecture cyclic mapping method based on a graph neural network.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. Executing the compute graph on the multiple RDPs.

The application belongs to the field of information technology and provides a column reconfigurable systolic array for a Transformer model. The main idea is to realize that each column computing unit of the array can work together for a single operator or can be split to work individually for multiple operators. The main scheme includes a reconfigurable computing unit of a two-dimensional network, which is composed of row and column distributed computing units, data is transferred from the previous row to the next row and from the previous column to the next column; a register unit of a two-dimensional network, which is composed of row and column distributed register units, data is transferred from the previous row to the next row and from the previous column to the next column, and the data transfer direction is opposite to that of the reconfigurable computing unit of the two-dimensional network; and the register and the computing unit of the same row and column are connected through a data path. A mixed parallel line is supported to improve the hardware efficiency of the Transformer-based model.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

A method for a reconfigurable computing system includes receiving a compute graph for execution on multiple RDPs interconnected with a ring network having R interconnected RDPs. A compute graph with a node specifying a reduction operation for a first and second tensor is detected. The detected compute graph node is partitioned into a compute subgraph corresponding to an RDP of the R interconnected RDPs. A first node is inserted into the compute subgraph that specifies a partial reduction operation for producing a partial reduction result corresponding to a shard of the first tensor and a shard of the second tensor. A second node is inserted for communicating the partial reduction result to an adjacent RDP. A third node is inserted that specifies a reduction operation for producing a total reduction result. A fourth node is inserted for communicating the total reduction result to at least one other RDP.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

The application belongs to the technical field of face recognition, and discloses a real-time face recognition terminal based on edge computing and a fast matching method, which comprises a reconfigurable sensing front end, the output end of the reconfigurable sensing front end is connected with a reconfigurable computing array on a chip, the reconfigurable computing array on the chip is connected with a feature routing network on the chip; further comprising an environment perception unit, the output end of the environment perception unit is connected with a quality evaluation module, the output end of the quality evaluation module is connected with the feature routing network on the chip; further comprising a communication module, the communication module is connected with the reconfigurable computing array on the chip; further comprising a power management module. Through hardware dynamic on-demand reconfiguration and intelligent routing scheduling, combined with a two-level fast matching mechanism and a space-time context fingerprint, the application realizes the balance of high-precision recognition, fast response, low-power operation and anti-fake ability in a single system for the first time in a complex real scene.

The invention discloses a bio-electricity signal recognition model and a reconfigurable hardware accelerator thereof, which adopt a multi-view learning method to comprehensively extract feature information from a plurality of feature views of bio-electricity signal data, can more comprehensively capture various characteristics of signals, and improve the recognition accuracy of the bio-electricity signals. The method comprises the following steps: firstly, learning initial features of three views by adopting a deep neural network to extract deep features; secondly, the depth features of all the views are fused to form a unified multi-view feature representation; and finally, inputting the fused multi-view features into a multi-layer perceptron for further feature learning to obtain a classification result, and finally completing the classification decision of the bio-electricity signals. A reconfigurable computing array is integrated in the reconfigurable hardware accelerator, dynamic multiplexing of hardware resources can be achieved through a time division multiplexing mechanism, a fast Fourier transform computing mode or a neural network reasoning computing mode is dynamically configured according to needs at different computing stages, and extra computing resources do not need to be introduced. Through the reconfigurable design, the overall area of the accelerator is reduced, and the utilization rate of computing resources is improved; data interaction is carried out among the modules through the data interfaces, instruction transmission is completed through the instruction interfaces, flexible reconstruction can be achieved, and it is ensured that in a bio-electricity signal processing task, different calculation stages are efficiently executed.

The application discloses a wafer-level chip, a chip system, an electronic device and a communication method, and relates to the technical field of integrated circuits. The wafer-level chip comprises a reconfigurable computing wafer, a cache storage wafer and an interconnection communication wafer which are stacked in sequence, and adjacent wafers are directly bonded wafer-to-wafer; the interconnection communication wafer comprises a photonic logic circuit, the cache storage wafer comprises an optical communication cache unit, and the optical communication cache unit is bonded with the photonic logic circuit; the optical communication cache unit caches data packets to be sent written by the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be sent from the optical communication cache unit and converts the data packets to optical signals and sends out the optical signals; and / or the photonic logic circuit receives optical signals and converts the optical signals to electrical signals and writes the electrical signals into the optical communication cache unit; the optical communication cache unit caches the electrical signals and informs the reconfigurable computing wafer to read the electrical signals.

The invention discloses an FPGA-based neural network acceleration method and system, and the method specifically comprises the steps: S1, carrying out the adaptive processing of input data, and converting original data into standardized feature data; s2, performing neural network model hardware mapping, and generating configuration parameters of the FPGA reconfigurable computing array; s3, parallel computing scheduling is carried out; s4, performing multi-level storage optimization; s5, integrating and outputting results, summarizing operation results of all the calculation units, executing interlayer data standardization processing, generating a current network layer output feature map, repeating the steps S3-S4 until all network layer operations are completed, and finally outputting a neural network reasoning result; dynamic energy efficiency adjustment is further included, and overall power consumption is reduced; the method has the advantages of multi-model adaptation, high calculation efficiency, low storage cost, high energy efficiency ratio and flexible precision, can be popularized on a large scale in scenes of edge calculation, automatic driving, intelligent security and protection and the like, and has practical application value and potential of nationwide multi-scene large-scale popularization.

The application relates to the technical field of computers and discloses an intelligent chip reconfigurable computing system based on FPGA, aiming to solve the inherent contradiction between the flexibility of FPGA configuration and the computing efficiency in the prior art. The system comprises: a configuration management module for receiving task scheduling instructions and generating a configuration parameter set containing computing core mapping parameters, data flow routing parameters and storage access parameters; a reconfigurable computing array composed of a plurality of dynamically configurable computing units; an intelligent resource scheduling engine for real-time monitoring of the operating state, adaptive resource allocation based on machine learning prediction analysis and dynamic programming scheduling; and a high-speed data interconnection network supporting multi-channel parallel data transmission. The application realizes dynamic optimal configuration of hardware resources, breaks through the limitations of traditional FPGA static configuration, significantly improves the computing efficiency and resource utilization of the system, effectively reduces the power consumption of the system, and can be widely applied in the fields of artificial intelligence reasoning, signal processing and the like.

The invention discloses a robot vision edge computing system and a computing method thereof. The system comprises a sensing layer, a reconfigurable computing platform and a robot decision-making layer, the reconfigurable computing platform comprises: an input adaptation and buffer module, which is used for receiving a multi-source sensing data stream of a sensing layer and carrying out hardware-level timestamp synchronization and format unification; the dynamic scheduler is used for receiving a mode instruction from a robot decision-making layer and generating a hardware control signal according to the mode instruction so as to control a switching path of a multi-source sensing data stream and distribute computing resources in the platform; the algorithm container loading and executing unit is used for loading and operating the algorithm container; and the time slice scheduler is activated and controlled by the dynamic scheduler and is used for periodically switching the algorithm containers running in the algorithm container loading and executing unit at a fixed time slice on the hardware level. The invention further comprises a calculation method of the robot vision edge calculation system. According to the invention, deterministic scheduling and efficient multiplexing of computing resources can be realized.

The invention discloses an auxiliary driving data decomposition method and system for a reconfigurable TPU computing device, and belongs to the technical field of electric digital data processing. The method comprises the steps of determining a preliminary decomposition parameter according to data attribute information of training aided driving data and operator combination information of an aided driving module deployed on a reconfigurable TPU computing device; the training auxiliary driving data are decomposed according to the preliminary decomposition parameters to obtain a preliminary decomposition result, and the reconfigurable TPU computing device is dynamically reconstructed based on the preliminary decomposition parameters; inputting the preliminary decomposition result into an auxiliary driving module, and collecting resource state information of the reconfigurable TPU computing device; and performing iterative optimization on the initial decomposition parameter according to the resource state information to obtain a target decomposition parameter. According to the technical scheme, self-adaptive and efficient data decomposition accurately matched with data characteristics and reasoning requirements is achieved, computing power optimization and resource dynamic adaptation are achieved, and reasoning efficiency and precision are remarkably improved.

A system for testing the firmware of a microcontroller (5) for an embedded system (7) is presented and claimed, comprising an interface (31) and a test environment. The test environment (39) includes a real-time capable reconfigurable computing system (35) and a non-real-time capable microprocessor-based computing system (37). The test environment (39) can simulate a response of a target system for which the microcontroller (5) is intended and / or of at least one component connected to the target system to the reception of signals from the microcontroller (5) in order to send responses to the received signals, based on the simulated response, to the microcontroller (5) via the counterparts (41a, 41b, ..., 41n). Furthermore, a use of the system and a method for testing the firmware of a microcontroller (5) for an embedded system (7) are described and claimed.

The application discloses a data processing method and device based on reconfigurable computing, equipment and a storage medium, wherein the method comprises the following steps: putting a task node of a current to-be-processed task into a to-be-scheduled task node table; performing cluster division on the task nodes in the to-be-scheduled task node table to obtain K clusters, wherein K is a positive integer; and mapping the K clusters to reconfigurable processing units respectively to process the current to-be-processed task in parallel. The technical scheme provided by the application can improve the utilization rate of redundant units in the reconfigurable computing module, and further improve the data processing efficiency.

The invention provides a high-reliability multi-data flow diagram execution device, which is characterized in that a proxy distribution module is used for storing a pre-generated data flow diagram pool when a current program is executed, and a plurality of data flow diagrams in the data flow diagram pool are loaded to a reconfigurable array in parallel under the control of a feedback control module; when the data flow diagram is wrongly calculated, other data flow diagrams which belong to the same program with the data flow diagram which is wrongly calculated are scheduled; the reconfigurable computing array is used for executing a plurality of heterogeneous data flow diagrams corresponding to the same to-be-executed program in parallel; the strategy judgment module is used for judging whether calculation is correct or not, outputting a result when the calculation is correct, marking a data flow diagram of a calculation error when the calculation result is wrong, and feeding back the data flow diagram to the reconfigurable calculation array and the feedback control module; and the feedback control module is used for controlling the operation of the whole device and sending the received feedback information to the proxy distribution module so as to control the proxy distribution module to schedule and calculate other data flow diagrams, belonging to the same program, of the wrong data flow diagrams in the diagram pool.

A system for computing comprising: a reconfigurable computing device, comprising: a lockable circuitry comprising: reconfigurable data routing junctions, each having a configuration interface and an internal configuration; a lock controller, connected to each of the reconfigurable data routing junctions; and a hardware lock bit; wherein the lock controller is configured to deliver a persistent lock signal to each of the reconfigurable data routing junctions when the hardware lock bit is in a locked state; wherein the hardware lock bit is transitioned from the locked state to an unlocked state only by a power cycle of the reconfigurable computing device; and wherein each reconfigurable data routing junction is configured to, in response to assertion of the persistent lock signal: lock the reconfigurable data routing junction's internal configuration; and decline to modify the internal configuration in response to one or more configuration signals received via the configuration interface.

The invention relates to a hybrid granularity reconfigurable computing system. The system comprises a fine granularity processing unit, a coarse granularity processing unit, a multi-layer control flow path and a multi-layer initialization flow path. The coarse granularity processing unit is used for decoupling the control flow information into coarse granularity control flow information and fine granularity control flow information, and performing coarse granularity processing on the coarse granularity control flow information; the coarse granularity processing unit is also used for decoupling the initialization stream information into coarse granularity initialization stream information and fine granularity initialization stream information, and performing coarse granularity processing on the coarse granularity initialization stream information; and the fine-grained processing unit is used for receiving fine-grained control flow information through the control flow path, receiving fine-grained initialization flow information through the initialization flow path, and performing fine-grained processing on the fine-grained control flow information and the fine-grained initialization flow information respectively. By adopting the method, the calculation efficiency can be improved.

The application discloses a face recognition method, a face recognition device, an embedded device and a nonvolatile computer readable storage medium. The face recognition method comprises the following steps: detecting face information in a collected image to generate a face image; detecting the quality of the face image based on a preset face screening model; and calculating the similarity between a face feature vector of the face image and a preset face feature vector based on a reconfigurable computing unit, so as to perform face recognition. The face recognition method, the face recognition device, the embedded device and the nonvolatile computer readable storage medium can eliminate some face images with poor quality, thereby reducing the number of face images that need to be recognized, and improving the recognition efficiency. The reconfigurable computing unit can reduce the resource occupation rate and time consumption of the embedded device in the face recognition process, so as to meet the operation requirements of the embedded device in other work.

This invention provides a data scheduling method and neural network accelerator based on a reconfigurable computing array. The method includes: receiving a raw data stream and performing valid data detection on the raw data stream to generate a sparse mask sequence corresponding to the raw data stream. Valid data detection is used to remove invalid data from the raw data stream. Invalid data includes invalid padding data and / or zero values ​​or non-important data below a set threshold. Data scheduling is performed on the raw data stream based on the sparse mask sequence to obtain a valid data sequence in the raw data stream. The processing path of the valid data sequence on the reconfigurable computing array is determined based on the sparse mask sequence, and the valid data sequence is processed based on the processing path. This invention can eliminate computational power consumption for invalid data, reduce storage access, achieve zero-pause loading of irregular data streams, reduce inference latency, meet the high frame rate requirements of scenarios such as autonomous driving perception and real-time voice on the edge, and reduce power consumption.

A method for improving runtime performance and alleviating place and route issues in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor. The compute graph includes a node specifying a template-based operation on a first and second tensor having a shared batch dimension B. The node may be split into B nodes. Each of the template-based operations on the pair of tensors may be replace with a GeMM operation on the first reduced rank tensor slice and a tile. B nodes that specify the GeMM operation may be appended with at least one first addition node that accepts input from the B nodes to produce a first modified compute graph. The first modified compute graph may be executed. The method describes a significant improvement to overall compute utilization across gradient-sections. Spatial tiling of tensors facilitates gradient calculation without the use of accumulators.

The present disclosure proposes a reconfigurable computing imaging method, comprising determining corresponding target configuration parameters from a preset task configuration library based on a target imaging task, the target configuration parameters comprising a target encoding operator and a target electrical computing reconstruction algorithm; modeling a multi-dimensional light field as a mathematical function containing multiple dimensions; mapping the mathematical function corresponding to the multi-dimensional light field to a sensor through the target encoding operator to obtain a sensor sampling signal; and obtaining target light field information through the target electrical computing reconstruction algorithm based on the sensor sampling signal. Through the collaborative design of optical computing and electrical computing, the present disclosure constructs an imaging system with dynamic reconfigurable capability, realizes efficient light field information acquisition and reconstruction facing tasks and dynamically controllable, and solves the problems of flux bottleneck and system solidification.

The present disclosure relates to indexing external memory in a reconfigurable computing fabric. Various examples relate to systems and methods in which a stream controller of a first synchronous stream can receive an instruction to execute a first loop using the first synchronous stream. The stream controller can determine a first iteration index for a first iteration of the first loop. The stream controller can send a first synchronization message to a first compute element of the first synchronous stream to initiate a first synchronization stream thread for executing the first iteration of the first loop. The first synchronization message can include the iteration index. The first compute element can be capable of performing an input / output operation at a first location of a first compute element memory indicated by the first iteration index.

The application discloses a data flow driven reconfigurable processor chip and a reconfigurable processor cluster. The reconfigurable processor chip comprises a plurality of reconfigurable processing units based on distributed storage, and the components of the reconfigurable processing units are logically interconnected, wherein the components comprise a reconfigurable computing component for computing data, a data flow controller adopting a data flow driven mode, the data flow driven mode controls the start and end of computing and data transmission tasks according to data flow information of a computing task and message transmission of upstream and downstream reconfigurable processing units, a distributed storage for realizing data storage of the corresponding reconfigurable processing unit, and a programmable data routing unit for realizing communication between the plurality of reconfigurable processing units, for controlling the direction of data packets and realizing flexible data packet transmission.

The invention particularly relates to a dynamic congestion sensing hierarchical scheduling method and device based on reconfigurable computing, and the method comprises the steps: constructing a hierarchical tree-shaped scheduling structure, and mapping a node scheduling algorithm and a congestion algorithm to a reconfigurable computing module; performing congestion identification on the dequeued and enqueued queues based on a mapping congestion algorithm; when an enqueue application is received, the messages are classified according to a congestion detection result; calculating priority and sending time information of the dequeued application queue elements; queue elements are pushed into the scheduling sub-lists according to the priorities, ordered insertion of the priorities and sending time of the queue elements is completed in the sub-lists, the elements which meet the sending time and have the highest priorities are extracted, and the scheduling sub-lists and information of corresponding pointers are updated during pushing and extraction. According to the invention, dynamic adjustment of the scheduling strategy is supported, dynamic and efficient sharing of intelligent differential congestion control and computing resources is realized, and the scheduling efficiency of complex multi-service traffic in high-speed network equipment is improved.

The application provides a digital control oscillator for a reconfigurable computing array, comprising a configuration module connected with a Cordic operation array, an output control module and an output cache module, and used for setting configuration information of the Cordic operation array, configuration information of the output control module and configuration information of the output cache module; the Cordic operation array is connected with the output control module, and used for generating a down-converted signal according to the configuration information of the Cordic operation array, and sending the down-converted signal to the output control module; the output control module is connected with the output cache module, and used for outputting the down-converted signal to the output cache module according to the configuration information of the output control module; and the output cache module is used for outputting a quadrature signal based on the down-converted signal according to the configuration information of the output cache module. The application further provides a signal generation method and electronic equipment, which can improve the NCO performance and reduce the NCO energy consumption.

The invention belongs to the technical field of artificial intelligence chips and reconfigurable computing, and particularly relates to an event-driven asynchronous graph neural network FPGA accelerator for real-time edge vision. Aiming at the problems of low storage utilization rate, obvious data access bottleneck, limited degree of parallelism, too high calculation redundancy and the like of a traditional GNN accelerator in an event vision scene, the invention provides a novel architecture combining efficient graph feature storage, hierarchical graph construction and redundancy elimination convolution calculation. By introducing parallel read-write optimization, low-dependence graph structure generation and a reusable computing cache mechanism, the computing delay is remarkably reduced while resource consumption is kept controllable, the overall throughput rate is increased, and therefore the sub-microsecond real-time reasoning capacity is achieved. The method is suitable for unmanned driving, intelligent monitoring, robot navigation and other application scenes needing low-delay visual calculation on edge equipment.