Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system

Abstract

The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a linear operation part suitable for the parallel execution of all pixels in low-level and intermediate-level image processing; the RP array is used for operation suitable to be finished in a row parallel way or complex nonlinear operation in the low-level and intermediate-level processing; and particularly, the PE array can also be dynamically reconfigured into a two-dimensional self-organizing map (SOM) neural network with extremely low performance and area overhead, and the neural network can realize advanced image processing functions of high-speed parallel online training, feature recognition and the like with the coordination of RPs. The shortcoming that advanced image processing cannot be used for pixel level parallel RP arrays in the conventional programmable vision chip and the conventional parallel vision processor is completely overcome, and the implementation of a fully-functional, low-cost, low-power consumption, intelligent and portable high-speed real-time visual image system on chip is facilitated.

Description

technical field [0001] The invention relates to the field of visual image processing technologies such as programmable visual chips, parallel visual image processors, and artificial neural networks, and in particular to a neural network that can be dynamically reconfigured into a self-organizing map for feature extraction and feature recognition of high-speed visual images A dynamically reconfigurable multilevel parallel SIMD array processing system. Background technique [0002] A traditional visual image processing system includes a discrete camera and a general-purpose processor (or digital signal processor (DSP)). The camera uses an image sensor to acquire images, and uses software in the general-purpose processor or DSP to process the images. Since the processing of images by software in general-purpose processors or DSPs is often carried out serially pixel by pixel, there is a bottleneck of serial processing, so the traditional visual image system generally can only re...

AI Technical Summary

Problems solved by technology

[0005] 1) The pixel-level parallel image processing units in the pixel-level parallel image processing architecture are arranged in a two-dimensional array, which can realize full-pixel parallel local processing, but cannot achieve fast and flexible wide-area processing;

[0006] 2) The pixel-level parallel image processing architecture supports low-level image processing and some intermediate image processing, so it can realize image feature extraction at 1000 frames per second, but lacks advanced image processing functions, especially the simple and intuitive fast Therefore, it is still necessary to rely on an external general-purpose processor to form a complete visual image system, and this will again introduce a serial processing bottleneck, completely covering up the high-speed real-time performance obtained by the pixel-level parallel processing architecture in low-level image processing , so that the overall process of visual image processing (including image feature extraction and image feature recognition) still cannot meet the high-speed real-time requirements of 1000 frames per second

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