6 results about "Fat tree" patented technology

Techniques and architecture are described for a method that includes an in network compute (INC) manager receiving from switches of a fat tree configured network, arithmetic logic unit (ALU) capacity of the switches. Based at least in part on the ALU capacity of the switches and bandwidth, the INC manager determines one or more switches within each tier that are capable of supporting the processing units and based at least in part on the determining, the INC manager selects a first switch as a root, wherein the first switch is included within a tier of switches having intermediate tiers of switches located between the tier and the plurality of processing units within the fat tree configured network. The INC manager creates one or more paths of switches within each of the intermediate tiers from the root to the plurality of processing units to provide a constrained disjoint spanning tree of switches.

A network on chip for high performance computing includes a first fat-tree network topology that connects each of a number of initiator nodes to one of a number of initiator core switches through one or more levels of initiator edge switches. A second fat-tree network topology connects each of the target nodes to one of a number of target core switches through one or more levels of target edge switches, and the first fat-tree network topology is joined to the second fat-tree network topology through connections between the initiator core switches and the target core switches.

This invention discloses an adaptive optimization method for edge optical links in a data center based on deep reinforcement learning. Using a fixed fat-tree electrical switching plane as the underlying architecture, it achieves adaptive addition and deletion of direct optical links between edge switches through topology control (DQN) and optical path switching. The DQN and packet-by-packet routing (DQN) form a two-layer collaborative decision-making structure. This invention models the optical link addition / deletion decision as a constrained Markov decision process, employing a dynamic candidate set mechanism to construct a low-dimensional state and action space, significantly reducing model computational complexity and training overhead. Compared to a pure electrical fat-tree architecture, the provided dynamic candidate set DQN scheme effectively reduces average on-network latency, packet rejection rate, and maximum queue length under high-load scenarios. Under the same link resource constraints, the dynamic candidate set scheme outperforms the all-optical link pair scheme, exhibiting higher training efficiency, decision stability, and network scalability. This invention can adaptively sense traffic distribution and schedule optical link resources on demand, making it suitable for real-time control and performance optimization scenarios in high-dynamic and high-throughput hybrid optoelectronic data center network topologies.

The present invention discloses a method for tracing the physical path of data packets in a data center network with a fat-tree topology, which includes the following steps: Step 1) Assign specific tags to each switch node and Pod in the data center network, and perform specific configurations on the server node IPs; Step 2) Based on the assigned tags, deploy certain flow table entries to each switch node in the data center network to implement functions such as pushing tags into the packet header space; Step 3) When the data packet passes through the switch node, the switch performs corresponding operations based on the flow table matching entry of the data packet; at the client or server side, the final path information sequence in the packet header is split and parsed to restore the complete path of the data packet in the data center network. This method can effectively reduce the number of switch flow table entries and the packet header space, and completely restore the physical path of the data packet in the network, and can be used for functions such as quickly measuring the network traffic matrix and monitoring and locating network anomalies.

The invention provides a reconfigurable active interposer, an integrated chip and a configuration method thereof. The reconfigurable active intermediate layer is configured to be connected with a plurality of core particles and comprises a programmable internet network, a flash memory and a four-wire serial peripheral interface, the programmable internet network is based on a multi-layer 2D toroidal grid and fat tree mixed topology layout, and the programmable internet network is configured to dynamically adjust signal transmission of each core particle; the flash memory is connected with the programmable internet, and the flash memory is configured to store configuration data; the four-wire serial peripheral interface is configured to preload a configuration signal to the flash memory. According to the reconfigurable active interposer, dynamic path reconfiguration and selective wiring can be realized, the flexibility of network topology is improved, efficient multiplexing of the interposer is realized, and the configuration power consumption is reduced.

The embodiment of the application provides a kind of fat tree network topology and the method for sending routing request of thinning, wherein the relationship between the total number of the fat tree network topology and the total number of source node: the relationship between the number of the routing node of the first layer and the number of the routing node of the first layer: Wherein, it is the integer greater than or equal to 1. Through the application, the problem of low link utilization rate of high-level routing node in the related art is solved, and the effect of improving the link utilization rate of high-level routing node is achieved.