7 results about "Deadlock free" patented technology

The invention relates to the technical field of multi-vehicle cooperative control, and discloses a multi-AGV distributed cooperative path planning method and system, and the method comprises the steps: carrying out the task distribution based on the AGV state and position distance after receiving the order picking wave issuing; performing global path planning on the selected AGV, and determining continuous path points to be driven; the AGV dynamically blocks a front path point to form a temporary exclusive channel; detecting conflicts among the AGVs through a double conflict judgment mechanism based on timestamps and direction representation; if no conflict exists, the task is executed, and if the conflict exists, deadlock judgment is carried out firstly; if deadlock occurs, a heuristic avoidance strategy is adopted to search temporary obstacle avoidance points, and a path is re-planned through an A * algorithm in combination with a direction priority principle; and if the deadlock does not exist, directly carrying out path adjustment. According to the scheme, through dynamic blocking and double conflict judgment, waiting and collision are effectively reduced, and the passing efficiency and safety are improved; and in combination with a heuristic avoidance method based on a ternary search tree, the scheduling flexibility and intelligence of the system in a deadlock scene are enhanced.

Apparatuses and methods related to routing robots are provided. A route map of an environment including first and second robots can be received. The route map can be annotated with one-way lanes connecting conflict areas, where each lane ends to avoid blocking a conflict area. A first route and a second route used by the first and second robots, respectively, can be determined, where the first route and the second route each include a first lane connecting to a first conflict area. A first higher priority and a second lower priority can be assigned to the first and second robots, respectively. It can be determined that the second robot following the second route will block the first robot on the first lane. Based on the first priority being higher than the second priority, a computing device can alter the second route to prevent the second robot from blocking the first robot.

The application discloses an industry chain collaboration-oriented B-end transaction platform multi-subject permission intelligent management method, and relates to the technical field of data processing and access control. The subject cooperation strength and trust degree are embedded through a graph attention network, and a transient role and a minimum necessary permission boundary are dynamically generated in combination with context attributes. Fourier transform and a long short-term memory network are used to analyze the cooperation event time sequence, a continuous operation window is calculated, an accurate continuous period and an elastic buffer interval are formed, a cooperation relationship is matched in real time, multi-source termination signals are fused, a dynamic recovery threshold is generated through a deep Q network, the subject access range and downstream dependence are double-checked, a non-deadlock atomized revocation sequence is output, a recovery instruction is triggered through distributed clock synchronization, and the state is confirmed by comparing audit logs, and the permission deviation is quantified by using dynamic time warping and mutation point detection. The application realizes accurate permission matching, intelligent recovery and strategy self-evolution, and improves the security and efficiency of cross-enterprise cooperation.

A design tool is disclosed for generation and synthesis of the network, such as a network-on-chip (NoC). The design tool starts with a deadlock free network design and makes changes or transforms the design to generate a desired NoC, including addressing paths that cross clock domain bourndaries or have timing violations. The design tool considers intermediate and proximal regions during the insertion process of distance links, which eliminates distance violations resulting from clock and timing domain traversal by a path.

The invention relates to the technical field of network-on-chip of a multi-core processor, and discloses a cache coherence network-on-chip optimization method based on containeability and expected propagation, through three-stage optimization of ''containeability deadlock avoidance-containeability expected propagation-local load awareness routing'', and in combination with cache coherence protocol adaptation, the network-on-chip optimization of the cache coherence is realized. According to the technical scheme, the NoC performance in the virtual channel limited scene is improved, and the problem that in an existing technical scheme, in the virtual channel limited scene, a network-on-chip with no deadlock, high VC utilization rate and low load sensing overhead cannot be considered at the same time, and then the requirement of a cache consistency multi-core processor cannot be adapted is solved.

This invention relates to the field of chip design, and in particular to a compilation method, electronic device, and storage medium free from SIMT deadlock risk. The method involves the compiler inserting initialization code for a thread group scheduling queue at the beginning of the target source code, thus obtaining the thread group scheduling queue. This queue is used to rearrange the execution order of basic blocks during the execution of the target source code. Queue maintenance code is inserted at the end of each basic block. The maintenance steps of the thread group scheduling queue include: the processor executing the queue maintenance code inserted at the end of the i-th basic block; the queue maintenance code detecting the next target instruction to be executed and pushing the target instruction and the binary execution mask of the current thread group onto the tail of the thread group scheduling queue; and the dequeueing of the head instruction of the thread group scheduling queue, followed by processor execution of the dequeueed head instruction, thus resolving the deadlock problem.