Self-adaptive routing method of two-dimensional network-on-chip topological structure

A network-on-chip and topological structure technology, which is applied in the direction of data exchange network, architecture with a single central processing unit, general-purpose stored program computer, etc., can solve the problems of low hardware overhead, high throughput rate, low network delay, etc., and achieve delay reduction , Improve network throughput and improve network performance

Active Publication Date: 2015-09-09
XIDIAN UNIV
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Problems solved by technology

[0007] The purpose of the present invention is to overcome the above-mentioned deficiencies in the prior art, and solve the problem that the traditional two-dimensional network-on-chip network routing method cannot effectively avoid congested nodes or avoid congested nodes, resulting in low network performance due to large hardware overhead. Strong performance control capability, low hardware overhead, low network delay, and high throughput

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  • Self-adaptive routing method of two-dimensional network-on-chip topological structure
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  • Self-adaptive routing method of two-dimensional network-on-chip topological structure

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Embodiment Construction

[0055] The present invention will be further described below in conjunction with the accompanying drawings.

[0056] Refer to attached figure 1 The two-dimensional on-chip network topology on which the adaptive routing method of the present invention is based is further described.

[0057] The two-dimensional on-chip network topology structure includes routing nodes and flow controllers. In the m×n network, m≥2, n≥2, including m×n routing nodes and m+n-2 flow controllers; the m×n routing nodes are arranged into an m×n rectangular network; A flow controller is placed between every two adjacent rows of routing nodes in the m×n network; a flow controller is placed between every two adjacent columns of routing nodes in the m×n network; the routing node passes the data A bus connects adjacent flow controllers; where:

[0058] The routing node is used for receiving data packets and distributing the data packets, injecting the data packets from the local port into the adjacent flo...

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Abstract

The invention discloses a self-adaptive routing method of a two-dimensional network-on-chip topological structure, and is used for solving the problems that a conventional two-dimensional network-on-chip routing method cannot effectively avoid congestion nodes or hardware expenditure is large and efficiency is low and thereby causing low network performance when congestion nodes are avoided. The self-adaptive routing method adopts a method of combining injection direction selection and flow controller output port allocation. Specific steps of the self-adaptive routing method provided by the invention are as follows: 1. a local port of a source node receives a data packet; 2. the data packet is injected; 3. a flow controller receives the data packet; 4. a flow controller output port is allocated; 5. a routing node receives the data packet; 6. whether the routing node is a destination node is judged; 7. the routing node calculates an output port direction; and 8. the data packet is transmitted to a local output port of the destination node. The routing method is a self-adaptive routing method which has a good congestion control capability, is deadlock-free and is small in hardware expenditure.

Description

technical field [0001] The invention belongs to the technical field of electronic physics, and further relates to a congestion control routing method technology based on a two-dimensional on-chip network topology in the technical field of microelectronic integrated circuits. The adaptive routing method of the present invention includes three parts: local injection direction selection, routing node routing calculation, and flow controller output port selection. The adaptive routing method of the present invention can well avoid congested nodes, improve network throughput and Reduce network latency. Background technique [0002] Network-on-Chip (Network-on-Chip) draws on the idea of ​​computer network communication, replaces the traditional bus communication mode with routing and packet switching technology, realizes the separation of processing unit (IP core) and communication structure (network), and solves the problem of The three major problems inherent in the bus structu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/833H04L12/801G06F15/78H04L47/31
Inventor 史江义舒浩李钊马佩军王禛吴冰冰余文哲张春焱
Owner XIDIAN UNIV
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