Dynamic reconfigurable subnetting method and system based on network on chip

Abstract

The invention provides a dynamic reconfigurable subnetting method and system based on a network on a chip, wherein the method comprises the following steps: step S1, the network on chip is partitioned into a plurality of logic subnets according to the configuration information, wherein the logic subnets include processing units which are used right now; step S2, a plurality of physical subnets are constructed on the network on chip according to the logic subnets, wherein each physical subnet correspondingly comprises one logic subnet, and each physical subnet is a regular rectangular subnet; and step S3, a deadlock-free routing mode is adopted to realize the communication between every two routing nodes in the physical subnets. The method can be used for effectively supporting any upper-layer resource partition strategies, the utilization rate of resources on a chip is fully increased, finally, the utilization rate of computing resources in a many-core processor system is effectively increased, and the performance of the many-core processor is improved.

Description

technical field [0001] The invention relates to the technical field of computer architecture design, in particular to a method and system for dividing dynamically reconfigurable subnets based on an on-chip network. Background technique [0002] In the past ten years, the performance of microprocessors has been increasing at a rate of 60% per year. The improvement of performance is mainly due to the progress of integrated circuit manufacturing process and the continuous development of microprocessor architecture. The advancement of integrated circuit manufacturing technology provides a large number of resources on a single chip. How to effectively use the chip area to improve the performance and throughput of microprocessors has become an important issue in the study of microarchitecture. [0003] For many-core processor systems, on-chip communication has become a performance bottleneck. The reason is that with the continuous improvement of chip integration, the communicatio...

AI Technical Summary

Problems solved by technology

[0007] However, for on-chip networks, this method cannot meet the dynamic characteristics of the upper-layer resource division of on-chip networks. Therefore, a dynamically reconfigurable subnetwork division method based on on-chip networks is needed, which can effectively support the realization of arbitrary upper-layer resource division and fully improve on-chip resource utilization

Images