85results about How to "Reduce the amount of hardware" patented technology

An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments. As test requirements change, the test system can be reconfigured to contain other virtual instruments, eliminating or reducing the need to add instruments to meet changing test requirements. To ensure adequate performance of the test system, a proposed configuration may be simulated, and if a virtual instrument does not provide a required level of performance, the test system may be reconfigured.

A shared memory multiprocessor is provided which includes a plurality of nodes connected to one another. Each node includes: a main memory for storing data; a cache memory for storing a copy of data obtained from the main memory; and a CPU for accessing the main memory and the cache memory and processing data. The node further includes a directory and a memory region group. The directory is made up of directory entries each including one or more directory bits which each indicate whether the cache memory of another node stores a copy of a part of a memory region group of the main memory of this node. The memory region group includes of memory regions having the same memory address portion including a cache index portion. Each node is assigned to one of the one or more directory bits.

A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.

A data input apparatus that includes an image acquiring unit for acquiring the image of data displayed on the data display section of a measuring instrument, a number reading unit for reading numbers in the above described acquired image and a display unit for displaying the numbers read, with the above described image acquiring unit also acquiring the image of a portion other than the data display section of the above described measuring instrument at the same time, the image recognition unit reading information on the above described measuring instrument other than the above described numbers from the acquired image and the information on the read measuring instrument being used when the above described number reading unit reads numbers.

A method for detecting and correcting bit errors. The method includes the steps of receiving original data, partitioning the memory storage into a first portion and a second portion, storing the original data in the first portion of the memory buffer, modifying the original data into modified data, storing the modified data in the second portion of the memory buffer, comparing the original data with the modified data, combining the original data and the modified data to create a final data stream, and outputting the final data stream. The method may further include the step of calculating and storing parity data.

This is a data reproduction circuit for receiving data and reproducing the data and its clock which comprises an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical / protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel. However, by preallocating response-processing resources, response packets are accepted by the destination node. Thus, any resource conflicts which may occur are temporary (as the response packets which make forward progress are processable). Viewed in another way, response packets may be logically independent if the destination node is capable of processing the response packets upon receipt. Accordingly, a response virtual channel is formed to which each response packet belongs.

The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.

The present invention relates to an apparatus for determining a position of a first object (14) within a second object (13), wherein the first object (14) contacts the second object (13) at a contact region. The apparatus (1) comprises a provision unit (2) for providing a three-dimensional model (20) of the second object (13). A projection unit (5, 6, 7, 21) generates a two-dimensional projection image (26) of the first object (14) and of the second object (13), and a registration unit (8) registers the three-dimensional model (20) with the two-dimensional projection image (26). A determination unit (9) determines the position of the contact region from the position of the first object (14) on the two-dimensional projection image (26) and the registered three-dimensional model (20) of the second object (13), wherein the position of the contact region is the position of the first object (14) within the second object (13).

The invention discloses a method for determining the over-current of an inverter. The method comprises the steps that a current detection circuit detects the current of the inverter and sends a current detection result to a microprocessor; the microprocessor compares a detected current peak with a preset current threshold, stops normal outputting of sinusoidal pulse width modulation (SPWM) signals if the current peak is larger than or equal to the current threshold and outputs the SPWM signals equivalent to low-amplitude sinusoidal wave signals to the inverter; a voltage detection circuit detects the output voltage of the inverter and sends a voltage detection result to the microprocessor; and the microprocessor compares a detected voltage effective value with a preset voltage threshold and determines that the inverter is short-circuited if the voltage effective value is smaller than the voltage threshold, and the over-current occurs to the inverter due to impact loads. The invention further discloses a device for implementing the method. By means of the method and the device, whether the over-current of the inverter is caused by impact loads or short-circuit can be distinguished accurately.

The invention discloses a check system for a LabVIEW-based automobile instrument. The check system for the LabVIEW-based automobile instrument comprises an upper computer, a national instruments corporation PCI extensions for instrumentation-6624 (NIPXI-6624) board card, two NIPXI-6528 board cards, a programmable network resistor, a controller area network (CAN) communication board card, an NIPXI case, a serial port to universal serial bus (USB) data line and a LabVIEW human-computer interface software program. The upper computer communicates with the NIPXI case by the serial port to USB data line; the NIPXI board cards are inserted into corresponding slots in the NIPXI case; the NIPXI-6624 board card is respectively connected with a speedometer and a tachometer; one of the two NIPXI-6528 board cards is connected with a fuel meter and a water-thermometer by the programmable network resistor; the other NIPXI-6528 board card is connected with various switching value signal indicating lamps; the upper computer, the NIPXI board cards and various instruments communicate with the switching value signal indicating lamps by a CAN bus of the CAN communication board card; and the LabVIEW human-computer interface software program is a software platform of the check system. The portable automobile instrument check system is compact and flexible and is high in reliability, and the real-time feedback of automobile state information can be realized by aiming at different automobiles.

The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

A timestamp neural network comprised of sensor elements, internal elements, and motor elements is responsive to timestamps. Sensor elements transform a wide variety of signals into events that trigger the updating of timestamps. Internal elements are responsive to timestamps. Motor elements convert timestamps into useful output signals. A real time video pattern recognition system is implemented.

The invention relates to an eye sight-based password inputting method and a hardware device thereof. The hardware device comprises a shooting unit, a display unit and a processing unit. The eye sight-based password inputting method includes the steps of subjecting the shooting unit to shooting a facial image to form an integral numerical image, determining a target area containing eyes of the user by using Adaboosts to perform a traversal to the integral numerical image and a cascade detection, determining positions of pupil centers of the left and the right eyes and inner eye corner points in the target area, and determining specific positions of sight focuses on the display unit according to geometrical relationship to achieve password inputting. Compared with the prior art, the eye sight-based password inputting method is safer, more rapid and convenient, higher in inputting accuracy, simplified in the required hardware device and lower in cost.

A data transfer control circuit is connected between a first bus and a second bus. The first bus is connected with a first CPU and a first memory. The second bus is connected with a second CPU and a second memory. The data transfer control circuit includes a temporary memory and a control unit. The temporary memory is configured to temporarily stores a first address and a first write data which are outputted by the first CPU through the first bus. The control unit is configured to translate the first address into a second address in the second memory with reference to an address translation table. The control unit occupies the second bus to write the first write data to the second address in the second memory through the second bus, when the first CPU releases the first bus after outputting the first address and the first write data to the data transfer control circuit through the first bus.

A fault tolerant data processing system for controlling a real time process. The system is tolerant to systematic faults in its software. The system includes a data processor unit with a program memory and a data memory and input and output units where program software residing in the program memory can be executed on the data processor unit. The system includes a normal-mode software program residing in the program memory, and a backup-mode software program also residing in the program memory arranged to perform the same or similar function of the normal mode software program but being differently implemented than the normal-mode software program, and where a trigger signal received by the data processor unit can switch execution control such that the normal-mode software program stops executing and the backup-mode software program starts executing.

The invention belongs to the field of household appliances, and particularly provides a clothes processing device. The clothes processing device is aimed at solving the problem that an existing clothes washing machine can not dry clothes through a drying system of the clothes dryer. For the purpose, the clothes processing device comprises a clothes dryer, a clothes washing machine and a drying system. The drying system comprises a reversing device. The drying system can produce drying air flow. By switching the state of the reversing device, the drying air flow can be alternatively conveyed into the clothes dryer or the clothes washing machine. Thus, the clothes processing device can dry the clothes in the clothes dryer and the clothes washing machine through the drying system, and the useexperience of the user is improved.

The adaptive digital filter of the present invention includes: a filter unit that includes a plurality of multipliers (3360-336N-1) that are divided into groups of at least one multiplier and the other multipliers based on expected values of filter coefficients and that generates first signals by means of convolution operations of an input signal and filter coefficients; an adder (338) that adds the input signal that is applied to at least one multiplier (336M-1) and first signals and supplies the results as second signals; and coefficient control unit (318 and 3190-319N-1) that control filter coefficients based on error between a target signal and an index value derived from the second signals.

A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline. The pipeline controller may invalidate an entire thread of instructions, squeeze out invalid instructions, and / or conserve power by selectively stopping the clocking of pipestages.

A fault tolerant data processing system for controlling a real time process. The system is tolerant to systematic faults in its software. The system includes a data processor unit with a program memory and a data memory and input and output units where program software residing in the program memory can be executed on the data processor unit. The system includes a normal-mode software program residing in the program memory, and a backup-mode software program also residing in the program memory arranged to perform the same or similar function of the normal mode software program but being differently implemented than the normal-mode software program, and where a trigger signal received by the data processor unit can switch execution control such that the normal-mode software program stops executing and the backup-mode software program starts executing.

In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

The invention discloses a virtual stereoscopic vision-based non-cooperative target cooperative measuring method. The virtual stereoscopic vision-based non-cooperative target cooperative measuring method comprises following steps: three dimensional cloud of points of a non-cooperative tumbling target are obtained; the relative pose relation of a satellite nozzle center and an A-frame inscribed circle center is extracted; the obtained satellite nozzle and A-frame image are subjected to image pre-treatment processing; coordinate transition is carried out so as to obtain the pose relation at a specific coordinate system; the radius of the satellite nozzle and the A-frame inscribed circle are obtained, and the pose information of the nozzle and the A-frame center is obtained. The invention alsodiscloses a virtual stereoscopic vision-based non-cooperative target cooperative measuring system. The virtual stereoscopic vision-based non-cooperative target cooperative measuring method is capableof reducing the hardware numbers of the measuring system, improving the capacity of the measuring system, reducing sensor numbers, reducing space emission cost, expanding space measuring capacity, isrelatively high in calculation efficiency, and can be widely used in the technical field of space non-cooperative satellite vision measuring.

Systems and methods for the implementation of more efficient cache locking mechanisms are disclosed. These systems and methods may alleviate the need to present both a virtual address (VA) and a physical address (PA) to a cache mechanism. A translation table is utilized to store both the address and the locking information associated with a virtual address, and this locking information is passed to the cache along with the address of the data. The cache can then lock data based on this information. Additionally, this locking information may be used to override the replacement mechanism used with the cache, thus keeping locked data in the cache. The translation table may also store translation table lock information such that entries in the translation table are locked as well.

An apparatus and method to condition the fuser surface of a fusing or transfusing apparatus for a toner based printing system is described. The apparatus and method integrate the functions of cleaning paper debris and residual toner from the fuser (or transfuse) surface on one hand and the application of a release agent such as silicone oil on the other hand using a single release agent impregnated web. The inventive device includes a release agent application roller and a cleaning roller where the outer surfaces and are selected in preferred embodiments for their respective wetting properties with respect to the release agent used. The fuser surface conditioning device increases the useful life for a fusing or transfusing roll or belt even when low amounts of release agent are applied to the fusing surface such that the amount of release agent that is transferred to the print media is in the range of 0.5 to 5 mg / A4 sheet.