Network interface adapter with shared data send resources

Abstract

A network interface adapter includes an outgoing packet generator, adapted to generate an outgoing request packet for delivery to a remote responder responsive to a request submitted by a host processor and a network output port, coupled to transmit the outgoing request packet over a network to the remote responder. A network input port receives an incoming response packet from the remote responder, in response to the outgoing request packet sent thereto, as well as an incoming request packet sent by a remote requester. An incoming packet processor receives and processes both the incoming response packet and the incoming request packet, and causes the outgoing packet generator, responsive to the incoming request packet, to generate, in addition to the outgoing request packet, an outgoing response packet for transmission to the remote requester.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Divisional of U.S. patent application Ser. No. 10 / 000,456 filed Dec. 4, 2001, which claims benefit of U.S. Provisional Application No. 60,238,018 filed Apr. 11, 2001.FIELD OF THE INVENTION [0002] The present invention relates generally to digital network communications, and specifically to remote direct memory access (RDMA) to data over a digital network. BACKGROUND OF THE INVENTION [0003] The computer industry is moving toward fast, packetized, serial input / output (I / O) bus architectures, in which computing hosts and peripherals are linked by a switching network, commonly referred to as a switching fabric. A number of architectures of this type have been proposed, culminating in the “InfiniBand™” (IB) architecture, which has been advanced by a consortium led by a group of industry leaders (including Intel, Sun Microsystems, Hewlett Packard, IBM, Compaq, Dell and Microsoft). The IB architecture is described in detai...

AI Technical Summary

Benefits of technology

[0009] It is a further object of some aspects of the present invention to provide a HCA that performs RDMA read and write operations efficiently, with reduced hardware requirements relative to devices known in the art.

[0010] It is still a further object of some aspects of the present invention to provide a HCA capable of handling a substantially unrestricted number of outstanding RDMA read requests.

[0013] The novel architecture of the present invention reduces markedly the amount of hardware required to implement the HCA, since the scatter and gather engines are shared by the requester and responder functions, rather than having a separate scatter and gather engine for each function as in devices known in the art. The overall design of the HCA is thus simplified, since only a single data flow path must be implemented. Furthermore, because the HCA uses the same resources to handle both the requester and responder flows, it inherently allocates the resources dynamically in response to load variations between local and remote requests, so that the efficiency of the HCA is enhanced.

[0014] A further advantage realized in some preferred embodiments of the present invention is that there is substantially no restriction placed on the number of outstanding RDMA read requests from remote requesters that the HCA can handle. This advantage stems from the use of the local memory to hold quasi-WQEs indicating the RDMA read responses to be sent by the HCA. Each quasi-WQE corresponds to an outstanding RDMA read request. Consequently, the number of outstanding RDMA read requests is limited not by the small, costly memory of the HCA chip, but only by the considerably larger size of the available memory allocated for this purpose off the HCA chip (either host memory or dedicated off-chip memory).

[0028] Preferably, the incoming packet processor is configured so that when it receives an incoming write request packet containing write data to be written to a system memory accessible via the host interface after receiving the incoming read request packet, it conveys the write data to the host interface without waiting for execution of the read response work item. Additionally or alternatively, the incoming packet processor is configured so that when it receives an incoming write request packet containing write data to be written to a system memory accessible via the host interface before receiving the incoming read request packet, it prevents execution of the read response work item until the write data have been written to the system memory.

[0051] coupling the incoming packet processor to the outgoing packet generator so as to cause the outgoing packet generator to generate, responsive to the incoming request packet, in addition to the outgoing request packet, an outgoing response packet for transmission via the network to the remote requester.

Problems solved by technology

The need for this restriction stems from the fact that each outstanding RDMA read request consumes a certain amount of memory on the HCA chip.

Because of the high cost of this HCA memory, IB devices known in the art typically allow no more than one or a few outstanding read requests per QP.

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