312 results about "Instruction decoder" patented technology

Integrated circuits, assemblies with integrated circuits, display devices and electrical circuits. There are various different aspects and embodiments of these apparatuses described herein. According to one aspect, a display device includes a plurality of display drivers which includes a serial shift register, wherein the display drivers are located in the display area of the display device which is viewable. According to another aspect, an integrated circuit, which has a plurality of functionally symmetric interface pads, includes an instruction decoder which decodes instructions received through at least one of the pads. In another aspect, an integrated circuit (IC) includes a position detector which detects a position of the IC relative to a receptor substrate and provides a signal which is determined by the position; this IC may be used in an assembly which includes the receptor substrate. In another aspect, an IC includes a position detector which detects a position of the IC relative to a receptor substrate and also includes a configurable pad which is configurable, depending upon the position as one of at least two of the following: an input pad, an output pad, or a no-operation pad. According to another aspect, a layout of an IC has a plurality of functionally symmetric interface pads wherein two such pads are configurable pads. According to another aspect, an assembly includes a receptor substrate and an IC attached to the substrate, and the IC includes a first logic circuit which provides a first function, a second logic circuit which provides a second function, and a selector which selects between the two functions such that the IC performs only the selected function. Other aspects and methods are also described.

Integrated circuits, assemblies with integrated circuits, display devices and electrical circuits. There are various different aspects and embodiments of these apparatuses described herein. According to one aspect, a display device includes a plurality of display drivers which includes a serial shift register, wherein the display drivers are located in the display area of the display device which is viewable. According to another aspect, an integrated circuit, which has a plurality of functionally symmetric interface pads, includes an instruction decoder which decodes instructions received through at least one of the pads. In another aspect, an integrated circuit (IC) includes a position detector which detects a position of the IC relative to a receptor substrate and provides a signal which is determined by the position; this IC may be used in an assembly which includes the receptor substrate. In another aspect, an IC includes a position detector which detects a position of the IC relative to a receptor substrate and also includes a configurable pad which is configurable, depending upon the position as one of at least two of the following: an input pad, an output pad, or a no-operation pad. According to another aspect, a layout of an IC has a plurality of functionally symmetric interface pads wherein two such pads are configurable pads. According to another aspect, an assembly includes a receptor substrate and an IC attached to the substrate, and the IC includes a first logic circuit which provides a first function, a second logic circuit which provides a second function, and a selector which selects between the two functions such that the IC performs only the selected function. Other aspects and methods are also described.

A microprocessor includes a hierarchical memory subsystem, an instruction decoder, and a stream prefetch unit. The decoder decodes an instruction that specifies a locality characteristic parameter. In one embodiment, the parameter specifies a relative urgency with which a data stream specified by the instruction is needed rather than specifying exactly which of the cache memories in the hierarchy to prefetch the data stream into. The prefetch unit selects one of the cache memory levels in the hierarchy for prefetching the data stream into based on the memory subsystem configuration and on the relative urgency. In another embodiment, the prefetch unit instructs the memory subsystem to mark the prefetched cache line for early, late, or normal eviction according to its cache line replacement policy based on the parameter value.

A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.

A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.

An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.

A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.