87 results about "Instruction decoder" patented technology

An apparatus is described having processing circuitry to perform vector processing operations, a set of vector registers, and an instruction decoder to decode vector instructions to control the processing circuitry to perform the required operations. The instruction decoder is responsive to a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element, to determine, from a data vector indication field of the given vector memory access instruction, at least one vector register in the set of vector registers associated with a plurality of data elements, and to determine, from at least one capability vector indication field of the given vector memory access instruction, a plurality of vector registers in the set of vector registers containing a plurality of capabilities. Each capability is associated with one of the data elements in the plurality of data elements and provides an address indication and constraining information constraining use of that address indication when accessing memory. The number of vector registers determined from the at least one capability vector indication field is greater than the number of vector registers determined from the data vector indication field. The instruction decoder controls the processing circuitry: to determine, for each given data element in the plurality of data elements, a memory address based on the address indication provided by the associated capability, and to determine whether the memory access operation to be used to access the given data element is allowed in respect of that determined memory address having regard to the constraining information of the associated capability; and to enable performance of the memory access operation for each data element for which the memory access operation is allowed.

The invention provides a data processor and method, electronic equipment and a storage medium, the data processor comprises an instruction scheduler and a copy engine, the instruction scheduler comprises a first tensor access register, and the first tensor access register is used for storing sub-tensor description information transmitted externally; the replication engine comprises a first queue structure, a second tensor access register and an instruction decoder, the second tensor access register is used for storing sub-tensor description information received from the first queue structure, and the instruction decoder is used for analyzing an instruction received from the first queue structure and generating a control signal to drive data handling; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure, so that the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item, therefore, the data transmission redundancy can be reduced, and the data transmission efficiency is improved. And the instruction processing efficiency is improved.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.

Embodiments of apparatuses and methods for copying and operating on matrix elements are described. In embodiments, an apparatus includes a hardware instruction decoder to decode a single instruction and execution circuitry, coupled to hardware instruction decoder, to perform one or more operations corresponding to the single instruction. The single instruction has a first operand to reference a base address of a first representation of a source matrix and a second operand to reference a base address of second representation of a destination matrix. The one or more operations include copying elements of the source matrix to corresponding locations in the destination matrix and filling empty elements of the destination matrix with a single value.

The invention provides an ALU array, a processor based on the ALU array and a message processing method, and relates to the field of communication, and the ALU array comprises a plurality of switch units and calculation units of various operation types. Wherein each switch unit is connected with at least one of the remaining switch units, and each switch unit is further connected with a calculation unit of at least one operation type. And each switch unit is used for receiving the to-be-processed sub-instruction mapped by the instruction decoder and sending the to-be-processed sub-instruction to the calculation unit which is connected with the switch unit and corresponds to the operation type required by the to-be-processed sub-instruction. According to the technical scheme, the utilization rate of ALU logic resources and the message processing efficiency are improved.

The invention discloses a data processing device, method and equipment, and belongs to the field of computers. The device comprises; the instruction decoder is used for decoding a four-word loading instruction, a first memory address and a target register are specified in the four-word loading instruction, and the processing circuit is used for responding to the four-word loading instruction and determining a next register of the target register; and the data loading module is used for reading continuous four-word data from the first memory address and orderly loading the continuous four-word data to the target register and the next register. Therefore, on the premise that the instruction format of the processor architecture is followed, the four-word instruction is loaded, and conflicts with existing instructions of the architecture are avoided. Based on similar principles, the device can store four-word instructions.

A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.

An apparatus is provided comprising processing circuitry to perform operations, instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions, and array storage comprising storage elements to store data elements. The array storage is arranged to store at least one two dimensional array of data elements accessible to the processing circuitry when performing the operations, each two dimensional array of data elements comprising a plurality of vectors of data elements, where each vector is one dimensional. The instruction decoder circuitry is arranged, in response to decoding a zero vectors instruction that identifies multiple vectors of data elements of a given two dimensional array of data elements within the array storage, to also decode a subsequent accumulate instruction arranged to operate on the identified multiple vectors of data elements, and to control the processing circuitry to perform a non-accumulating variant of an accumulate operation specified by the accumulate instruction to produce result data elements for storing in the identified multiple vectors within the array storage.

Techniques for monitoring memory tag load performance are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a first instruction, the first instruction including an instruction format, the instruction format having a field for a value to indicate that execution of the first instruction is to include one or more memory tag checking operations; execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform the one or more memory tag checking operations in response to the first instruction, wherein the one or more memory tag checking operations include a memory tag load operation; and performance monitoring circuitry to count occurrences of an event associated with the memory tag load operation.

A checker pipeline for checking integrity of an instruction decoder of a primary processor pipeline of a processing system including an instruction fetch checker and an instruction decoder checker. The processor pipeline includes an instruction fetch stage that receives an instruction with fields and the instruction decoder stage that decodes the instruction into instruction field values. The instruction fetch checker receives and converts instruction correction information provided with the instruction into instruction byte parity information. The instruction decoder checker includes a parity converter that converts the instruction byte parity information and instruction field information into predicted field parity information used to check the integrity of the instruction decoder. The instruction correction information is ECC bits or the like which are converted into instruction byte parity bits. The parity converter combines instruction byte parity bits with corresponding instruction bits using a logic operation into the predicted field parity information.

A processor includes an instruction decoder configured to provide at least a floating point instruction control signal; performing floating point calculation on a data path; a floating point custom instruction control logic block coupled to the floating point compute data path; a control and status register coupled to the floating point computational data path and the floating point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point computational data path based on a state of a selection control signal; and a second multiplexer configured to provide a floating point operand or a custom operand to the floating point computing data path based on a state of the selection control signal. The floating point custom instruction control logic block asserts a select signal while directing the floating point computational data path to assist it in executing custom instructions. The custom instruction may be a floating point exponential function.

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

A vector processor includes a mask register configured to hold mask values, an instruction decoder configured to set dependency information included in instruction execution information when a decoded instruction is a subsequent instruction having data dependency with one or more previous instructions, and to set all-set information included in instruction execution information when a decoded instruction sets all of the mask values, a vector processing unit configured to execute vector arithmetic operations based on the instruction execution information, and to store in the data register a result of an arithmetic operation of a vector element corresponding to each mask value that is in a set state, and a dependency reset unit configured to reset the dependency information corresponding to a destination operand of the subsequent instruction and the mask register, when the all-set information is set for the mask register and the mask register is designated by the subsequent instruction.

Processing circuitry (16) and an instruction decoder (9) supports a load chunk instruction and a store chunk instruction which can be useful for implementing memory copy functions and other library functions for manipulating or comparing blocks of memory. Number of bytes to load or store in response to these instructions is determined based on an implementation specific condition. As well as loading or storing bytes of data, the load chunk instruction and (10) store chunk instruction also designated a load / store length value as data corresponding to an architecturally visible register, which provides an indication of a number of bytes loaded or stored.

Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

The invention is applicable to the technical field related to processors, and provides an ALU architecture low-power optimization system and method based on RISC-V. The system comprises a register file, an instruction decoder, a control state machine, an improved multiplier and an improved divider. The register file is used for storing operands; the instruction decoder is used for identifying a multiplication or division instruction and outputting a control signal; the control state machine is used for freezing or releasing the assembly line according to the control signal; the improved multiplier and the improved divider are used for executing low-power-consumption arithmetic operation; through the improvement, the power consumption and the area overhead of a chip are effectively reduced while the multiplier and the divider guarantee high-speed operation, and the method is particularly suitable for an SoC system with high requirements for energy efficiency and performance and shows remarkable advantages in application scenes such as a mobile terminal and artificial intelligence.

The present invention discloses a CPU capable of precise delay control and a precise delay control method, comprising: an instruction decoder for decoding a valid delay instruction and outputting a delay request and instruction information; an adder having a first delay value and a second delay value inputted into its input terminal and a counter connected to its output terminal; a counter that, upon receiving a delay request, reloads the output value of the adder, counts, and outputs the count result to a delay controller; a delay monitor for receiving instruction matching information, matching according to detected pipeline instructions, and transmitting the matching result to the delay controller; and a delay controller for receiving the delay request and instruction matching information outputted by the instruction decoder, the counting result outputted by the counter, and the matching result outputted by the delay monitor, and generating or canceling a pause request to a CPU pipeline controller. The present invention has high delay accuracy, deterministic results, high processor utilization, and low power consumption.

An apparatus comprises an instruction decoder 20 and processing circuitry 22. Monitoring circuitry 36 monitors one or more events indicative of a potential update to data associated with any of a monitored set of addresses, and makes accessible to software executing on the processing circuitry 22 a monitoring reporting indication indicative of whether any events has occurred for at least one of the monitored set of addresses. In response to decoding of an exclusive status setting instruction specifying a given address, the processing circuitry 22 sets an exclusive status associated with the given address. The exclusive status is cleared in response to detecting an event indicative of a conflicting memory access to the given address. In response to decoding of a monitor exclusive instruction, the processing circuitry 22: determines whether the exclusive status is associated with a target address, and if so allocates the target address to be one of the monitored set of addresses.

A digital data processor (100) comprising: an instruction memory (121) storing instructions, each of the instructions specifying a data processing operation and at least one data operand field; an instruction decoder (113) coupled to the instruction memory for sequentially retrieving instructions from the instruction memory and determining the data processing operation and the at least one data operand; and at least one arithmetic unit (110) coupled to a data register file (123) and to the instruction decoder for performing a data processing operation on at least one operand corresponding to an instruction decoded by the instruction decoder and storing the result of the data processing operation. The arithmetic unit is configured to increment a histogram value in response to a histogram instruction by incrementing a bin entry at a specified location in at least one histogram of a specified number.

Processing circuitry is provided to perform operations, along with instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions. A set of registers is used to hold data values for access by the processing circuitry. The instruction decoder circuitry is responsive to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing circuitry to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information. Further, an ordering indication is derived from the ordering constrained access instruction and used to determine an order in which the multiple data values are to be accessed when performing the sequence of access operations, to thereby ensure that observability conditions required when implementing the ordering constrained access instruction are met.

The invention relates to histogram operation. A digital data processor (100) includes: an instruction memory (121) storing instructions each specifying a data processing operation and at least one data operation digit segment; an instruction decoder (113) coupled to the instruction memory for sequentially invoking instructions from the instruction memory and determining the data processing operation and the at least one data operand; and at least one arithmetic unit (110) coupled to the data register file (123) and to an instruction decoder to perform a data processing operation on at least one operand corresponding to an instruction decoded by the instruction decoder and to store a result of the data processing operation. The arithmetic unit is configured to incrementing a histogram value in response to a histogram instruction by incrementing a bin entry at a specified location in at least one histogram of a specified number.

Processing of iterative operations is disclosed. An apparatus has processing circuitry to perform an iterative operation in response to a decoding of an iterative operation instruction by an instruction decoder, the iterative operation including at least two iterations of processing in which an iteration depends on an operand produced in a preceding iteration. Initial information producing circuitry performs an initial portion of the processing of a given iteration to produce initial information. Result producing circuitry performs a remaining portion of the processing of the given iteration to produce a result value using the initial information. For iterations other than a final iteration, forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation. The initial information producing circuitry begins performing an initial portion of the next iteration in parallel with the result producing circuitry completing the remaining portion of the current iteration to improve performance.

Computer systems and methods for cache writeback and invalidation of specified keys. In one embodiment, in response to a first instruction of an instruction set architecture for writeback and invalidation of a hierarchical cache based on a single specified key identification, a decoder translates at least one microinstruction. According to the at least one microinstruction, a writeback and invalidation request is supplied to an in-core cache via a memory order buffer, and in turn by the in-core cache to a last level cache. In response to the writeback and invalidation request, the last level cache finds all matching cache lines that match the specified key identification, writes back to system memory those matching cache lines that have been modified and do not exist in a superior cache, and invalidates all matching cache lines found regardless of whether a state change has occurred. For a second instruction of an instruction set architecture for writeback and invalidation of a hierarchical cache based on multiple specified key identifications, the present application implements multiple writeback and invalidation requests.

A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.

The present invention relates to a processor designed to optimize memory bandwidth utilization for tensor transpositions in machine learning. It features an instruction decoder that decodes tensor transpose instructions for an input tensor, distinguishing between transposing and stationary axes. An inner transpose engine, equipped with multiple tensor buffer units of varying sizes, transposes the tensor by reading data by rows and writing by columns, efficiently managing memory when the buffer is full. Additionally, an address scheduler determines the target memory addresses in the output tensor memory for the tensor data, improving the handling and transformation of tensors in machine learning environments. This processor significantly enhances the efficiency and speed of tensor operations critical to advanced machine learning applications.

Techniques for tag checking for dynamically repeating memory accesses are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a single instruction, the single instruction having a format including an opcode field, the single instruction having a first opcode value in the opcode field; and execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform operations in response to decoding of the single instruction, the operations including performing repeating memory tag checking operations in connection with repeating memory access operations.

Data processing apparatus comprises vector processing circuitry to access an array register having at least n×n storage locations, where n is an integer greater than one, the vector processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry. The instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, for a vector of n vector elements, a set of n storage locations each having a respective array location in the array register. The array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

Provided is a processor controlling pipeline processing to avoid the occurrence of pipeline bubbles as much as possible even when executing jump instruction. The present processor executes pipeline processing in which: an instruction fetcher fetching a machine-language instruction based on a memory address set in a program counter; a decoder decoding the machine-language instruction output from the instruction fetcher into control information; and an executer executing the control information output from the decoder, are connected, and the present processor comprises: a table describing a head address and a head machine-language instruction for each destination of jump; and a pipeline controller setting, when the executer executing a control information of a jump, an address specifying a second machine-language instruction at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction at the destination of the jump to the decoder.