5 results about "Multiply–accumulate operation" patented technology

The application provides an error upper bound device, a determination method, a medium, a terminal and a program product suitable for dynamic precision floating point multiply-accumulate operation, comprising: a feature acquisition module for acquiring a truncation compensation factor of each operand and an accumulator tolerance factor; a local threshold allocation module for allocating a local error threshold for the current multiply-accumulate operation according to a preset global error tolerance, a remaining term number, a remaining budget, an energy consumption mode and the accumulator tolerance factor; a bit budget formula calculation module for calculating the actual precision supply and precision demand of each path respectively; a determination and feedback module for determining according to the actual precision supply and precision demand calculated by each path; if each path passes, a precision pass signal is fed back; otherwise, a precision upgrade mechanism is triggered. The application can give a deterministic error upper bound for the truncation error of each multiply-accumulate operation, and ensure that the global precision target is met.

The present application belongs to the technical field of reservoir computing, and particularly relates to a method for implementing a large-scale optoelectronic reservoir computing system. The method comprises: performing matrix sparsification connection to form a sparse connection matrix in the form of a lower triangular matrix composed of basic matrix calculation units A and B; then performing rank reduction operation on the sparse connection matrix, so that the product of the original sparse matrix and the input signal is converted into the product form of each basic matrix unit after splitting and the input signal after splitting, and the dimension of each subunit is reduced to 1 / 2 of the original dimension; the above splitting operation is repeated until the splitting reaches the scale supported by the optical chip unit; then the reservoir is trained and tested to obtain a weight matrix calculation prediction value. The multiplication operation shares the same chip, and the multiplication and accumulation operation of a matrix of any scale can be completed by multiplexing the basic scale optical computing chip. The present application achieves ideal effects in the application of communication signal post-equalization, signal recognition, etc.

The application provides a self-adaptive precision floating-point multiply-accumulate operation device, method, medium, terminal and program product, comprising: an unpacking and feature extraction module which unpacks and performs feature extraction on the received floating-point number to be operated; a precision level prediction module which predicts an initial precision level according to the input key features and the pre-set energy consumption mode and error threshold; a precision control module which generates an effective precision bit number control signal according to the initial precision level; a multiplication module which performs multiplication operation on the floating-point number to be operated according to the received effective precision bit number control signal; an error upper bound module which calculates the error upper bound; and compares the error upper bound with the error threshold; and a fusion accumulation module which accumulates the final multiplication result after normalization and rounding operation when the error upper bound is less than or equal to the error threshold, and outputs the operation result. The application can improve operation efficiency, reduce energy consumption and cost, and enhance numerical stability and reliability.

Embodiments of the present disclosure relate to a multiply-accumulate (MAC) device for in-memory computing. A capacitive charge-coupled mode analog in-memory computing (CIM) bitcell array is configured to generate an analog output voltage corresponding to a multiply-accumulate (MAC) operation result using multi-bit weights. The analog output voltage is input to a dual-mode activation module that is selectively capable of operating in a deep neural network (DNN) mode and a spiking neural network (SNN) mode. The activation module includes a sample-and-hold (S&H) circuit, a comparator, a digital-to-analog converter (DAC) that can be reconfigured depending on the selected mode of the DNN mode and the SNN mode.

Tensor processing circuitry 17 comprises a plurality of dot-product units 100, each of which is configured to perform a multiply accumulate operation. A format conversion unit (20, Fig. 2) is configur