Neural network accelerator for bit width partitioning and implementation method of neural network accelerator

Abstract

The present invention provides a neural network accelerator for bit width partitioning and an implementation method of the neural network accelerator. The neural network accelerator includes a plurality of computing and processing units with different bit widths, input buffers, weight buffers, output buffers, data shifters and an off-chip memory; each of the computing and processing units obtains data from the corresponding input buffering area and weight buffer, and performs parallel processing on data of a neural network layer having a bit width consistent with the bit width of the corresponding computing and processing unit; the data shifters are used for converting the bit width of data outputted by the current computing and processing unit into a bit width consistent with the bit width of a next computing and processing unit corresponding to the current computing and processing unit; and the off-chip memory is used for storing data which have not been processed and have been processed by the computing and processing units. With the neural network accelerator for bit width partitioning and the implementation method of the neural network accelerator of the invention adopted, multiply-accumulate operation can be performed on a plurality of short-bit width data, so that the utilization rate of a DSP can be increased; and the computing and processing units (CP) with different bit widths are adopted to perform parallel computation of each layer of a neural network, and therefore, the computing throughput of the accelerator can be improved.

Description

technical field [0001] The invention relates to computer vision technology, in particular to a neural network accelerator for bit width partitioning and its implementation method. Background technique [0002] In recent years, convolutional neural networks have made great progress in many computer vision applications, such as image recognition, video classification, gesture recognition, etc. Recently, with the introduction of more and more convolutional neural network (CNN) algorithms, the recognition accuracy of CNN has been greatly improved, and the recognition accuracy reached 96.4% at the 2015 ILSVRC conference. However, in order to achieve such a high recognition accuracy, CNN needs to introduce very complex algorithms, which will increase the overhead of hardware computing resources and greatly limit the performance improvement of CNN at the hardware level. Therefore, many acceleration methods for CNN have been proposed to increase the computing performance of CNN, su...

AI Technical Summary

Problems solved by technology

However, this design method converts the multiplication and accumulation operation in the convolutional neural network into an AND or logic operation, which improves the computing performance of the accelerator, but increases the hardware area by 35%, but largely sacrifices the CNN hardware. Area index

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