Method in microprocessor

Abstract

Accoridng to a method in a microprocessor, the microprocessor prepares a fused multiply-accumulate operation of a form +-A*B+-C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.

Description

[0001] This application has an application date of June 24, 2015, an application number of 201580003388.3 (international application number PCT / US2015 / 037508), and an invention titled "Branch fusion product-accumulation operation using the first and second sub-operations" Divisional application of the application. [0002] related application [0003] This application claims the U.S. Patent No. 62 / 020,246 provisional application "Non-Atomic Split-Path Fused Multiply-Accumulate with Rounding cache" filed on July 2, 2014 and the U.S. Patent No. 62 / 020,246 filed on June 10, 2015 Priority of Provisional Application No. 62 / 173,808 "Non-Atomic Temporally-SplitFused Multiply-Accumulate Apparatus and Operation Using a Calculation Control Indicator Cache and Providing a Split-Path Heuristic for Performing a FusedFMA Operation and Generating a Standard Format Intermediate Result". The entirety of these priorities are incorporated into this application by reference. [0004] This applica...

AI Technical Summary

Problems solved by technology

However, this approach has many disadvantages

[0015] First, FMA hardware is more expensive and complex to set up than using separate add and multiply functional units

Second, when performing simple addition or multiplication operations, using FMA hardware has higher latency and generally consumes more power than using separate addition and multiplication functional units

This time delay is sometimes modeled as a delay due to "long wires"

Therefore, in order to reduce the impact of the indivisible FMA operation on instruction-level parallel processing, the additional functional blocks can provide quite limited improvement after considering the required chip size, power consumption and arithmetic operation delay.

[0017] Therefore, the best proposals and implementations will usually (but not always) provide correct results (corresponding to IEEE rounding and other specifications), sometimes provide high instruction output (throughput), but obviously require additional Hardware circuitry increases setup cost and increases power consumption to perform simple multiply and add operations on complex FMA hardware

[0018] What modern FMA designs were intended to achieve has not yet been fully achieved

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