28 results about "Binary neural network" patented technology

The invention provides a quasi-e-system neural network model, a construction method, a data processing method and an electronic device, the quasi-e-system neural network model comprises an input layer, a hidden layer and an output layer, the input layer is used for receiving data; the hidden layer comprises neurons, the neurons comprise at least one sub-neuron, the sub-neuron can represent any one of a binary function g (x) and a ternary function t (x), and an activation function F (x) of the neurons represents linear weighted fitting of the binary function g (x) and the ternary function t (x). According to the scheme provided by the invention, by adopting the combination of the binary function g (x) and the ternary function t (x), the precision and the energy consumption of the model are balanced on the basis of keeping the high compression ratio and the high calculation efficiency of the binary neural network.

The application discloses a permanent magnet synchronous motor stator fault diagnosis method and system based on a human learning optimization algorithm, and the method comprises the following steps: obtaining a three-phase current signal of a stator of a permanent magnet synchronous motor, converting the signal into a two-dimensional time-frequency diagram after being decomposed by a variational mode and being demodulated by a Hilbert envelope; constructing a binary neural network for processing the two-dimensional time-frequency diagram and determining a search space; generating a candidate architecture by global search using a first human learning optimization algorithm; for each candidate architecture, fine-tuning the classification layer parameters thereof by proportional evolution using a second human learning optimization algorithm, taking the classification performance of a verification set as a fitness value, and iteratively obtaining an optimal model; inputting a current signal to be diagnosed into the model after the same preprocessing, and outputting a stator fault diagnosis result. Compared with the prior art, the application realizes low-overhead accurate diagnosis of weak faults of a permanent magnet synchronous motor stator by physical information driven preprocessing and double-layer human learning optimization.

A framework is presented that provides a shift in the conceptual and practical realization of privacy-preserving interference on deep neural networks. The framework leverages the concept of the binary neural networks (BNNs) in conjunction with the garbled circuits protocol. In BNNs, the weights and activations are restricted to binary (e.g., ±1) values, substituting the costly multiplications with simple XNOR operations during the inference phase. The XNOR operation is known to be free in the GC protocol; therefore, performing oblivious inference on BNNs using GC results in the removal of costly multiplications. The approach consistent with implementations of the current subject matter provides for oblivious inference on the standard DL benchmarks being performed with minimal, if any, decrease in the prediction accuracy.

A binary neural network (BNN) without floating-point layers uses inter-layer input data and inter-layer output data represented in n-bit binary format, where n is less than 32. For instance, n may be 8. Each layer of a set of hidden layers is operative to perform binarized operations on respective input data and at least one of the hidden layers, and includes a trained one-bit binary quantizer with a preconfigured binarization threshold that was configured during training.

This invention proposes a lightweight remote sensing image change detection method based on a binary neural network and large-kernel strip convolution. The implementation steps are as follows: obtaining training and testing sample sets; constructing a lightweight remote sensing image change detection network model based on a binary neural network and large-kernel strip convolution and iteratively training it; and obtaining the lightweight remote sensing image change detection results. In the process of iteratively training the lightweight remote sensing image change detection network model and obtaining the change detection results, this invention uses ResNet18 networks in two branches to perform deep feature extraction on the feature maps of both time periods. This allows the weights and activations to be quantized to +1 and -1, achieving a 32-fold memory saving and a 58-fold CPU acceleration, avoiding the drawback of existing technologies with a large number of parameters, and effectively improving detection efficiency. Simultaneously, the large-kernel strip convolution network compensates for the accuracy deficiency caused by binary quantization.

The application provides a face image privacy protection recognition method based on optical coding and reverse feature enhancement, and relates to the technical field of computer vision recognition, and the method comprises the following steps: S1, acquiring a face data set, performing data enhancement, and constructing a face enhanced data set; S2, constructing a binary neural network convolution coding layer based on a straight-through estimator quantization, and performing optical coding on the face enhanced data set; S3, constructing a CNN and Transformer dual-channel multiplexing reverse feature enhancement neural network model, and performing feature dimension enhancement; S4, using a hybrid constraint, and jointly optimizing the neural network coding layer and the dual-channel multiplexing reverse feature enhancement neural network model; and S5, constructing a face embedding database, comparing a high-dimensional coding value of a single-pixel detection value with features in the face embedding database, and realizing face recognition. The application jointly optimizes the neural network binary convolution coding layer for spatial light modulator optical coding and the dual-channel multiplexing reverse feature enhancement model, so that the recognition precision is improved.

The invention relates to the field of semiconductor devices, and discloses an in-memory computing accelerator and an in-memory computing system for a ferroelectric capacitor without an operational amplifier, a word line WL and a word line anti-WLB are parallel to each other, and a bit line BL is located in the vertical direction of the word line WL and the word line anti-WLB; one end of the first capacitor is connected with the bit line BL, and the other end is connected with the word line WL; one end of the second capacitor is connected with the bit line BL, and the other end of the second capacitor is connected with the word line reverse WLB. According to the calculation accelerator in the ferroelectric capacitor memory, by optimizing an array structure and a read-out mechanism, high power consumption caused by OPAMP is eliminated, meanwhile, high calculation precision and energy efficiency are kept, and the calculation accelerator is suitable for a high-efficiency reasoning task of an edge-end binary neural network BNN.

The invention relates to the technical field of currency detection, and discloses a currency detection method, system and device based on a deep binary neural network, and the key point of the technical scheme is that the method comprises the following steps: S1, obtaining an image of a currency sample and corresponding labeling data, and forming a data set, the currency sample comprises a variety of genuine currency and counterfeit currency, and the labeling data comprises true and false labels; s2, constructing a deep binary neural network model, wherein the model comprises an input layer, a plurality of binarization convolution layers, a plurality of binarization full-connection layers and an output layer which are connected in sequence; s3, training, verifying and testing the deep binary neural network model through the data set to obtain an applicable model; and S4, integrating the applicable model in currency detection equipment, and detecting the to-be-detected currency.

Methods and systems for computing in-dynamic random access memory (DRAM) computing include loading a first group of cells of the DRAM with input parameters and loading a second group of cells of the DRAM with inverted input parameters that are each complementary to corresponding input parameters. An offset group of cells of the DRAM is loaded with an indication of an offset voltage. An operation is performed on weights with corresponding stored input parameters or the stored inverted input parameters, and a column of the first group and the second group is activated to perform an accumulation of the operations of weights for cells in the column to store a sum. An offset voltage is generated using the indication, and an output is generated based on the comparison of the sum and the offset voltage and is stored in an output group of cells of the DRAM.

This patent relates to an asymmetric channel expansion and contraction technique (AESBNN) applied to binary convolutional layers, belonging to the field of binary neural network optimization technology in deep neural networks. This design aims to solve the problem that existing symmetric channel expansion and contraction techniques (ESBNN) cannot balance computational complexity and model accuracy according to the needs of different scenarios due to their fixed expansion / contraction ratio. The core solution is to introduce an asymmetric ratio r to first expand the number of input channels by a factor of t to increase the dynamic range of the binary convolution output. Then, the number of output channels of the convolution kernel is reduced to 1 / (t*r) of the original number to adjust computational complexity. Finally, through channel duplication and splicing layers and batch normalization (BN) layers, the final output channels are restored to be compatible with subsequent network layers. This method provides a flexible accuracy-efficiency balance strategy: when r > 1, computational complexity is prioritized to be reduced; when r < 1, the model's representational ability is prioritized to be improved. Experiments show that this technology can achieve better performance (such as PSNR) than basic binary convolutional units in tasks such as image super-resolution with lower computational cost (such as halving the computational cost when r=2), and can be flexibly integrated into various deep neural networks as a plug-and-play general module.

The invention discloses a data processing method and device of an intermediate neural network layer and a random binary neural network, and relates to the technical field of neural networks, and the method comprises the steps: obtaining the output data of a preorder neural network layer, and converting the output data of the preorder neural network layer into weighted summation data; based on preset sampling times, performing multiple independent Bernoulli sampling on the weighted summation data to obtain multiple sampling results; and based on multiple sampling results, determining target sampling data, and transmitting the target sampling data to a post-order neural network layer for reasoning. Through the above mode, a noise suppression mechanism is moved forward from an output layer to an intermediate layer, and multiple sampling and averaging operations are carried out in the intermediate layer, so that instantaneous noise introduced by single random sampling can be effectively smoothed, the statistical variance output by an activation value of the intermediate layer is reduced, and the stability of signal transmission between layers of a neural network is improved. The cascade amplification effect of noise in the deep network is effectively suppressed, and the overall reasoning precision of the model is improved.

The application discloses a privacy protection inference method for a binary neural network model under outsourcing computation and belongs to the field of neural network inference under outsourcing computation environment. Firstly, an inference system composed of a model owner, an edge server group and a user group is constructed, the model owner performs RSS, encrypts and distributes BNN model parameters to three edge servers, runs a symbolic function, generates an FSS function key and distributes the FSS function key to each edge server; meanwhile, random numbers are generated to mask multiplication operation and send data. Then, aiming at the BNN model, an activation function is designed based on the FSS and RSS hybrid protocol to optimize nonlinear operation, and a convolution layer and a full connection layer are constructed based on the RSS to provide efficient linear operation. Finally, the user adds the query result of the BNN model locally by using the additive homomorphism property of secret sharing to reconstruct a plaintext inference result. The application completes the lightweight construction of each module in the BNN, improves inference efficiency and realizes the protection of inference data privacy under a limited computing resource environment.

The invention provides a memory device and an in-memory computing method. A memory device, such as a three-dimensional NAND type flash memory, provides a high performance and high capacity storage medium. In a memory device, an input parser provides initial address information and initial layer activation value data. The read-out data sensing and comparator reads initial data corresponding to the initial address information from the memory array, and compares initial layer activation value data with a plurality of weight data in the initial data bit by bit to generate a plurality of first comparison data. The error bit detector analyzes the first comparison data so as to generate a plurality of first analysis data. The operation circuit uses an activation function to operate each of the first analysis data and the corresponding second analysis data to provide intermediate layer activation value data to the input parser.

This invention provides a secure prediction method based on a binary neural network. For each layer of the binary neural network, while fully utilizing its binary characteristics, a secure and efficient ciphertext evaluation protocol is designed using lightweight low-level cryptographic primitives. Combining these protocols enables end-to-end privacy prediction services. Specifically, for the linear layers in the prediction process, this invention proposes a binary matrix multiplication protocol. For the nonlinear layers in the prediction process, this invention innovatively introduces a secure symbolic protocol with adder logic. All the protocols proposed in this invention can significantly improve the communication and computational efficiency of ciphertext prediction while ensuring security.

The application discloses a kind of panoramic perception method, device, equipment and medium based on fish-eye camera, can be widely applied in real-time look-around depth estimation field, method includes: four fish-eye cameras are obtained four fish-eye images;Four fish-eye cameras are placed on the four vertices of a square respectively, lens is directed to the outside of the diagonal of square;Each fish-eye camera generates two virtual pinhole cameras, each virtual pinhole camera and adjacent fish-eye camera generated virtual pinhole camera constitute binocular camera;According to the mapping table generated by the imaging principle of fish-eye camera and the parameter of virtual pinhole camera in advance, each fish-eye image is converted into the left image and right image of corresponding binocular camera;The left image feature of each binocular camera left image and the right image feature of right image are extracted using binary neural network;Disparity calculation is carried out to the left image feature and right image feature corresponding to each binocular camera, and four depth maps covering the panoramic of the position of four fish-eye cameras are obtained.

The application discloses a kind of knowledge distillation method and system based on structural feature knowledge, belong to model compression technical field, including: S1, student network and teacher network are built;Wherein, teacher network is loaded with trained model, is full-precision neural network;Student network is binary neural network;S2, the second training sample set that is collected in advance is respectively input to student network and teacher network, by simultaneously minimizing the difference between the intermediate layer features of student network and teacher network, and the difference between the relationship features in student network and teacher network, student network and teacher network are trained, to realize the model compression of teacher network. Through the above process, the present application can reduce the huge difference between the intermediate structure of teacher and student network, to solve the problem of knowledge transfer limited due to distribution difference and the overfitting problem of student network, the accuracy of neural network model compression is higher.

The application relates to the technical field of power system state monitoring, and discloses a power distribution network multi-parameter state monitoring system, method, equipment and medium based on edge computing, the method comprising the following steps: the system comprises a miniaturized heterogeneous sensing module, an edge computing unit, a dual-mode communication module and a synchronous clock module. The miniaturized heterogeneous sensing module synchronously collects temperature, partial discharge, vibration and current signals of key equipment of a power distribution network; the edge computing unit deploys a binary neural network model, performs local fault diagnosis on multi-parameter digital signals, and generates fault grade coding; the dual-mode communication module dynamically selects a communication mode according to the fault severity and channel quality, and uploads the diagnosis result; and the synchronous clock module provides a unified sampling and processing time sequence reference, and ensures that multi-parameter data is time-aligned.

This invention discloses a high-efficiency segmented sparse binary neural network accelerator for real-time gesture recognition. This invention relates to the field of integrated circuit technology. The invention designs an accelerator architecture including an interface unit, an on-chip storage unit, an on-chip data transmission unit, a channel rearrangement (CSR) compression unit, a sparse sensing computing controller, and a processing unit array. The core of this invention is to improve activation graph compression efficiency through channel rearrangement (CSR) compression, to pre-compute redundant data through sparse sensing computing to skip invalid computations, and to improve processing unit utilization through optimized scheduling. It features low power consumption and low latency, effectively reducing hardware resource consumption and further improving hardware energy efficiency.

The invention discloses a power distribution network reliability index evaluation method and system based on a binary neural network, and belongs to the technical field of power system reliability evaluation. The method comprises the following steps: acquiring configuration data of the circuit breaker of the power distribution network and preprocessing; constructing a multi-task binary neural network model comprising a shared encoder and a plurality of task specific headers; calculating conservative double-boundary constraints of the key node indexes based on the training data; constructing a multi-task total loss function fusing constraint penalty terms through an augmented Lagrange method; and taking the loss function as a target training model, and performing evaluation and prediction by using the trained model. According to the method, the calculation complexity is reduced through the binary neural network, the engineering constraint is fused into the training through the augmented Lagrange method, the lightweight, constraint-aware and multi-task cooperative high-efficiency evaluation of the reliability of the power distribution network is realized, and the evaluation speed, precision and practicability are remarkably improved.

The invention relates to the field of circuit breaker intelligent control, in particular to a circuit breaker intelligent control system and method based on the Internet of Things, and the system comprises an intelligent circuit breaker terminal, a cloud platform and a database. Generating an abnormal signal according to a preset threshold value and the counter, and sending the abnormal signal to the cloud platform; after an edge calculation module of the cloud platform receives the abnormal signal, time domain and frequency domain features of the operation data are extracted, a preset binary neural network fault classification model is input, and a fault type with the maximum prediction probability is selected as a classification result by using an argmax function; and the dynamic protection module uses a multi-target particle swarm optimization algorithm to update individual and global optimal positions, searches an optimal solution set at a Pareto frontier, maps the updated particle positions into corresponding parameters, generates a switching-on and switching-off instruction and a fault retry instruction, and sends the switching-on and switching-off instruction and the fault retry instruction to the intelligent circuit breaker terminal.

The application discloses a kind of neural network binary quantization method and image classification method, belong to digital image processing technical field.The binary neural network of the application strengthens the ability of shallow feature to retain detail information by detail feature penalty term, and is supplemented with semantic information regular module, while avoiding overfitting, strengthen the effectiveness of advanced semantic information of deep feature, finally reach the effect of enhancing the information retention of input feature map, further improve the performance of quantized network.Simulation results prove that the application has higher accuracy than existing binary neural network-based image classification method, while maintaining faster inference speed and less memory usage;In addition, the binary neural network of the application can clearly observe the main contour of the picture object, retains enough discriminative semantic information, so it can better identify the target subject in the image classification task, thereby further ensuring the accuracy of image classification.

This invention relates to a dedicated hardware accelerator for binary neural networks (BNNs) in the field of integrated circuit technology. Through the following multi-level optimization techniques, it achieves high-performance parallel computing: a multi-bank memory design and a Ping-Pong buffer structure effectively overlap data transmission and computation time, significantly improving system throughput; a hierarchical alignment mechanism, using historical registers and parity memory design, systematically solves the bit-level and address alignment challenges in BNN data streams; and a reconfigurable computing architecture, through dynamic configuration of registers and data flow paths, enables flexible adaptation to various BNN computation modes, balancing high efficiency and versatility. These optimizations work synergistically to ensure the high-performance, low-power, and highly versatile deployment of the dedicated BNN hardware accelerator on resource-constrained edge devices.

The invention relates to an optimized binary convolution unit (ESBCU) based on a channel expansion and contraction technology, and belongs to the technical field of binary neural network optimization. The optimized binary convolution unit aims to solve the problem that an existing basic binary convolution unit (BBCU) is insufficient in information expression ability due to the fact that an output value is limited to a limited discrete set. According to the core scheme, through channel expansion, contraction and copy operation, firstly, the number of input channels is expanded by t times to increase a discrete set output by binary convolution, then the number of convolution kernel output channels is reduced to 1 / t of the original number to maintain the calculation complexity unchanged, and finally, through processing of a channel copy splicing layer and a batch normalization (BN) layer, the convolution kernel output channel number is reduced to 1 / t of the original number to maintain the calculation complexity unchanged. And recovering the final output channels to the number compatible with the next layer. According to the method, on the premise of not increasing the calculation complexity, the output dynamic range of the binary convolution is effectively expanded, and the feature representation capability of the binary convolution is enhanced. Experiments show that the unit can effectively improve model performance (such as a PSNR index) in low-level visual tasks such as image super-resolution and the like, and can be flexibly integrated into various deep neural networks as a plug-and-play standard module.

The invention discloses a linear transformation execution method independent of multiplication and a computing system, and relates to the field of computer system structures and digital signal processing. The method comprises the following steps: acquiring input data in a computing local area domain; performing an element level selection or rearrangement operation on the input according to a linear transformation rule; performing symbol mapping or element suppression operation on the selected elements to achieve mapping; performing addition combination or reduction operation on the plurality of elements subjected to weight mapping to generate a linear transformation result; and keeping the linear transformation result in a computing local area domain to serve as the input of a subsequent linear transformation stage. The method does not depend on general numerical multiplication in the execution process, and the intermediate result of the multi-stage linear transformation is kept to circulate in the computing local area domain. According to the scheme, the hardware area and the dynamic power consumption are remarkably reduced, the carrying frequency of data between a calculation unit and a storage unit is reduced, and the method is suitable for weight-limited linear transformation scenes such as FFT and a binary neural network and has high energy efficiency and good expandability.

This application relates to an image processing method, system, and storage medium based on local binary convolution. It includes: acquiring the original image to be processed; performing feature-based reprocessing on the original image to obtain an initial feature map; constructing a local binary convolution model based on a binary neural network; binarizing the initial feature map using the binary convolution model to obtain a binarized feature map; using the center pixel as a local threshold for neighboring pixels in the binarized feature map and collecting high-order image statistical information; and realizing image processing through local binary convolution by having the binary neural network recognize the high-order image statistical information. This application aims to improve the accuracy of BNN structures. This method can effectively capture high-order image statistical information with maximum information retention from the input feature map through a local thresholding strategy, thereby enhancing the representation and discrimination capabilities of the BNN and improving the accuracy of image recognition.

This invention discloses a high-efficiency hardware accelerator for channel rearrangement and compression of segmented sparse binary neural networks. The invention relates to the field of integrated circuit technology and includes: a five-interval channel-level positive-to-negative ratio collector, a channel rearrangement unit, a segmented sparse activation map CSR compression unit, and a compressed segmented sparse activation map buffer. This hardware accelerator rearranges and compresses the output feature map channels of a segmented sparse binary neural network. The five-interval channel-level positive-to-negative ratio collector systematically reorders the channels to maximize compression efficiency. The channel rearrangement unit physically rearranges the segmented sparse activation vectors, activation maps, and weights according to the reordered channel sequence. The segmented sparse activation map compression unit applies CSR encoding to the reordered activation map to generate a compressed segmented sparse activation map, significantly reducing storage resource consumption. This invention features low power consumption and low latency, effectively reducing hardware resources and improving the energy efficiency ratio of the hardware.

This application relates to the field of industrial data processing technology, and discloses a deep learning-based industrial task processing method, client, cloud server, and system. The method includes: the client acquiring raw industrial data; the client processing the raw industrial data using a locally deployed feature extraction model to obtain plaintext feature vectors; encrypting the plaintext feature vectors using a preset homomorphic encryption algorithm to obtain encrypted feature vectors, and sending the encrypted feature vectors to the cloud server; the cloud server performing homomorphic encryption operations on the encrypted feature vectors using a binary neural network deployed on it to obtain ciphertext classification results; the cloud server returning the ciphertext classification results to the client; and the client decrypting the ciphertext classification results to obtain plaintext classification results, using these results to instruct industrial operations. Through this method, this application achieves the goal of meeting the real-time requirements of industrial tasks while protecting the privacy of industrial data.

Image classification methods, systems, devices, and media based on deep binary neural network models are disclosed. The method includes inputting an image to be classified into a preset deep binary neural network model to obtain a classification prediction result. The preset deep binary neural network model is obtained through the following steps: improving the binary convolution module, fusing the improved binary convolution module and the re-activation module, adding an attention mechanism module to each layer of binary convolution operations, assigning an adaptive linear scaling factor for backpropagation to the binary convolution operations, constructing a baseline network of the deep binary neural network model and initializing the floating-point parameters of the baseline network, and training using the Adam algorithm to obtain the deep binary neural network model. The system, devices, and media are used to implement the image classification method based on the deep binary neural network model. This invention reduces model complexity while achieving better stability, and improves both the accuracy and speed of image classification results.