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Time domain in-memory computing array structure based on magnetic random access memory

A random access memory and computing array technology, applied in the field of high-energy-efficiency circuit design, can solve the problems of low calculation and quantization accuracy, achieve high quantization accuracy, reduce overall power consumption, and reduce memory access power consumption

Active Publication Date: 2021-03-30
SOUTHEAST UNIV
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AI Technical Summary

Problems solved by technology

And based on the delay difference quantization unit disclosed in the present invention, the problem of low quantization accuracy of traditional in-memory calculations is solved

Method used

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  • Time domain in-memory computing array structure based on magnetic random access memory
  • Time domain in-memory computing array structure based on magnetic random access memory
  • Time domain in-memory computing array structure based on magnetic random access memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0094] In-memory computing circuit suitable for fully connected binary neural network, including: dual-mode storage array, adaptive pipeline decoder, pre-charging circuit, column selector, sense amplifier, input and output unit, delay difference quantization unit , counting unit, timing control circuit and mode selection module.

[0095]

[0096] In the formula (2), the weight matrix M is mapped in the dual-mode storage array disclosed by the present invention as:

[0097]

[0098] The mapping method is that the weight matrix M in the formula (2) is transposed along the diagonal as in the formula (3), and the matrix coordinates after the transposition are stored in the storage unit in the dual-mode storage array disclosed by the present invention.

[0099] In the formula (2), the activation value vector V is mapped as:

[0100]

[0101] The mapping method is that the activation value vector V in the formula (2) is applied in the form of a word line signal in the dual...

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Abstract

The invention discloses a time domain in-memory computing array structure based on a magnetic random access memory (MRAM), and belongs to the field of integrated circuit design. The circuit is characterized in that the structure comprises a dual-mode storage array, a self-adaptive pipeline decoder, a pre-charging circuit, a column selector, a sensitive amplifier, an input and output unit, a delaydifference quantization unit, a counting unit, a time sequence control circuit and a mode selection module. The method has a standard read-write mode and an in-memory calculation mode. Under the standard read-write mode, the read-write operation of the data in the storage array can be realized; the in-memory calculation mode can realize multiply-accumulate operation in binary neural network calculation. Multiply-accumulate calculation is completed during the reading of data; meanwhile, the delay quantization unit and the storage array are integrated together to reduce memory access energy consumption; compared with a conventional Von Noemann architecture neural network accelerator, the network operation energy efficiency is effectively improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a magnetic random access memory (MRAM)-based time-domain in-memory computing array structure and a high-energy-efficiency circuit design method for realizing binary neural network convolution calculation based on the memory. Background technique [0002] In recent years, Convolutional Neural Networks (CNN) have shined in areas such as image recognition, leading a new wave of artificial intelligence. Convolutional neural network is a hierarchical network structure, such as figure 1 As shown, it mainly includes the following hierarchical structures: data input layer, convolution calculation layer, function excitation layer, pooling layer, and fully connected layer. Such as figure 2 As shown, the calculation process can be summarized as that the current network layer is to weight and sum the activation values ​​of the previous layer, then add a bias item, and finally obta...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/16G06N3/063
CPCG11C11/1653G11C11/1673G11C11/1675G06N3/063Y02D10/00
Inventor 蔡浩周永亮张优优刘波
Owner SOUTHEAST UNIV
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