Binary neural network accumulator circuit based on analog delay chain

A technology of binarizing neural and simulating delay, applied in biological neural network models, neural architectures, neural learning methods, etc., can solve problems such as excessive consumption of energy and hardware resources, achieve less area overhead and reduce overall power consumption , the effect of high power consumption

Active Publication Date: 2019-11-08
SOUTHEAST UNIV
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Problems solved by technology

One of the most important challenges in implementing deep learning networks i...

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  • Binary neural network accumulator circuit based on analog delay chain
  • Binary neural network accumulator circuit based on analog delay chain
  • Binary neural network accumulator circuit based on analog delay chain

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Embodiment Construction

[0026] The technical solution of the invention will be described in detail below in conjunction with the drawings, but the protection scope of the invention is not limited to the embodiments.

[0027] Delay unit of the present invention such as figure 1 As shown, it consists of 3 NMOS transistors, 1 PMOS transistor and an inverter. The peripheral input data A is connected to the gates of PMOS transistor M1 and NMOS transistor M2, and the peripheral input data D is connected to the gate of NMOS transistor M3. The source of the NMOS transistor M2 and the drains of the NMOS transistors M3 and M4 are connected to the node n, the sources of the NMOS transistors M3 and M4 are connected to the ground, the source of the PMOS transistor M1 and the gate of the third NMOS transistor M4 are both connected to the power supply, The drains of the PMOS transistor M1 and the NMOS transistor M2 are connected to the node m and serve as the input end of the inverter U1, and the output of the inve...

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Abstract

The invention discloses a binary neural network accumulator circuit based on an analog delay chain, which belongs to the technical field of basic electronic circuits and comprises a delay chain modulewith two delay chains and a pulse generating circuit, the analog delay chain is composed of a plurality of analog delay units connected in series, each analog delay unit adopts six metal oxide semiconductor (MOS) tubes, and '0' and '1' are judged according to delay. According to the invention, accumulation calculation in traditional digital circuit design is replaced by an analog calculation method, the accumulator structure can stably work under wide voltage, the circuit is simple to realize, the power consumption of binary neural network accumulation calculation is effectively reduced, andthe energy efficiency of the neural network circuit can be greatly improved.

Description

technical field [0001] The invention relates to a binary neural network accumulator circuit based on an analog delay chain, relates to a circuit for realizing neural network accumulative calculation by using a digital-analog hybrid technology, and belongs to the technical field of basic electronic circuits. Background technique [0002] In recent years, artificial intelligence technology has demonstrated its unique advantages in areas such as image recognition, face detection, speech recognition, word processing and artificial intelligence games. In developed countries, artificial intelligence has become a priority development goal. Among them, the most prominent is the recent progress in the field of deep learning (Deep Learning). The research practices of high-end Internet companies such as Baidu, Google, Microsoft, and Facebook have shown that deep learning can It reaches or even surpasses human level in image perception. One of the most important challenges in implement...

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Application Information

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IPC IPC(8): G06N3/063G06N3/04G06N3/08
CPCG06N3/08G06N3/065G06N3/045
Inventor 单伟伟商新超
Owner SOUTHEAST UNIV
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