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Neural network chip of a binary memristor

A neural network and binary neural technology, applied in the field of computer and electronic information, can solve the problems of consuming too many memristor units, complex network structure, complex regulation, etc., and achieve the effect of improving computing efficiency and speed

Active Publication Date: 2019-04-19
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0004] Neural networks based on memristors have been reported so far, such as single-layer perceptron [1], on-site training algorithm [2] and other methods, all of which are based on algorithms that can be accurately calculated by traditional digital circuits. The weights mapped to the neural network require high accuracy, but at present, because there is still no general understanding of the memristor regulation mechanism, the performance of memristors made of different materials varies greatly, and generally speaking, it is still impossible to achieve For the precise control of the resistance value, although some reports have proposed some solutions, such as small voltage step-by-step control [3], differential pair [1] [2], read check after writing [3], etc., but these methods are not feasible. To avoid problems such as narrow algorithm applicability, complex control, more memristor units, and complex network structure, there is still a long way to go before the actual large-scale application of traditional neural network algorithms for memristors

Method used

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  • Neural network chip of a binary memristor
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Embodiment Construction

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0036] A X86-based Intel E5-2620V4 central processing unit is used for simulation with a 30*3 memristor cross-array structure.

[0037] Wherein, the design of central processing unit 1 can use ARM, X86 or MIPS framework, can be divided into a plurality of single-core or multi-core central processing units with high performance, high power consumption and low performance and low power consumption according to needs, and can be selected according to the heavy degree of tasks Processed by different CPU modules. An example can be given here: 2 strongest ARM Cortex-A72 cores, clocked at 2.5GHz; 2 enhanced A53e cores, clocked at 2.0GHz; 4 ordinary low-power A53 cores, clocked at 1.4GHz, together constitute the central processing unit 1.

[0038] Such as image 3 As shown, in this example for figure 2 The memristor chip in the memristor core 5 a...

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Abstract

The invention relates to the technical field of computers and electronic information, in particular to a neural network chip of a binary memristor. According to the invention, the switching ratio of the memristor is utilized, For example, a high resistance state and a low resistance state exist, the memristor is combined with the binary neural network to complete storage and operation on the memristors made of different materials, and the memristors are combined with the central processing unit to improve the calculation efficiency and speed of the neural network. Except the execution of a neural network algorithm, the method can also utilize a binary neural network architecture to carry out field programming similar to an FPGA. The method comprises the following steps: inputting a data stream subjected to special coding processing, carrying out on-site learning according to a binarization neural network method by comparing an output result of the data stream, stopping learning when the correct rate reaches 100%, and executing a corresponding function by the network.

Description

technical field [0001] The invention relates to the technical field of computer and electronic information, in particular to a neural network chip of a binary memristor. Background technique [0002] Currently, neural network operations are basically based on central processing units (CPUs) and graphics processing units (GPUs). No matter which kind of hardware the neural network is based on, its operation belongs to digital matrix vector multiplication, and the computing hardware needs to provide accurate synaptic weight representation, otherwise it will bring extremely serious deviations to the neural network operation. [0003] The central processing unit (CPU) is limited by the bandwidth limit of serial processing and data reading when performing matrix-vector multiplication, and the operation efficiency is low; although the graphics processing unit (GPU) has high parallel computing efficiency when performing matrix-vector multiplication, its High energy consumption. Us...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 帅垚乔石珺彭赟吴传贵罗文博王韬张万里梁翔潘忻强
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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