Binary neural network acceleration method and system based on FPGA

A binary neural network and acceleration system technology, which is applied in FPGA-based binary neural network acceleration methods and systems, can solve the problems of convolutional neural network deployment difficulties, difficulty in achieving real-time effects, and consumption of computing resources. The effect of reducing communication costs, increasing convolution calculation speed, and improving detection speed

A binary neural network and acceleration system technology, which is applied in FPGA-based binary neural network acceleration methods and systems, can solve the problems of convolutional neural network deployment difficulties, difficulty in achieving real-time effects, and consumption of computing resources. The effect of reducing communication costs, increasing convolution calculation speed, and improving detection speed

CN110458279AActive Publication Date: 2019-11-15武汉魅瞳科技有限公司
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  • Binary neural network acceleration method and system based on FPGA
  • Binary neural network acceleration method and system based on FPGA
  • Binary neural network acceleration method and system based on FPGA

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Embodiment Construction

[0039] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0040] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other. The present invention will be further described in detail below in combination with specific embodiments.

[0041] figure 1 It is a structural schematic diagram of an FPGA-based binary neural network acceleration system according to an embodiment of the present invention. Such as figure 1 As shown, a binary neural network acceleration system based on FPGA, the system includes a convolu...

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Abstract

The invention discloses a binary neural network acceleration system based on an FPGA. A convolution kernel parameter acquisition module, a binarization convolution neural network structure and a cachemodule which are formed by an FPGA are utilized. The cache module is an on-chip memory of the FPGA; each module obtains an input feature map of a to-be-processed picture, obtains a convolution calculation logic rule and correspondingly carries out binarization convolution calculation. The FPGA traverses convolution calculation of a plurality of threads according to a convolution calculation logicrule. The output feature map data of the to-be-processed image is obtained, and the calculated amount of each layer in the binary neural network is completely unloaded to the on-chip memory through the overall architecture without depending on the interaction between the off-chip memory and the on-chip memory, so that the communication cost between memories is reduced, the calculation efficiencyis greatly improved, and the detection speed of the to-be-detected image is increased.

Description

technical field [0001] The invention belongs to the field of image processing, and in particular relates to an FPGA-based binary neural network acceleration method and system. Background technique [0002] Significant advances in artificial intelligence technology have begun to benefit all aspects of human life. From a vacuum robot in your home to an entire set of smart production equipment in a factory, many tasks in the world have already achieved a high degree of automation. Deep learning plays a pivotal role in this great technological revolution, and it has a wide range of applications in face recognition, object detection, image processing, and other fields. The main algorithm used is the convolutional neural network. This deep learning algorithm with better performance has been deployed in a large number of PCs, mobile phones and embedded dedicated accelerators to achieve various intelligent computing tasks. A better acceleration effect has been achieved. [0003] ...

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Application Information

Patent Timeline
15 Nov 2019
Publication
CN110458279A
IPC
G06N3/04; G06N3/063
CPC
G06N3/063; G06N3/045; Y02D10/00
Inventors
李开; 邹复好