Binary neural network acceleration method and system based on FPGA

Abstract

The invention discloses a binary neural network acceleration system based on an FPGA. A convolution kernel parameter acquisition module, a binarization convolution neural network structure and a cachemodule which are formed by an FPGA are utilized. The cache module is an on-chip memory of the FPGA; each module obtains an input feature map of a to-be-processed picture, obtains a convolution calculation logic rule and correspondingly carries out binarization convolution calculation. The FPGA traverses convolution calculation of a plurality of threads according to a convolution calculation logicrule. The output feature map data of the to-be-processed image is obtained, and the calculated amount of each layer in the binary neural network is completely unloaded to the on-chip memory through the overall architecture without depending on the interaction between the off-chip memory and the on-chip memory, so that the communication cost between memories is reduced, the calculation efficiencyis greatly improved, and the detection speed of the to-be-detected image is increased.

Description

technical field [0001] The invention belongs to the field of image processing, and in particular relates to an FPGA-based binary neural network acceleration method and system. Background technique [0002] Significant advances in artificial intelligence technology have begun to benefit all aspects of human life. From a vacuum robot in your home to an entire set of smart production equipment in a factory, many tasks in the world have already achieved a high degree of automation. Deep learning plays a pivotal role in this great technological revolution, and it has a wide range of applications in face recognition, object detection, image processing, and other fields. The main algorithm used is the convolutional neural network. This deep learning algorithm with better performance has been deployed in a large number of PCs, mobile phones and embedded dedicated accelerators to achieve various intelligent computing tasks. A better acceleration effect has been achieved. [0003] ...

AI Technical Summary

Problems solved by technology

[0004] However, all such mobile and embedded computing devices can only provide limited computing power and on-chip storage with a small capacity.

As the model structure of the convolutional neural network becomes more and more complex, the number of model layers becomes deeper, and the amount of model parameters increases, the deployment of convolutional neural networks on mobile and embedded terminals becomes more and more complex. difficulty

The huge amount of calculations all use 32bit floating-point numbers as operands to run on lightweight chips, which undoubtedly consumes a huge amount of computing resources, and it is also difficult to achieve better real-time results

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